Reissue
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Amended patent claims 1-16 and new claims 17-30 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-7 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 2012/0068350 to Kim et al. (hereinafter Kim ‘350) in view of EP 1942365 to Kim et al. (hereinafter Kim EP).
With respect to claims 1, 4, 10, and 11, Kim ‘350 teaches a pre-conductive array (matrix arrangement of regions 240) disposed on a target circuit substrate 205, the pre-conductive array comprising: a plurality of conductive electrode groups 217,270 disposed on the target circuit substrate 205, wherein a first distance L1 is provided between every two of the plurality of conductive electrode groups (see annotated Figure 2B below), and each of the plurality of conductive electrode groups comprises at least a pair of conductive electrodes. Kim ‘350 does not teach a protrusion pattern above the conductive electrodes and instead of conductive particles Kim ‘350 discloses solder bumps 270 on electrode pads 217 to connect substrate 205 to solder material 170 on lower substrate 105. See Figure 3;
PNG
media_image1.png
909
975
media_image1.png
Greyscale
paras [0070-0090].
Kim EP discloses a means of connecting a chip 41 to a TFT substrate 81 using conductive particles. The chip 41 includes metal bumps 53 in electrical connection with electrode pads 43. A resin layer 60 comprising a protrusion pattern is disposed above the conductive electrode/metal bump 53 such that the conductive particles 30 are limited by the protrusion pattern 60 to be above the protrusion pattern. See Figures 9 and 10; para [0052]. The layer 60 is disclosed by Kim to assure conductive particles 30
PNG
media_image2.png
305
404
media_image2.png
Greyscale
PNG
media_image3.png
296
414
media_image3.png
Greyscale
“are in good electrical contact with the electrode pads” (para [0052]).
Further, Kim EP teaches that use of the conductive particles with the metal bumps permits the bumps to “have a fine pitch, so that chip size may be reduced to increase the number of net dies per wafer, thereby reducing manufacturing cost.” See col.11, lines 1-9. Thus, it would have been obvious to replace the opposing bumps of Kim ‘350 with the single bump and conductive particles of Kim so as to place dies closer together, increasing the number of dies per wafer.
When replacing the solder bumps of Kim ‘350 with the bump and conductive particles of Kim EP, at least one conductive particle will be disposed on each of the pairs of the conductive electrodes wherein the conductive particles and the corresponding pair of the conductive electrodes form pre-conductive structures, and the pre-conductive structures form the pre-conductive array. As to the density of conductive particles, when the array of Kim ‘350 (shown in Figure 2B) is modified by Kim EP such that each electrode has at least one conductive particle therein, a first density is defined to represent a number of the plurality of conductive particles within a unit area of each of the pre-conductive structures, a second density is defined to represent a number of the plurality of conductive particles within a unit area between two of the pre-conductive structures, and the first density is greater than the second density. Since no conductive particles are located between each conductive structure, the first density will necessarily be larger than the second density which includes the empty areas between adjacent conductive structures.
As to claims 2 and 3, each of the plurality of conductive electrode groups of Kim ‘350 comprises multiple pairs of conductive electrodes, a second distance L2 is provided between adjacent two pairs of the conductive electrodes, and a third distance L3 is provided between two of the conductive electrodes of each pair. See Annotated Figure 2B above.
With respect to claims 5-7 and 12-14, the resin layer 60 is disclosed by Kim EP to be an adhesive (e.g. contact layer). As shown in Figure 10, the contact layer between two adjacent electrodes is removed in order to prevent adhesion of conductive particles and subsequent electrical shorts. See para [0065]. It would have been obvious to prevent adhesion of conductive particles between all pre-conductive structures of the combination for the same reason.
Claim(s) 1-7 and 10-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘350 in view of US 5,034,245 to Matsubara (hereinafter Matsubara).
With respect to claims 1, 4, 10, and 11, Kim ‘350 teaches a pre-conductive array (matrix arrangement of regions 240) disposed on a target circuit substrate 205, the pre-conductive array comprising: a plurality of conductive electrode groups 217,270 disposed on the target circuit substrate 205, wherein a first distance L1 is provided between every two of the plurality of conductive electrode groups (see annotated Figure 2B below), and each of the plurality of conductive electrode groups comprises at least a pair of conductive electrodes. Kim ‘350 does not teach a protrusion pattern above the conductive electrodes and instead of conductive particles Kim ‘350 discloses solder bumps 270 on electrode pads 217 to connect substrate 205 to solder material 170 on lower substrate 105. See Figure 3;
PNG
media_image1.png
909
975
media_image1.png
Greyscale
paras [0070-0090].
Matsubara teaches a protrusion pattern 13b over conductive electrodes 12. Conductive particles 14 are located on and in the protrusions 13b and limited thereby. See col.5, lines 24-31. Note that Matsubara discloses particles located on protecting layer 16 are removed. See
PNG
media_image4.png
296
578
media_image4.png
Greyscale
col.5, lines 10-18. It would have been obvious to replace the solder bumps of Kim ‘350 with the conductive particles of Matsubara, as Matsubara discloses that solder connections may cause thermal damage whereas conductive particles “improve the reliability with which the projections of respective electrodes which are formed of the conductive particles are connected…In consequence, productivity increases and cost decreases.” See col.2, lines 9-17.
When replacing the solder bumps of Kim ‘350 with the bump and conductive particles of Matsubara, at least one conductive particle will be disposed on each of the pairs of the conductive electrodes wherein the conductive particles and the corresponding pair of the conductive electrodes form pre-conductive structures, and the pre-conductive structures form the pre-conductive array. As to the density of conductive particles, when the array of Kim ‘350 (shown in Figure 2B) is modified by Matsubara such that each electrode has at least one conductive particle therein, a first density is defined to represent a number of the plurality of conductive particles within a unit area of each of the pre-conductive structures, a second density is defined to represent a number of the plurality of conductive particles within a unit area between two of the pre-conductive structures, and the first density is greater than the second density. Since no conductive particles are located between each conductive structure, the first density will necessarily be larger than the second density which includes the empty areas between adjacent conductive structures.
As to claims 2 and 3, each of the plurality of conductive electrode groups of Kim ‘350 comprises multiple pairs of conductive electrodes, a second distance L2 is provided between adjacent two pairs of the conductive electrodes, and a third distance L3 is provided between two of the conductive electrodes of each pair. See Annotated Figure 1A above.
With respect to claims 5-7 and 12-14, the resin layer 13b is disclosed by Matsubara to act as an adhesive (e.g. contact layer). Matsubara repeatedly teaches removing conductive particles located between adjacent electrodes and the desire to prevent electrical shorts. See col.1, lines 59-64; col.2, lines 5-6 and 27-29; col.5, lines 14-18. It would have been obvious to prevent adhesion of conductive particles between all pre-conductive structures for the same reason.
Claim(s) 8, 9, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim ‘350 in view of Kim EP or Matsubara as applied to claims 1 and 10 above, and further in view of US 2015/0308511 to Ishimatsu (hereinafter Ishimatsu).
The combination of Kim ‘350 with Kim EP or Matsubara does not teach a second contact layer covering the first contact layer.
PNG
media_image5.png
240
522
media_image5.png
Greyscale
PNG
media_image6.png
328
576
media_image6.png
Greyscale
Ishimatsu discloses an electrode 58 disposed on substrate 54 wherein a first contact layer 5 comprises a protrusion pattern 15,15 (Figure 8A) and a second contact layer 8 covers the first contact layer 5. See Figure 10. As shown in Figures 8A and 8B, the conductive particles 3 are limited by the protrusion pattern and the two contact layers having a corresponding pattern shape.
Layers 5,8 are resins and together hold the conductive particles 3 therebetween and prevent their movement, assuring “good connectivity” and “electrical and mechanical connection reliability…over a long period of time.” See paras [0089-0090]. For this reason, it would have been obvious to modify the combinations of Kim ‘350 with either of Kim or Matsubara with the second resin layer of Ishimatsu, assuring electrical and mechanical connection reliability over a long period of time.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 and 10-14 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-4, 6, and 7 of copending Application No. 18/752,520 in view of EP 1942365 to Kim et al. (hereinafter Kim EP) or US 5,034,245 to Matsubara (hereinafter Matsubara).
The limitations of claims 1-4, 10, and 11 are fully recited by claims 1-4, 6, and 7, respectively of the copending ‘520 application except that the copending application does not recite “at least a layer comprising a protrusion pattern above the conductive electrodes” such that a conductive particle is “limited by the protrusion pattern inside or above the protrusion pattern.”
Kim EP and Matsubara are relied upon as set forth above.
It would have been obvious to modify the pre-conductive array of claim 1 with the protrusion pattern layer 60 of Kim EP as being disclosed by Kim EP to assure conductive particles 30 “are in good electrical contact with the electrode pads” (para [0052]). Alternatively, one would have found it obvious to modify the pre-conductive array of claim 1 with the protrusion pattern layer 13 of Matsubara which is disclosed to embed and adhere the conductive particles only over the electrodes, thereby preventing electrical shorts. See col.1, line 59 to col.2, line 17.
With respect to claims 5-7 and 12-14, the claims of the ‘520 copending application do not recite that there are areas with no contact layer. Kim EP teaches the resin layer 60 is an adhesive (e.g. contact layer) and as shown in Figure 10, the contact layer between two adjacent electrodes is removed in order to prevent adhesion of conductive particles and subsequent electrical shorts. See para [0065]. It would have been obvious to prevent adhesion of conductive particles between all pre-conductive structures of the ‘520 copending claims for the same reason.
Alternatively, the resin layer 13b of Matsubara is an adhesive (e.g. contact layer). Matsubara repeatedly teaches removing conductive particles located between adjacent electrodes and the desire to prevent electrical shorts. See col.1, lines 59-64; col.2, lines 5-6 and 27-29; col.5, lines 14-18. It would have been obvious to prevent adhesion of conductive particles between the pre-conductive structures of the ‘520 copending claims for the same reason.
This is a provisional nonstatutory double patenting rejection.
Claims 8, 9, 15, and 16 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1 and 5 of copending Application No. 18/752,520 in view of Kim EP or Matsubara, and further in view of US 2015/0308511 to Ishimatsu (hereinafter Ishimatsu).
The claims of the ‘520 copending application as modified by Kim EP or Matsubara does not teach a second contact layer covering the first contact layer.
Ishimatsu is relied upon as set forth above.
It would have been obvious to modify the combinations supra with the second resin layer of Ishimatsu, assuring electrical and mechanical connection reliability over a long period of time.
This is a provisional nonstatutory double patenting rejection.
Allowable Subject Matter
Claims 17-30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 17 and 24 recite “…wherein one or more of micro semiconductor structures are disposed corresponding to a part or all of the pre-conductive array of the target circuit substrate, and wherein each of the micro semiconductor structures has an electrode, and the electrode of each of the micro semiconductor structures and a corresponding pre-conductive structure of the target circuit substrate together form a conductive structure.”
Kim ‘350 is directed to semiconductor packages and electronic devices, including CPUs and logic devices. Kim ‘350 does not teach or suggest disposing array-type micro-semiconductor structures, each having a pair of electrodes, on corresponding pre-conductive structures of the target circuit substrate to form a conductive structure, as required by claim 13. Kim EP likewise does not teach or suggest disposing micro-semiconductor structures in the manner claimed.
Claims 18-23 and 25-30 are likewise free of the art as depending from one of claims 17 or 24.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-16 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant is reminded of the continuing obligation under 37 CFR 1.178(b), to timely apprise the Office of any prior or concurrent proceeding in which Patent No. 10,854,566 is or was involved. These proceedings would include any trial before the Patent Trial and Appeal Board, interferences, reissues, reexaminations, supplemental examinations, and litigation.
Applicant is further reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is material to patentability of the claims under consideration in this reissue application.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to ELIZABETH MCKANE whose telephone number is
(571) 272-1275. The examiner can normally be reached on Mon-Thurs; 6:30 am -
4:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor Patricia Engle can be reached on 571-272-6660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of any application may be obtained from the
Patent Center at https://patentcenter.uspto.gov.
Should you have questions, contact the Electronic Business Center (EBC) at
866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service
Representative or access to the automated information system, call 800-786-9199 (IN
USA OR CANADA) or 571-272-1000.
/ELIZABETH L MCKANE/Specialist, Art Unit 3991
Conferees:
/LEE E SANDERSON/Reexamination Specialist, Art Unit 3991
/Patricia L Engle/SPRS, Art Unit 3991