DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement (lDS) submitted on June 25, 2024 is in compliance with the provisions of 37 CFR 1.97 and has been considered by the Examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Oike et al. (US Pub. 2010/0259662), in view of Li (US Pub. 2012/0188424).
In regard to claim 1, note Oike discloses an imaging device comprising a pixel array in which pixels including photoelectric conversion elements that perform photoelectric conversion are disposed in a matrix (paragraph 0054, and figures 1-2: 110/110a), wherein the photoelectric conversion elements of a plurality of the pixels include a floating diffusion that accumulates photoelectrically converted charge (paragraphs 0060, 0064, 0067, and figure 2: FD), vertical signal lines that output signals based on the charge accumulated in the floating diffusion to the outside are wired to each column of the pixel array (paragraph 0058, and figures 1-2: VSL), a column selection signal line that transmits a selection control signal selecting one of a plurality of vertical signal lines adjacent in a row direction is wired within a region of the pixel array (paragraphs 0068-0075, and figures 1-2: LSEL), and one column processing circuit that processes the signal is provided for the plurality of vertical signal lines selected by the selection control signal (paragraphs 0058, 0053, 0094, and figure 1: 140; one A/D converter 140 is provided for plural vertical signal lines VSL).
Therefore, it can be seen that the primary reference fails to explicitly disclose that the photoelectric conversion elements of a plurality of the pixels adjacent in a column direction share a floating diffusion.
In analogous art, Li discloses an imaging device comprising a pixel array in which pixels including photoelectric conversion elements that perform photoelectric conversion are disposed in a matrix (paragraph 0022, and figure 2: 230), wherein the photoelectric conversion elements of a plurality of the pixels adjacent in a column direction share a floating diffusion (paragraphs 0004, 0032, and figure 3: 320). Li teaches that the use of photoelectric conversion elements of a plurality of the pixels adjacent in a column direction sharing a floating diffusion is conventional in the art. Additionally, the Examiner notes that the use of photoelectric conversion elements of a plurality of the pixels adjacent in a column direction sharing a floating diffusion is common in the art in order to reduce the number of components required to form each of the pixels of the imaging device, and thereby increase available space for the photosensitive area of the pixel. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference such that the photoelectric conversion elements of a plurality of the pixels adjacent in a column direction share a floating diffusion in order to reduce the number of components required to form each of the pixels of the imaging device, and thereby increase available space for the photosensitive area of the pixel, as is known in the art.
In regard to claim 2, note Li discloses that the pixels sharing the floating diffusion are two adjacent pixels in the column direction (figure 3: 312, 316, 320; pixels 312 and 316, which are in the same column, share the floating diffusion 320).
In regard to claim 3, note Oike discloses that the plurality of vertical signal lines selected by the selection control signal are connected to one shared vertical signal line outside the region of the pixel array, and the shared vertical signal line is connected to the column processing circuit (paragraphs 0086-0095, and figure 1: 130, 140; plural vertical signal lines VSL are connected to one shared vertical signal line formed as the output of the multiplexer 130).
In regard to claim 4, note Oike discloses that the column processing circuit is disposed in parallel with pixel columns of the pixel array outside the region of the pixel array (paragraph 0094, and figure 1: 110a, 140; the A/D converters are connected in parallel with the pixel columns).
In regard to claim 5, note Oike discloses the imaging device of figures 1-2, as discussed with respect to claim 1 above. Oike additionally discloses an imaging device comprising an upper substrate on which the pixel array is disposed (paragraphs 0149-0154, and figure 12: “first semiconductor layer”, 110c), and a lower substrate on which the column processing circuit is disposed (paragraphs 0149-0154, and figure 12: “second semiconductor layer”, 140c; the A/D converters 140 are disposed on the second substrate), wherein the pixel array is laminated on the upper substrate (paragraphs 0149-0154, and figure 12: 110c), and the column processing circuit of the lower substrate is disposed in parallel with pixel columns of the pixel array of the upper substrate (paragraphs 0149-0154, and figure 12: 140c; the A/D converters 140 are connected in parallel with the pixel columns). Oike teaches that the use of first and second stacked substrates, having the pixel array and the column processing circuitry disposed thereon, respectively, is preferred in order to enable highly parallel AD conversion against a limited number of wired liens, thereby realizing a faster imaging (paragraph 0149-0154). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the embodiment of Oike to include the use of first and second stacked substrates, having the pixel array and the column processing circuitry disposed thereon, respectively, in order to enable highly parallel AD conversion against a limited number of wired liens, thereby realizing a faster imaging.
In regard to claim 6, note Oike discloses a transfer control signal line that selects one of the pixels, and transmits a transfer control signal for outputting the signal from the selected pixel to the outside, wherein the transfer control signal line is wired to pass through a region of the pixels (paragraphs 0063, 0071-0075, and figure 2: LTRG). Additionally, Li discloses a transfer control signal line that selects one of shared pixels, which are the plurality of pixels sharing the floating diffusion, and transmits a transfer control signal for outputting the signal from the selected pixel to the outside, wherein the transfer control signal line is wired to pass through a region of the shared pixels (paragraphs 0032-0033, and figure 3: TX).
In regard to claim 7, note Li discloses that the column selection signal line is wired to pass through the region of the shared pixels (paragraph 0032, and figure 3: “Row”).
In regard to claim 8, note Oike discloses a reset signal line that resets the charge accumulated in the floating diffusion (paragraph 0065, figure 2: RST). Additionally, Li discloses a reset signal line that resets the charge accumulated in the floating diffusion, wherein the reset signal line is wired to pass through the region of the shared pixels (paragraphs 0020, 0028, and figure 3: RST).
In regard to claim 9, note Li discloses that the reset signal line is wired to pass through a region of one pixel in the region of the shared pixels (figure 3: RST; the reset signal line passes through a first pixel region of the shared pixels), and the column selection signal line is wired to pass through a region of another pixel in the region of the shared pixels (figure 3: “Row”; the row select line passes through another pixel region of the shared pixel).
In regard to claim 10, note Li discloses that the shared pixels are two of the pixels adjacent in the column direction (paragraph 0024, and figure 3: 312, 316; the pixels 312 and 316 of the shared pixel are adjacent in the column direction), a reset signal line wired in to the shared pixels (figure 3: RST), and the column selection signal line is wired to pass through each region of the shared pixels (figure 3: “Row”).
Therefore, it can be seen that the primary reference fails to explicitly disclose that the reset signal line is wired in a middle position between the shared pixels.
However, the Examiner notes that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the primary reference, such that the reset signal line is wired in a middle position between the shared pixels, since it has been held that rearranging parts of an invention involves only routine skill in the art.
In regard to claim 11, note Oike discloses that the column selection signal line includes a signal line that transmits an odd column selection control signal for selecting an odd column vertical signal line of two of the vertical signal lines adjacent in the row direction (paragraphs 0072-0078, and figures 1-2: LSEL0, LSEL2; the signal lines LSEL0 and LSEL2 control the connection of pixels in the odd columns, to connect to the vertical signal lines), and a signal line that transmits an even column selection control signal for selecting an even column vertical signal line of two of the vertical signal lines adjacent in the row direction (paragraphs 0072-0078, and figures 1-2: LSEL1, LSEL3; the signal lines LSEL1 and LSEL3 control the connection of pixels in the odd columns, to connect to the vertical signal lines), and the odd column selection control signal and the even column selection control signal are controlled in a time-division manner (paragraphs 0072-0078, 0082, 0114; the odd and even columns are controlled to be output in a time-division manner).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2021/0400224: note the use of an imaging device that includes stacked substrates, as well as shared readout circuitry.
US 11,588,988: note the use of an imaging device that includes the use of one column processing circuit that processes the signals from plural vertical signal lines.
US 2023/0283918: note the use of an imaging device that includes the use of one column processing circuit that processes the signals from plural vertical signal lines.
US 12,532,092: note the use of an imaging device that includes the use of shared readout circuitry within the pixels, as well as one column processing circuit that processes the signals from plural vertical signal lines.
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/CHRISS S YODER III/Examiner, Art Unit 2638