DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This non-final office action is responsive to Applicants' application filed on 06/25/24. Claims 1-20 are presented for examination and are pending for the reasons indicated herein below.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7-8, 14, 15-18, 20 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Joshi et al. (US 20210311513 A1)
Regarding claim 1. Joshi teaches a circuit [fig 1-3, coupled is interpreted as connected between any intervening elements] comprising: voltage source circuitry having a terminal [Vin];
a first transistor [fig 2, 208] having a first terminal [upper terminal (S)] and a control terminal [(D)], the control terminal of the first transistor coupled [gate coupled through 320 of 106 shown fig 3] to the terminal of the voltage source circuitry;
current mirror circuitry [310 of 106] having a first terminal and a second terminal, the first terminal of the current mirror circuitry coupled to the first terminal of the first transistor [upper terminal of 314];
and a second transistor [308 of 106] having a control terminal coupled to the second terminal of the current mirror circuitry [upper terminal of 310].
Regarding claim 2. Joshi teaches the circuit of claim 1, wherein the first transistor includes a second terminal, the second transistor includes a first terminal [upper terminal of 308], and the circuit further comprising:
a third transistor [210, fig 2] having a first terminal [upper terminal of 210] and a control terminal, the control terminal of the third transistor is coupled to the second terminal of the first transistor [coupled through gate of 208];
a resistor [fig 2, resistor of 208] having a first terminal [upper terminal] and a second terminal, the first terminal of the resistor is coupled to the first terminal of the third transistor;
and amplifier circuitry [fig 3, 306] having a first terminal and a second terminal, the first terminal of the amplifier circuitry coupled to the second terminal of the resistor, the second terminal [negative terminal of 306] of the amplifier circuitry coupled to the first terminal of the second transistor.
Regarding claim 7. Joshi teaches the circuit of claim 1, wherein the second transistor further has a first terminal, and the circuit further comprising:
a third transistor [210] having a first terminal and a control terminal, the control terminal of the third transistor is coupled to the first terminal of the second transistor;
a fourth transistor [318] having a first terminal [lower terminal], a second terminal, and a control terminal, the first terminal of the fourth transistor is coupled [coupled through upper terminal of 318 to vin of 210] to the first terminal of the third transistor and the control terminal of the fourth transistor;
and current source circuitry [206] having a terminal [220] coupled to the second terminal of the current mirror circuitry, the control terminal of the second transistor, and the second terminal of the fourth transistor.
Regarding claim 8. Joshi teaches an apparatus [fig 1-3, 100, coupled is interpreted as connected between intervening elements] comprising: a transistor [208, fig 2] having a first terminal and a control terminal;
a feedback terminal [see fb of 202];
error amplifier circuitry [202] having a first terminal [+ terminal] and a second terminal, the first terminal of the error amplifier circuitry coupled to the feedback terminal;
buffer circuitry [206] having a first terminal and a second terminal;
and amplifier circuitry [306 of 106, fig 3] having a first terminal and a second terminal, the first terminal of the amplifier circuitry coupled to the control terminal of the transistor [output terminal of 306 with gate of 208 is coupled through 308, 307, 320] and the first terminal of the buffer circuitry [gate of 208 is also coupled to buffer],
the second terminal [+] of the amplifier circuitry coupled to the second terminal of the error amplifier circuitry and the second terminal of the buffer circuitry [+ terminal of 306 with output terminal of 202 is coupled through 304, 220, Vout, 208 and 206].
Regarding claim 14. Joshi teaches the apparatus of claim 8, wherein the apparatus is linear regulator circuitry [fig 1 is a linear regulator].
Regarding claim 15. Johsi teaches an apparatus [fig 1, coupled is interpreted as connected between intervening elements] comprising: a first input terminal configured to receive an input voltage [vin];
an output terminal configured to supply an output voltage [vout];
a second input terminal configured to supply a feedback voltage [fb to 202], the feedback voltage proportional to the output voltage;
regulator circuitry [linear reg of fig 2] coupled to the first input terminal, the second input terminal, and the output terminal, the regulator circuitry configured to: generate the output voltage using the input voltage [function of device] based on a first voltage [voltage value of vout];
generate a second voltage [V_ea] based on a difference between the feedback voltage and a first reference voltage;
and adjust the first voltage based on the second voltage [implicit, by means of 208];
and dropout loop circuitry [106, 204, 222, 214, 212 make this device] coupled to the first input terminal and the regulator circuitry, the dropout loop circuitry configured to: detect dropout conditions [vout of 214] based on the first voltage and a second reference voltage [vref of 214];
and after detecting the dropout conditions, compensate the second voltage with a current [output of 204].
Regarding claim 16. Joshi teaches the apparatus of claim 15, wherein the second reference voltage is a dropout reference voltage [implicit from claims 13/14], the dropout loop circuitry is further configured to: generate a third reference voltage corresponding to the dropout conditions [Vpulldown];
and generate the dropout reference voltage by level shifting the third reference voltage [0025].
Regarding claim 17. Joshi teaches the apparatus of claim 15, wherein the regulator circuitry is further configured to adjust the first voltage [value of vout] based on the second voltage [i.e. Vea] and the current [current from 204] from the dropout loop circuitry.
Regarding claim 18. Joshi teaches the apparatus of claim 15, wherein the dropout loop circuitry is further configured to: compare the first voltage to the second reference voltage [214 compares vout with vref];
and determine the regulator circuitry is operating in the dropout [i.e. over/under shoot state] conditions in response to the first voltage being a threshold voltage less than the second reference voltage [¶34].
Regarding claim 20. Joshi teaches the apparatus of claim 15, wherein the regulator circuitry is further configured to continue to regulate the output voltage using the first voltage and the second voltage despite the dropout conditions and responsive to the current from the dropout loop circuitry [function of device as shown in fig 8A-8B, ¶34].
Allowable Subject Matter
Claims 3-6,9-13 and 19 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, and if the claim objections stated above were overcome.
Examiner Note
The examiner cites particular columns and lines numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bryan Perez whose telephone number is (571)272-8837. The examiner can normally be reached on Mon.-Fri. (7:30 – 5:00).
If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Crystal Hammond, can be reached on (571) 270-1682. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN R PEREZ/Examiner, Art Unit 2838