DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-33 are pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3, 14, 18, 19, 20, 22 and 33 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pant et l. (hereinafter Pant) (US 20240429908 A1).
As to claim 1, Pant teaches an electronic device, comprising:
a plurality of power supply phase circuits [FIG. 1: V1 and V2];
a voltage rail [FIG.1: connection between MUX and first circuit];
a first multiplexer [FIG. 1: power MUX 130] coupled between at least one of the plurality of power supply phase circuits and the voltage rail [FIG.1]; and
a controller [FIG.1: MUX controller 140] configured to:
determine a multiplexer configuration of the first multiplexer to direct current from the at least one of the plurality of power supply phase circuits to the voltage rail [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140. This allows the multiplexer controller 140 to switch the first circuit 150 between the first power rail 110 and the second power rail 115 (and hence switch the first circuit 150 between the first supply voltage and the second supply voltage) using the power multiplexer 130.”], wherein a first operating region of each of the plurality of power supply phase circuits is identified based on a power characteristic of each of the plurality of power supply phase circuits [0041: “the voltage controller 350 keeps the voltage level of the second supply voltage (labeled “V2”) at or above a first threshold voltage level corresponding to the minimum voltage level…the voltage controller 350 may set the first supply voltage to a voltage level above or below the first threshold voltage level depending on the performance mode of the second circuit 315.”], and wherein the controller is configured to identify the multiplexer configuration based on the first operating region [voltage level of first and second supply voltage] [0024: “ For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters. The one or more parameters may include the voltage level of the first supply voltage, the voltage level of the second supply voltage, a transition of the first supply voltage or the second supply voltage from one voltage level to another voltage level, a threshold voltage level, or any combination thereof.”] [0046: “during the transition of the voltage level of the first supply voltage, the multiplexer controller 140 compares the voltage level of first supply voltage with the voltage level of the second supply voltage, and causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”]; and
control the first multiplexer based on the multiplexer configuration [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140…For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters.”] [0046: “causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”].
As to claim 3, Pant teaches wherein the first operating region of each of the plurality of power supply phase circuits is associated with a power supply output current being more than a first current threshold and less than a second current threshold [FIGs. 9A and 9B].
As to claim 14, Pant teaches wherein the first multiplexer includes inputs coupled to outputs of at least a first phase circuit and a second phase circuit of the plurality of power supply phase circuits and an output coupled to the voltage rail [FIG. 1].
As to claim 18, Pant teaches wherein the first multiplexer is configured to direct current from each of the first phase circuit and the second phase circuit to the voltage rail [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140.”].
As to claim 19, Pant teaches wherein the plurality of power supply phase circuits are part of a power management integrated circuit (PMIC) [0022: “The voltage generator 120 may be implemented in a power management integrated circuit (PMIC).”], and wherein the first multiplexer is part of the PMIC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)). The voltage generator 120 may also be integrated on the chip or may be external to the chip (i.e., located off chip).”].
As to claim 20, Pant teaches a method for power generation, comprising:
determining at least one multiplexer configuration of one or more multiplexers to direct current from at least one of a plurality of power supply phase circuits to at least one of a plurality of voltage rails [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140. This allows the multiplexer controller 140 to switch the first circuit 150 between the first power rail 110 and the second power rail 115 (and hence switch the first circuit 150 between the first supply voltage and the second supply voltage) using the power multiplexer 130.”], wherein a first operating region of each of the plurality of power supply phase circuits is identified based on a power efficiency of each of the plurality of power supply phase circuits [0041: “the voltage controller 350 keeps the voltage level of the second supply voltage (labeled “V2”) at or above a first threshold voltage level corresponding to the minimum voltage level…the voltage controller 350 may set the first supply voltage to a voltage level above or below the first threshold voltage level depending on the performance mode of the second circuit 315.”] [0031: “the voltage controller 350 may independently set the voltage levels of the first supply voltage and second supply voltage. This allows the second circuit 315 and the third circuit 320 to operate in different voltage domains (also referred to as power domains) for improved power efficiency. For example, when the second circuit 315 operates in a high performance mode requiring a higher voltage level than the third circuit 320, the voltage controller 350 may set the first supply voltage to a higher voltage level than the second supply voltage. This improves power efficiency by allowing the third circuit 320 to operate at a lower voltage level than the second circuit 315, which reduces the power consumption of the third circuit 320.”], and wherein the at least one multiplexer configuration is determined based on the first operating region [voltage level of first and second supply voltage] [0024: “ For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters. The one or more parameters may include the voltage level of the first supply voltage, the voltage level of the second supply voltage, a transition of the first supply voltage or the second supply voltage from one voltage level to another voltage level, a threshold voltage level, or any combination thereof.”] [0046: “during the transition of the voltage level of the first supply voltage, the multiplexer controller 140 compares the voltage level of first supply voltage with the voltage level of the second supply voltage, and causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”]; and
controlling the one or more multiplexers based on the at least one multiplexer configuration [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140…For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters.”] [0046: “causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”].
As claim 22, Pant teaches wherein the first operating region of each of the plurality of power supply phase circuits is associated with a power supply output current being more than a first current threshold and less than a second current threshold [FIGs. 9A and 9B].
As to claim 33, Pant teaches a non-transitory computer-readable medium having instructions stored thereon, that when executed by one or more processors [0118], cause the one or more processors to:
determine at least one multiplexer configuration of one or more multiplexers to direct current from at least one of a plurality of power supply phase circuits to at least one of a plurality of voltage rails 0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140. This allows the multiplexer controller 140 to switch the first circuit 150 between the first power rail 110 and the second power rail 115 (and hence switch the first circuit 150 between the first supply voltage and the second supply voltage) using the power multiplexer 130.”], wherein an operating region of each of the plurality of power supply phase circuits is identified based on a power efficiency of each of the plurality of power supply phase circuits [0041: “the voltage controller 350 keeps the voltage level of the second supply voltage (labeled “V2”) at or above a first threshold voltage level corresponding to the minimum voltage level…the voltage controller 350 may set the first supply voltage to a voltage level above or below the first threshold voltage level depending on the performance mode of the second circuit 315.”] [0031: “the voltage controller 350 may independently set the voltage levels of the first supply voltage and second supply voltage. This allows the second circuit 315 and the third circuit 320 to operate in different voltage domains (also referred to as power domains) for improved power efficiency. For example, when the second circuit 315 operates in a high performance mode requiring a higher voltage level than the third circuit 320, the voltage controller 350 may set the first supply voltage to a higher voltage level than the second supply voltage. This improves power efficiency by allowing the third circuit 320 to operate at a lower voltage level than the second circuit 315, which reduces the power consumption of the third circuit 320.”], and wherein the at least one multiplexer configuration is determined based on the operating region [voltage level of first and second supply voltage] [0024: “ For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters. The one or more parameters may include the voltage level of the first supply voltage, the voltage level of the second supply voltage, a transition of the first supply voltage or the second supply voltage from one voltage level to another voltage level, a threshold voltage level, or any combination thereof.”] [0046: “during the transition of the voltage level of the first supply voltage, the multiplexer controller 140 compares the voltage level of first supply voltage with the voltage level of the second supply voltage, and causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”]; and
control the one or more multiplexers based on the at least one multiplexer configuration [0024: “The power multiplexer 130 is configured to selectively couple the first circuit 150 to the first power rail 110 or the second power rail 115 under the control of the multiplexer controller 140…For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters.”] [0046: “causes the power multiplexer 130 to switch between the first power rail 110 and the second power rail 115 when the voltage level of first supply voltage crosses the voltage level of the second supply voltage.”].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 2, 6-11, 21, 25-29, 32 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pant et l. (hereinafter Pant) (US 20240429908 A1) in view of Park et al. (hereinafter Park) (US 20170277238 A1).
As to claim 2, Pant does not teach wherein the controller is configured to determine the multiplexer configuration based on an amount of current supplied by each of the plurality of power supply phase circuits.
Park teaches multiplexer configuration being determined by a controller based on an amount of current supplied by each of the plurality of power supply phase circuits [0031: “the current and voltage characteristics supplied by a selected one of voltage rails 110, 112, and 114 are coupled through the selecting one of power multiplexers 122, 124, 126, and 128 to the power input of the corresponding computing device component. Each computing device component that is selectively coupled to one of voltage rails 110, 112, and 114 in this manner thus draws current through a selected one of voltage rails 110, 112, and 114 and, correspondingly, from a selected one of power supplies 116, 118, and 120.”] [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of determining mux configuration based on amount of current supplied by each of the plurality of power supply phase circuits as suggested in Park into Pant to implement power supply selection. One having ordinary skill in the art would have been motivated to make such modification to ensure the performance and safety of the power supplies.
As to claim 6, Pan in view of Park teaches wherein the voltage rail is one of a plurality of voltage rails [Pan, FIG. 3], and wherein, to determine the multiplexer configuration, the controller is configured to determine, based on a mode associated with the electronic device [Pant, 0041: “the voltage controller 350 may set the first supply voltage to a voltage level above or below the first threshold voltage level depending on the performance mode of the second circuit 315.”] [Pant, 0042: “the multiplexer controller 140 may couple the first circuit 150 to the first power rail 110 or the second power rail 115 based on the voltage level of the first supply voltage set by the voltage controller 350 and the first threshold voltage level.”], to at least one of: merge at least two of the plurality of voltage rails to receive current from the same one or more power supply phase circuits of the plurality of power supply phase circuits [Park, 0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”]; or merging at least two of the power supply phase circuits to supply the same voltage rail of the plurality of voltage rails.
As to claim 7, Park further teaches wherein the voltage rail is one of a plurality of voltage rails, and wherein the controller is configured to control the first multiplexer to combine at least two of the plurality of voltage rails to receive current from the same one or more power supply phase circuits of the plurality of power supply phase circuits [FIG. 3] [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
As to claim 8, Pant teaches wherein the plurality of voltage rails are associated with respective loads that are part of a system on chip (SoC), and wherein the first multiplexer are part of the SoC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)).”].
As to claim 9, Pant teaches wherein the first multiplexer is part of a core circuit of the SoC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)).”].
As to claim 10, Park further teaches wherein the controller is configured to control the first multiplexer to merge at least two of the plurality of power supply phase circuits to supply current for the voltage rail [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
As to claim 11, Pan teaches the electronic device of claim 10, further comprising a power management integrated circuit (PMIC) including the plurality of power supply phase circuits [0022: “The voltage generator 120 may be implemented in a power management integrated circuit (PMIC).”], and wherein the first multiplexer is part of the PMIC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)). The voltage generator 120 may also be integrated on the chip or may be external to the chip (i.e., located off chip).”].
As to claim 21, Park teaches wherein the at least one multiplexer configuration is further determined based on an amount of current supplied by each of the plurality of power supply phase circuits [0031: “the current and voltage characteristics supplied by a selected one of voltage rails 110, 112, and 114 are coupled through the selecting one of power multiplexers 122, 124, 126, and 128 to the power input of the corresponding computing device component. Each computing device component that is selectively coupled to one of voltage rails 110, 112, and 114 in this manner thus draws current through a selected one of voltage rails 110, 112, and 114 and, correspondingly, from a selected one of power supplies 116, 118, and 120.”] [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
As to claim 25, Park further teaches wherein the one or more multiplexers are controlled to combine at least two of the plurality of voltage rails to receive current from the same one or more power supply phase circuits of the plurality of power supply phase circuits [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
As to claim 26, Pant teaches wherein the plurality of voltage rails are associated with respective loads that are part of a system on chip (SoC), and wherein the one or more multiplexers are part of the SoC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)).”].
As to claim 27, Pant teaches wherein the one or more multiplexers are part of a core circuit of the SoC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)).”].
As to claim 28, Park teaches wherein the one or more multiplexers are controlled to merge at least two of the plurality of power supply phase circuits to supply current for the same voltage rail of the plurality of voltage rails [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”].
As to claim 29, Pant teaches wherein the plurality of power supply phase circuits are part of a power management integrated circuit (PMIC) [0022: “The voltage generator 120 may be implemented in a power management integrated circuit (PMIC).”], and wherein the one or more multiplexers are part of the PMIC [0025: “The power multiplexer 130, the first circuit 150, and the multiplexer controller 140 may be integrated on a chip (e.g., integrated in a system on a chip (SoC)). The voltage generator 120 may also be integrated on the chip or may be external to the chip (i.e., located off chip).”].
As to claim 32, Pant in view of Park teaches wherein determining the at least one multiplexer configuration comprises determining to merge at least two of the plurality of voltage rails to receive current from the same one or more power supply phase circuits of the plurality of power supply phase circuits [0034: “The control signal(s) 332 may close and open the power switches to selectively provide additional current, via connection(s) 324, from the shared secondary power supply 310 to one of the power rails 110, 112, and 114.”] or to merge at least two of the power supply phase circuits to supply the same voltage rail of the plurality of voltage rails, based on a mode associated with an apparatus including the plurality of the voltage rails.
Claim(s) 12, 13, 30, 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pant et l. (hereinafter Pant) (US 20240429908 A1) in view of Lambert et al. (hereinafter Lambert) (US20230026653 A1).
As to claim 12, Pant does not teach wherein the controller comprises a machine learning (ML) controller.
Lambert teaches that the controller comprises a machine learning (ML) controller [0007: “A controller (e.g., a BIOS and/or BMC) may control muxes within one or more components of an information handling system to perform channel swaps after determining a channel configuration through any number of algorithms. In one example, the controller may walk each channel through each lane direction while performing measurements on the channels to discover an optimal signal integrity before or after link training and determining a channel configuration based on the lane tests. In another example, the controller may use a trained machine learning (ML) by inputting information (e.g., measurement of figures of merits, device information, and/or channel physical characteristics) to the ML model and determining a channel configuration based on the ML model.”].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teaching of using machine learning controller as suggested in Lambert into Pant to implement MUX control. One having ordinary skill in the art would have been motivated to make such modification to improve adaptability and efficiency.
As to claim 13, Pant in view of Lamber teaches wherein the ML controller is configured to determine the multiplexer configuration based on one or more of: a current rating of at least one of the plurality of power supply phase circuits; an amount of current being supplied by at least one of the plurality of power supply phase circuits; current consumption associated with the voltage rail; a voltage associated with the voltage rail [0024: “ For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters. The one or more parameters may include the voltage level of the first supply voltage, the voltage level of the second supply voltage, a transition of the first supply voltage or the second supply voltage from one voltage level to another voltage level, a threshold voltage level, or any combination thereof.”]; a temperature of at least one of the plurality of power supply phase circuits; an operating frequency of at least one of the plurality of power supply phase circuits; a part type of a system on chip (SoC) associated with the voltage rail; or a mode associated with the SoC.
As to claim 30, Pant in view of Lambert teaches wherein the at least one multiplexer configuration is determined via inferencing by a machine learning (ML) model [0007: “A controller (e.g., a BIOS and/or BMC) may control muxes within one or more components of an information handling system to perform channel swaps after determining a channel configuration through any number of algorithms. In one example, the controller may walk each channel through each lane direction while performing measurements on the channels to discover an optimal signal integrity before or after link training and determining a channel configuration based on the lane tests. In another example, the controller may use a trained machine learning (ML) by inputting information (e.g., measurement of figures of merits, device information, and/or channel physical characteristics) to the ML model and determining a channel configuration based on the ML model.”].
As to claim 31, Pant in view of Lamber teaches wherein the at least one multiplexer configuration is determined via the ML model based on one or more of: a current rating of at least one of the plurality of power supply phase circuits; an amount of current being supplied by at least one of the plurality of power supply phase circuits; current consumption associated with at least one of the plurality of voltage rails; a voltage associated with at least one of the plurality of voltage rails [0024: “ For example, the multiplexer controller 140 may switch the first circuit 150 between the first power rail 110 and the second power rail 115 based on one or more parameters. The one or more parameters may include the voltage level of the first supply voltage, the voltage level of the second supply voltage, a transition of the first supply voltage or the second supply voltage from one voltage level to another voltage level, a threshold voltage level, or any combination thereof.”]; a temperature of at least one of the plurality of power supply phase circuits; an operating frequency of at least one of the plurality of power supply phase circuits;4 a part type of a system on chip (SoC) associated with the plurality of voltage rails; or a mode associated the SoC.33
Allowable Subject Matter
Claims 4, 5, 15-17, 23 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XUXING CHEN whose telephone number is (571)270-3486. The examiner can normally be reached M-F 9-5:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jaweed Abbaszadeh can be reached at 571-270-1640. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XUXING CHEN/ Primary Examiner, Art Unit 2176