Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed July 28, 2026 have been fully considered but they are not persuasive.
Applicant argues that the Kajita reference does not teach the newly added limitation “a step surface connecting an end of the first inclined surface and an end of the second inclined surface”, wherein “neither the second region (W2) nor the fourth region (W4) is connecting the end of the first region (W1) and the end of the fifth region (W5)”. The examiner respectfully disagrees. The stepped surface in figure 1b is considered to be a combination of sections W2, W3, and W4, which connect the ends of first inclined surface W1 and second inclined surface W5.
Applicant argues that the Kajita reference does not teach “a seed layer comprising a sputtered layer formed on the first inclined surface, step surface and second inclined surface of the inner wall surface”, wherein Kajita “teaches forming an electroless plating film (31) is formed on the inner wall (W) in the via hole (V) by electroless plating technique (i.e., a chemical process to deposit a metal in a solution)”. The examiner respectfully disagrees.
It is noted that the limitations of the method steps reciting "comprising a sputtered layer” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Furthermore, the reference Ikeda teaches in Col. 9, lines 39-41, that the seed layer 1001 is a sputtered film.
Applicant argues that the Kajita reference does not teach that the inorganic particles are dispersed in the resin, wherein Kajita “refers to Figs. 5(a0) and 5(b) and describes that the inorganic insulating layer (13) is formed such that the adjacent inorganic particles (20) are caused to be connected to each other at their mutually closest points. Thus, EP '158 describes the inorganic particles (20) firmly aggregated, rather than dispersed, in in the inorganic insulating layer (13)”. The examiner respectfully disagrees. In Col. 6 lines 30-35, Col. 7 lines 54-56, and Col. 8 lines 45-47, Kajita states that the inorganic particles (16, 23, 25) are spaced apart and dispersed in the resin (18, 22, 24).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajita (EP 2981158 B1) in view of Ikeda (US 9538642 B2).
Regarding claim 1, Kajita teaches a printed wiring board (Fig. 1b), comprising:
a first conductor layer (bottom 11);
a resin insulating layer (13, 14, 15) formed on the first conductor layer;
a second conductor layer (top 11) formed on the resin insulating layer; and
a via conductor (12) formed in the resin insulating layer such that the via conductor is
penetrating through the resin insulating layer and connecting the first conductor layer and the second conductor layer (Col. 5, lines 1-4),
wherein the resin insulating layer has a via hole (V) in which the via conductor is formed such
that an inner wall surface (W) in the via hole has a first inclined surface (W1) decreasing in diameter from the second conductor layer to a middle portion of the via hole in a thickness direction of the resin insulating layer (at W1 from a top down view, the bottom area of the via is smaller than the top area), a second inclined surface (W5) decreasing in diameter from the middle portion to the first conductor layer with a smaller diameter than an end part of the first inclined surface in the middle portion (at W5 from a top down view, the bottom area of the via is smaller than the top area), and a step surface connecting an end of the first inclined surface and an end of the second inclined surface (wherein the section of W including W2, W3, and W4 is the step surface).
Kajita does not teach that a via conductor includes a seed layer comprising a sputtered layer formed on the surface of the inner wall surface in the via hole, and a metal layer on the seed layer.
However, Ikeda teaches, in figure 9, that the via conductor (101b, 102b) includes a seed layer (1001) comprising a sputtered layer (Col. 9, lines 39-41; wherein the seed layer 1001 is a sputtered film) formed on the inner wall surface in the via hole (101a, 102a) and a metal layer (1002) on the seed layer (Col. 9 lines 20-26).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via conductor of Kajita to include a seed layer and metal on the seed layer, in order to improve adhesion and conductivity of the via.
It is noted that the limitations of the method steps reciting "comprising a sputtered layer” are process limitations in a product claim and is treated in accordance with MPEP 2113. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777Fo 2d 695,698 USPQ 964, 966 (Fed. Cir.1985). See also MPEP 2113.
Regarding claim 2, Kajita teaches the resin insulating layer is formed such that the via hole has a
first inclination angle (A1) of the first inclined surface with respect to the first conductor layer and a
second inclination angle (A2; Col. 10, lines 19-23) of the second inclined surface with respect to the first
conductor layer and that the second inclination angle is larger than the first inclination angle (Col. 10,
lines 19-23).
Regarding claims 3 and 8, Kajita teaches the resin insulating layer is formed such that the inner wall surface in the via hole (W) is a non-roughened surface (the inner wall of the resin layer has not been subjected to a roughening treatment).
Claim(s) 4, 9, and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajita (EP 2981158 B1) in view of Ikeda (US 9538642 B2), as applied to claims 1-3 and 8 above, and further in view of Murai (US 7759583 B2).
Regarding claims 4, 9, and 13, a modified Kajita teaches in figure 1b that the resin insulating layer includes resin (18, 22, 24) and inorganic particles (16, 23, 25) and is formed such that the inorganic particles have particle sizes in a range of 0.1 μm to 5.0 μm (wherein Col. 7, lines 23-25 states particles 21 are 0.5 μm to 5 μm; Col. 8, lines 24-25 states particles 23 are 0.05 μm to 0.7 μm; and Col. 8, lines 55-57 states particles 25 are 0.5 μm to 5 μm) and are dispersed in the resin (Col. 6 lines 30-35, Col. 7 lines 54-56, and Col. 8 lines 45-47; wherein the particles are spaced apart and dispersed in the resin).
Kajita fails to teach that the resin insulating layer is formed such that the inner wall surface in the via hole includes the resin and the inorganic particles.
However, Murai teaches, in figure 1, that the resin insulating layer is formed such that the inner wall surface in the via hole (60) includes the resin (30) and the inorganic particles (40).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the inner wall surface of the via hole in Kajita to ensure that its surface includes the resin and inorganic particles, as in Murai, in order to prevent the via conductor from exfoliating from the resin and particles (Murai Col. 3, lines 16-30).
Claim(s) 5-7, 10-12, 14-16, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajita (EP 2981158 B1) in view of Ikeda (US 9538642 B2), as applied to claims 1-3 and 8 above, and further in view of Park (US 20170347450 A1).
Regarding claims 5, 10, and 14, a modified Kajita teaches a printed wiring board (Kajita figure 1b; 3) with a via conductor (Kajita figure 1b; 12), wherein the via conductor includes a seed layer (Ikeda figure 9; wherein layer 1001 of via conductors 101b and 102b is a seed layer).
A modified Kajita does not teach a seed layer comprising a first seed layer formed on the inner wall surface in the via hole and a second seed layer formed on the first seed layer.
However, Park teaches in figure 1 a seed layer comprising a first seed layer (130) formed on the inner wall surface in the via hole ([0090]; 130 is formed in via hole 125) and a second seed layer (140) formed on the first seed layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seed layer of Kajita to include two seed layers, in order to improve conductivity and adhesion between the substrate and metal layer of the via (Park [0028]).
Regarding claims 6, 11, and 15, a modified Kajita teaches a printed wiring board (Kajita figure 1b; 3) with a seed layer (Ikeda figure 9; 1001).
A modified Kajita does not teach a first seed layer that includes a copper alloy layer.
However, Park teaches in figure 1 a first seed layer (130) that includes a copper alloy layer ([0055]; wherein 130 includes at one or more nitrides, such as CuN).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seed layer of Kajita to include a copper alloy first seed layer, in order to improve conductivity and adhesion between the substrate and metal layer of the via (Park [0028]).
Regarding claims 7, 12, 16, and 20, a modified Kajita teaches in figure 1b a via conductor (12).
A modified Kajita fails to specifically teach that the via conductor is formed such that the metal layer includes an electrolytic plating layer filling the via hole formed in the resin insulating layer.
However, Ikeda teaches, in figure 9, that the via conductor (101b, 102b) is formed such that the metal layer includes an electrolytic plating layer (1002) filling the via hole (101a, 102a) formed in the resin insulating layer (101, 102; Col. 9 lines 20-26).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via conductor of Kajita to include an electrolytic plating layer in the metal layer filling the via hole, as in Ikeda, in order to improve the electrical characteristics of the via hole to perform circuit operations.
Claim(s) 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kajita (EP 2981158 B1) in view of Ikeda (US 9538642 B2) and in view of Murai (US 7759583 B2) as applied to claims 1-4, 8, 9, and 13 above, and further in view of Park (US 20170347450 A1).
Regarding claim 17, a modified Kajita teaches in figure 1b a printed wiring board (Kajita figure 1b; 3) with a via conductor (Kajita figure 1b; 12), wherein the via conductor includes a seed layer (Ikeda figure 9; layer 1001).
A modified Kajita does not teach a seed layer comprising a first seed layer formed on the inner wall surface in the via hole and a second seed layer formed on the first seed layer.
However, Park teaches in figure 1 a seed layer comprising a first seed layer (130) formed on the inner wall surface in the via hole ([0090]; 130 is formed in via hole 125) and a second seed layer (140) formed on the first seed layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seed layer of Kajita to include two seed layers, in order to improve conductivity and adhesion between the substrate and metal layer of the via (Park [0028]).
Regarding claim 18, a modified Kajita teaches a printed wiring board (Kajita figure 1b; 3) with a seed layer (Ikeda figure 9; 1001).
A modified Kajita does not teach a first seed layer that includes a copper alloy layer.
However, Park teaches in figure 1 a first seed layer (130) that includes a copper alloy layer ([0055]; wherein 130 includes one or more nitrides, such as CuN).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the seed layer of Kajita to include a copper alloy first seed layer, in order to improve conductivity and adhesion between the substrate and metal layer of the via (Park [0028]).
Regarding claims 19, a modified Kajita teaches in figure 1b a via conductor (12).
A modified Kajita fails to specifically teach that the via conductor is formed such that the metal layer includes an electrolytic plating layer filling the via hole formed in the resin insulating layer.
However, Ikeda teaches, in figure 9, that the via conductor (101b, 102b) is formed such that the metal layer includes an electrolytic plating layer (1002) filling the via hole (101a, 102a) formed in the resin insulating layer (101, 102; Col. 9 lines 20-26).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the via conductor of Kajita to include an electrolytic plating layer in the metal layer filling the via hole, as in Ikeda, in order to improve the electrical characteristics of the via hole to perform circuit operations.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Murase (US 20220346231 A1), Aratani (US 20220087016 A1), and Yamasaki (US 20090200072 A1).
Murase teaches a printed wiring board, consisting of two conductor layers and resin insulating
layers with inorganic filler, wherein via holes and via conductors connect the first and second conductor.
Aratani teaches a printed wiring board with multiple conductor layers, an insulating resin layer,
and via conductors with seed layers and electrolytic plating in the metal layers formed by sputtering.
Yamasaki teaches a printed wiring board with two conductor layers, an insulating resin layer,
and via conductors with a seed layer and electrolytic plating layer in the metal connecting the two
conductors, wherein the seed layer includes two layers and the first of which is a copper alloy.
The above references are considered of particular relevance to the claimed invention but cannot
be considered to teach the limitations or combined to being obvious to a person skilled in the art to
disclose the claimed invention.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABIGAIL MARIE THAYER whose telephone number is (571)270-0134. The examiner can normally be reached M-Th/F 7:30-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ABIGAIL MARIE THAYER/Examiner, Art Unit 2847
/Timothy J. Dole/Supervisory Patent Examiner, Art Unit 2847
