DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 6/25/2024 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
1: Claim(s) 1, 2, 4, 5, 10, 11, 13 and 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0302545 A1 Harris et al.
2: As for Claim 1, Claim 1 is rejected for reasons discussed related to Claim 10.
3: As for Claim 2, Claim 2 is rejected for reasons discussed related to Claim 11.
4: As for Claim 4, Claim 4 is rejected for reasons discussed related to Claim 13.
5: As for Claim 5, Claim 5 is rejected for reasons discussed related to Claim 14.
6: As for Claim 10, Harris et al depicts in Figure 4 and teaches on [0082] A graphics processor configured to perform tile-based rendering in which a render output is sub-divided into a plurality of tiles for rendering (Paragraph [0083]), the graphics processor comprising: a geometry processing circuit that is configured to perform a first processing pass that generates, for a sequence of primitives to be processed for a render output, a cumulative bounding box encompassing all of the primitives in the sequence of primitives,( Harris et al teaches in Paragraphs [64 and 0077 and 0080] a bonding box is formed to encompasses the primitives (polygons) to include maximum and minimum values in both the X and Y directions. This is viewed as a cumulative bonding box. Harris et al teaches in Paragraph [0164]
the graphics processor further configured to test regions of the render output for intersection with the cumulative bounding box (the determined maximum and minimum X and Y value locations of the primitives within the bounding box) determine which of the tiles into which the render output is sub-divided for rendering intersect the cumulative bounding box and therefore which of the tiles potentially contain primitives to be rendered. Harris et al teaches tiler 11 operates in a first rendering pass 28 to sort primitives for the data array (e.g. shadow map) to be generated in the first rendering pass into tile lists for each tile of the array. The tiler 11 stores in the polygon list array 12 a set of tile lists, one list for each tile of the array. In the present embodiment, the tiler 11 additionally generates a bounding box 30. The bounding box 30 represents the minimum and maximum spatial extent of primitives (i.e. in a first (x) direction and a second (y) direction) in the array. That is, the bounding box 30 comprises minimum and maximum x and y values that encompass all of the primitives present in the array.
7: As for Claim 11, Harris et al teaches in Paragraph [0177] further comprising a rendering circuit that is configured to perform a second processing pass (second rendering pass) to render the tiles into which the render output is sub-divided for rendering, wherein issuing of tiles for rendering by the second processing pass is controlled based on the determination of which of the tiles potentially contain primitives to be rendered. Harris et al teaches using the determination in the first rendering pass to control the generation of the array of graphic data and/or using the determination in the second rendering pass to control the reading of the array of graphics data.
8: As for Claim 13, Harris et al teaches in Paragraph [0168] wherein the geometry processing circuit writes the generated cumulative bounding box (30) to memory (14).
9: As for Claim 14, Harris et al teaches in Paragraphs [0168, 0171 and 0073] wherein the testing the regions of the render output for intersection with the cumulative bounding box is performed in a hierarchical manner. Harris et al teaches performing a sorting operation on the primitives and subsequently performing processing based on the sorted data. The sorting operation and subsequent processing based on the sorted order is viewed by the examiner as performing processing in a hierarchical manner.
Allowable Subject Matter
Claims 3, 6-9, 12, 15-18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES M HANNETT whose telephone number is (571)272-7309. The examiner can normally be reached 8:00 AM-5:00 PM Monday thru Thursday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Twyler Haskins can be reached at 571-272-7406 The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES M HANNETT/Primary Examiner, Art Unit 2639
JMH
February 4, 2026
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