DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) in view of Kim et al. (US 2006/0139848).
PNG
media_image1.png
264
372
media_image1.png
Greyscale
PNG
media_image2.png
456
426
media_image2.png
Greyscale
Regarding claim 1, Kato discloses in fig. 3, 4, a multilayer ceramic capacitor (11) comprising:
an element body portion (11) including a first principal surface (top) and a second principal surface (bottom) opposite to each other in a thickness direction (Z), a first side surface (left) and a second side surface (right) opposite to each other in a width direction (Y), and a first end surface (front) and a second end surface (back) opposite to each other in a length direction (X), and a plurality of dielectric layers (20) and a plurality of internal electrode layers (12, 13) including Ni [0058] laminated in the thickness direction (Z); and
a pair of external electrodes (14, 15) respectively on the first end surface (front) and the second end surface (back), and electrically connected to the plurality of internal electrode layers (12, 13); wherein
each of the plurality of internal electrode layers (12, 13) includes an opposing portion opposed to an internal electrode layer (13) of the plurality of internal electrode layers which is adjacent in the thickness direction (Z), and a lead-out portion (see Fig. 9) connected to the opposing portion and extending to the first end surface (left) or the second end surface (right);
the element body portion (11) includes a pair of side margin portions (17, 17) extending in the width direction (Y) from both end portions of the opposing portion to the first side surface (left) and the second side surface (right) in a cross section on both sides in the width direction (Y), passing through a central portion in the length direction (X), and parallel or substantially parallel to the thickness direction (Z) and the width direction (Y);
a dielectric layer (20) of the plurality of dielectric layers between the internal electrode layers (12, 13) adjacent to each other in the thickness direction (Z) includes a plurality of grains (see Fig. 4, [0074];
each of the pair of side margin portions (17) includes a dielectric including a plurality of grains (see Fig. 4, [0069]);
the plurality of grains included in the dielectric layer includes pores (not illustrated, [0074], “a few crystal grains including the intergranular pores P”); and
the plurality of grains in the pair of side margin portions does not include pores (see Fig. 4 – the plurality of grains not including “P” – [0069]).
Kato discloses the claimed invention except for a width of the opposing portion is larger than a width of the lead-out portion in the width direction.
PNG
media_image3.png
248
811
media_image3.png
Greyscale
Kim et al. disclose a multilayer ceramic capacitor comprising internal electrodes (52, 53), wherein each internal electrode (53, 54) includes an opposing portion (@ 52, @ 53), and a lead-out portion (52A, 53a), wherein a width (M) of the opposing portion (@52, @53) is larger than a width (N) of the lead-out portion (52a, 52b) in the width direction (W).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the internal electrodes of Kato so that a width of the opposing portion is larger than a width of the lead-out portion in the width direction, since such a modification would from a multilayer ceramic capacitor where reliability can be enhanced [0055].
Regarding claim 6, Kato discloses wherein the element body portion has a rectangular or substantially rectangular parallelepiped shape (see Fig. 1).
Regarding claim 7, Kato discloses each of the plurality of dielectric layers (20) includes a perovskite compound including Ba and Ti as a primary component [0060].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) and Kim et al. (US 2006/0139848), as applied to claim 1 above, and further in view of Kim et al. (US 2013/0063862).
Regarding claim 5, Kato discloses the claimed invention except for a thickness of the plurality of dielectric layers (20) in the thickness direction (Z) is greater than or equal to about 0.3 µm and less than or equal to about 0.4 µm.
Kim et al. (‘862) disclose a multilayer ceramic capacitor wherein a thickness of a plurality of ceramic dielectric layers is greater than or equal to about 0.3 and less than or equal to about 0.4 µm (table 1 – samples 10, 11, 14-15, and 18-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form multilayer ceramic capacitor of Kato so that a thickness of the plurality of dielectric layers in the thickness direction is greater than or equal to about 0.3 µm and less than or equal to about 0.4 µm, since such a modification would form thin dielectric layer which will produce a multilayer ceramic capacitor having desired capacitance.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) and Kim et al. (US 2006/0139848) as applied to claim 7 above, and further in view of Suzuki et al. (US 2013/0321980).
Regarding claim 8, Kato discloses the claimed invention except for each of the plurality of dielectric layers (20) includes at least one of Si, Mg, Mn, V, Cr, or rare earth elements as an additive.
Suzuki et al. discloses a ceramic capacitor dielectric composition, wherein the dielectric composition comprises a perovskite compound that includes Ba and Ti as a primary component ([0029], [0034]-[0035] table 1) and includes at least one of Si, Mg, Mn, V, Cr, or rare earth elements as an additive [0034]-[0035].
It would have been obvious to a person of ordinary skill in the ceramic art to modify the dielectric layers of Kato to comprise a perovskite compound having Ba and Ti as main components and at least one of Si, Mg, Mn, V, Cr, or rare earth elements as an additive, since such a modification would form a multilayer ceramic capacitor having a high-dielectric constant ceramic that exhibits superior reliability [0029].
It has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) and Kim et al. (US 2006/0139848) as applied to claim 1 above, and further in view of Saito et al. (US 2021/0098191).
Regarding claim 9, Kato discloses the claimed invention except for each of the plurality of internal electrode layers includes Sn at an interface with a dielectric layer of the plurality of dielectric layers.
Saito et al. disclose a multilayer ceramic capacitor comprising internal electrodes (21, 22) and dielectric layers (20), wherein the internal electrode include Sn [0072] at an interface (62) with a dielectric layer (20) of the plurality of dielectric layers (20).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Kato so that each of the plurality of internal electrode layers includes Sn at an interface with a dielectric layer of the plurality of dielectric layers, since such a modification would form a highly reliable capacitor [0011].
Regarding claim 10, Kato discloses the claimed invention except for the multilayer ceramic capacitor has a dimension in the length direction of greater than or equal to about 0.2 mm and less than or equal to about 4.5 mm, a dimension in the width
direction of greater than or equal to about 0.125 mm and less than or equal to about 3.2 mm, and a dimension in the thickness direction of greater than or equal to about 0.125 mm and less than or equal to about 2.5 mm.
Saito et al. disclose a multilayer ceramic capacitor wherein the multilayer ceramic capacitor has a dimension om the length direction of 0.40 mm [0095], a dimension in the width direction of 0.2 mm [0094] and a dimension in the thickness direction of 0.20 mm [0093].
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Kato so that the multilayer ceramic capacitor has a dimension in the length direction of greater than or equal to about 0.2 mm and less than or equal to about 4.5 mm, a dimension in the width direction of greater than or equal to about 0.125 mm and less than or equal to about 3.2 mm, and a dimension in the thickness direction of greater than or equal to about 0.125 mm and less than or equal to about 2.5 mm, since such a modification would form a multilayer ceramic capacitor having desired capacitance and dimensions.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) and Kim et al. (US 2006/0139848) as applied to claim 1 above, and further in view of Okuda (US 2021/0104364).
Regarding claim 11, Kato discloses the claimed invention except for wherein a portion of the plurality of internal electrode layers bulges toward one of the first and second principal surfaces.
Okuda discloses a multilayer ceramic capacitor (title) comprising internal electrodes (21), wherein a portion of the plurality of internal electrode layers bulges toward one of the first (11) and second (12) principal surfaces.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form a portion of the plurality of internal electrode layers so that it bulges toward one of the first and second principal surfaces, since such a modification would provide a multilayer ceramic capacitor having posture stability during mounting.
Regarding claim 12, Kato discloses the claimed invention except for the portion of the plurality of internal electrode layers includes about 20% or less of a total number of the plurality of internal electrode layers.
Okuda discloses the portion of the plurality of internal electrode layers (21) that bulges toward one of the first (11) and second (12) principal surfaces improves adhesion between the internal electrodes and dielectric layers, resulting in enhanced anchoring effect and greater posture stability.
It would have been obvious to a person of ordinary skill in the internal electrode art to form the device of Kato so that the portion of the plurality of internal electrode layers includes about 20% or less of a total number of the plurality of internal electrode layers, since such a modification would provide a multilayer ceramic capacitor having the desired posture stability during mounting.
Claim(s) 13-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kato (US 2019/0348222) and Kim et al. (US 2006/0139848) as applied to claim 1 above, and further in view of Nishisaka et al. (US 2018/0096791).
Regarding claim 13, Kato discloses the claimed invention except for each of the pair of external electrode layers includes a Cu layer on the element body portion, a Ni plating layer on the Cu layer, and a Sn plating layer on the Ni plating layer.
Nishisaka et al. disclose a multilayer ceramic capacitor (title) comprising external electrodes (14a, 14b), wherein each of the external electrode layers (14a, 14b) includes a Cu layer (141a, 143a; 141b, 143b, [0048], [0056], [0086]) on an element body portion, a Ni plating layer (144a, 144b – [0092]) on the Cu layer, and a Sn plating layer on the Ni plating layer (144a, 144b – [0066], [0092]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to form the capacitor of Kato so that each of the pair of external electrode layers includes a Cu layer on the element body portion, a Ni plating layer on the Cu layer, and a Sn plating layer on the Ni plating layer, since such a modification would form a multilayer ceramic capacitor having external electrodes with improved moisture resistance reliability.
Regarding claim 14, the modified Kato discloses the Cu layer (Nishisaka et al.) includes a first layer portion (141a, 141b, Nishisaka et al.) and a second layer portion (143a, 143b) on the first layer portion.
Regarding claim 15, the modified Kato discloses the first layer portion (141a, 141b, Nishisaka et al.) is a Cu-rich layer including a higher Cu content [0048]-[0049] than the second layer portion (143a, 143b, table 1 - Nishisaka et al.).
Regarding claim 16, the modified Kato discloses the second layer portion (143a, 143b, Nishisaka et al.) is a glass-rich portion including a higher glass content (table 1) than the first layer portion (141a, 141b – plated).
Regarding claim 17, the modified Kato discloses a thickness of the first layer portion (141a, 141b) is about 25% or less of a total thickness of the Cu layer [0052], [0057].
Regarding claim 18, the modified Kato discloses a thickness of the first layer (141a, 141b) portion is about 5% or less of a total thickness of the Cu layer [0052], [0057].
Allowable Subject Matter
Claims 2-4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: In combination with the other claim limitations, the prior art does not teach or suggest a multilayer ceramic capacitor:
wherein only the plurality of the grains included in a central portion in the width direction of the plurality of dielectric layers between the internal electrode layers on both outermost sides in the thickness direction includes pores (claim 2);
wherein the plurality of grains included in the plurality of dielectric layers in a portion between the pair of side margin portions and both end portions of the lead-out portion in the width direction includes pores (claim 3); and
wherein a circle equivalent diameter of the plurality of grains including pores is smaller than a circle equivalent diameter of the plurality of grains not including pores (claim 4).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2007/0128794 – capacitor comprising internal electrodes wherein a width of the opposing portion is larger than a width of the lead-out portion in the width direction
US 2008/0266751 -- ceramic grains containing pores
US 2020/0258689 – ceramic grains containing pores
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC THOMAS whose telephone number is (571)272-1985. The examiner can normally be reached Monday-Friday, 6:00 AM-2:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC W THOMAS/Primary Examiner, Art Unit 2848
ERIC THOMAS
Primary Examiner
Art Unit 2848
Prosecution Insights