Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-5 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. US 2019/0281294 from IDS, supporting evidence by Liu et al. US 2020/0021834 from IDS
Kim discloses:
1. and under similar rationale 7 and complementary rationale 8 and 9. An image processing device (0135-9) comprising: a decoding circuit configured to decode a bitstream to generate a decoded image according to a block structure having a unified hierarchical structure of a transformation block, a prediction block, and a coding block, wherein the transformation block of the decoded image generated by the decoding circuit (0036: That is, in ITU-T H.265, an array of pixel difference values may be sub-divided for purposes of generating transform coefficients (e.g., four 8×8 transforms may be applied to a 16×16 array of residual values), for each component of video data, such sub-divisions may be referred to as Transform Blocks (TBs). Currently in JEM, when a QTBT partitioning structure is used, residual values corresponding to a CB are used to generate transform coefficients without further partitioning. That is, in JEM a QTBT leaf node may be analogous to both a PB and TB in ITU-T H.265. Thus, JEM enables rectangular CB predictions for intra and inter predictions.; While Kim is silent about unified hierarchical structure it would be have been obvious to a person having ordinary skill before the effective filing date to modify the reference(s) as above as supporting evidence Liu teaches 0087: A QTBT structure unifies the concepts of the coding unit (CU), prediction unit (PU), and transform unit (TU) and supports more flexibility for CU partition shapes.); a determination circuit configured to determine whether to apply a deblocking filter according to a block size of a sub-block obtained by dividing the transform block (0040-52; Fig. 5; Fig. 10: block size condition 1008); and a filter circuit configured to apply the deblocking filter to pixels on a line orthogonal to a block boundary (0040-52; Fig. 5).
8 and 9. Additionally have a sub-block circuit configured to obtain a sub-block by dividing a transform block on which intra prediction is performed in a locally decoded image that is locally decoded when an image is encoded (0036)
2. The image processing device according to claim 1, wherein the filter circuit is configured to apply the deblocking filter to pixels on a line orthogonal to the sub-block boundary in accordance with a boundary strength that is set according to characteristics of adjacent sub-blocks adjacent to each other across the sub-block boundary (0047: If one of the blocks (P or Q) has an intra prediction mode, then Bs=2; fig. 5).
3. The image processing device according to claim 2, wherein the filter circuit is configured to apply the deblocking filter to pixels on a line orthogonal to the sub-block boundary of a sub-block obtained by dividing the transform block on which intra prediction is performed (0040-52; Fig. 5).
4. The image processing device according to claim 3, wherein the filter circuit is configured to apply the deblocking filter to pixels on a line orthogonal to the sub-block boundary in accordance with a boundary strength that is set to be the same as a block boundary of the transform block on which intra prediction is performed (0079: For example, filter unit 300 may be configured to either perform filtering or skip filtering based on a block size condition.).
5. The image processing device according to claim 1, wherein the filter circuit is configured to apply the deblocking filter of a filter type set according to the block size of the sub-block (Fig. 12: second block size condition 1024, first filter type 1016, fourth filter type 1026; 0129: In one example, the second block size condition (1024) may include any of the minimum size conditions for video block P and/or Q described above.).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Andersson et al. US 2021/0329266 from IDS
Kim discloses:
6. The image processing device according to claim 1,
Kim does not explicitly disclose the following, however Andersson teaches wherein the filter circuit is configured such that pixels to which the deblocking filter is applied at one sub-block boundary do not include pixels referenced in application of the deblocking filter at another sub-block boundary. (0250: By doing the deblocking first internally in the block can help to apply longer deblocking filters on the block boundary. By doing the filtering of internal sub-block boundaries inside the block without overlap in filtering of other internal sub-block boundaries inside the block such filtering can be performed in parallel.).
Therefore, it would have been obvious to a person having ordinary skill before the effective filing date to modify the reference(s) as above in order to do the filtering of internal sub-block boundaries inside the block without overlap in filtering of other internal sub-block boundaries inside the block such filtering can be performed in parallel (Andersson 0250)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH W BECKER whose telephone number is (571)270-7301. The examiner can normally be reached flexible usually 10-6.
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/JOSEPH W BECKER/Examiner, Art Unit 2483