NON-FINAL OFFICE ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/26/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Pub. No. 2019/0303230 to Liberty et al. (hereinafter Liberty) in view of U.S. Patent Pub. No. 2007/0061634 to Marisetty et al. (hereinafter Marisetty).
Liberty discloses:
1. A device comprising:
a processor core configured for processing tasks (paras. [0024], [0018]-[0020] and Fig. 2, execution units 210); and
a management core configured for management tasks exclusive of the processing tasks (paras. [0025], [0018]-[0020] and Fig. 2, control logic 220), and configured to:
detect an error of the processor core (paras. [0025], [0034] and Fig. 4, block 405); and
process the error independently from the processor core running the processing tasks (paras. [0013], [0035] and Fig. 4, block 415).
Liberty does not disclose expressly:
provide instructions to the processor core for responding to the error.
Marisetty teaches providing instructions to the processor core for responding to the error (paras. [0031], [0049], [0050]).
Before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify Liberty by providing instructions to the processor core, as taught by Marisetty. A person of ordinary skill in the art would have been motivated to do so in order to minimize processor hardware and architecture changes, and provide flexibility and scalability via firmware, as discussed by Marisetty (para. [0024]).
Modified Liberty discloses:
2. The device of claim 1, wherein the management core is further configured to cloak or uncloak the error from an operating system (Liberty - para. [0035] and Fig. 4, blocks 420, 425).
3. The device of claim 2, wherein the management core is configured to cloak or uncloak the error from the operating system based on an error policy (Liberty - para. [0035] and Fig. 4, blocks 420, 425).
4. The device of claim 3, wherein the error policy is programmable (Liberty - paras. [0027]-[0028]).
5. The device of claim 3, wherein the error policy corresponds to microcode in the management core (Liberty - para. [0028]).
6. The device of claim 2, wherein cloaking the error comprises preventing the operating system from reading an error state for the error (Liberty - paras. [0031]-[0032], [0035]-[0036]).
7. The device of claim 2, wherein cloaking the error comprises suppressing an error interrupt to the operating system (Liberty - para. [0037]).
8. The device of claim 2, wherein uncloaking the error comprises allowing the operating system to read an error state for the error (Liberty - para. [0035]).
9. The device of claim 2, wherein uncloaking the error comprises sending an error interrupt to the operating system (Liberty - para. [0038]).
10. The device of claim 1, further comprising a register for storing an error state corresponding to the error (Liberty - paras. [0018], [0025] and Fig. 2, registers 230).
11. The device of claim 10, wherein processing the error further comprises accessing the register to read the error state (Liberty - para. [0035]).
12. The device of claim 1, wherein processing the error further comprises instructing the processor core to continue operations (Liberty - paras. [0035]-[0036]).
13. A system comprising:
a memory (Liberty - Fig. 1, memory devices 112, 140); and
a processor (Liberty - Fig. 1, computing system 100) comprising:
a processor core configured for processing tasks (Liberty - Fig. 1, processor cores 105);
a register for storing an error state of the processor core (Liberty - Fig. 2, registers 230) and
a management core configured for management tasks exclusive of the processing tasks (Liberty - Fig. 2, control logic 220), and configured to:
detect an error of the processor core (Liberty - paras. [0025], [0034] and Fig. 4, block 405);
control read access to the error state in the register (Liberty - para. [0026]);
process the error independently from the processor core running the processing tasks (Liberty - paras. [0013], [0035] and Fig. 4, block 415); and
provide instructions to the processor core for responding to the error (Marisetty - paras. [0031], [0049], [0050]).
14. The system of claim 13, wherein the management core is configured to control read access to the error state based on an error policy (Liberty - para. [0035] and Fig. 4, blocks 420, 425).
15. The system of claim 14, wherein the error policy corresponds to programmable microcode in the management core (Liberty - paras. [0027]-[0028]).
16. The system of claim 14, wherein the management core is further configured to cloak the error from an operating system based on the error policy by preventing the operating system from reading the error state and suppressing an error interrupt to the operating system (Liberty - paras. [0031]-[0032], [0035]-[0037]).
17. The system of claim 14, wherein the management core is further configured to uncloak the error from an operating system based on the error policy by allowing the operating system to read an error state for the error and sending an error interrupt to the operating system (Liberty - paras. [0035], [0038]).
18. The system of claim 13, wherein processing the error further comprises accessing the register to read the error state and instructing the processor core to continue operations (Liberty - paras. [0035]-[0036]).
19. A method comprising:
detecting, by a management core of a processor that is configured for management tasks exclusive of processing tasks for a processor core of the processor, an error of the processor core of the processor (Liberty - para. [0025], [0034] and Fig. 4, block 405);
controlling, by the management core, read access to an error state in a register based on an error policy (Liberty - para. [0026]);
processing, by the management core, the error independently from the processor core while the processor core continues operations on the processing tasks (Liberty - paras. [0013], [0035] and Fig. 4, block 415); and
providing, by the management core, instructions to the processor core for responding to the error (Marisetty - paras. [0031], [0049], [0050]).
20. The method of claim 19, further comprising providing read access to the error state for an operating system (Liberty - paras. [0026], [0035]-[0036]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Philip Guyton whose telephone number is (571)272-3807. The examiner can normally be reached M-F 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bryce Bonzo can be reached at (571)272-3655. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PHILIP GUYTON/ Primary Examiner, Art Unit 2113
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