DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 11/11/25, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhardwaj (US 20210397562) in view of Kim (US 20200057580).
With respect to claim 1, the Bhardwaj reference teaches a storage device comprising:
a memory device including a plurality of memory blocks corresponding to a plurality of physical zones; (see fig 1, controller 115; and paragraph 34, where memory sub-system controller 115 (or controller 115, for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations) and
a memory controller connected to the memory device, (see fig. 1, memory device 140) and
wherein the memory controller is configured to, when receiving a zone reset command for a reset target zone, (paragraph 44, where after the memory request is executed, e.g. during a downtime or a scheduled GC time, the controller 115 can perform static GC 218 and/or background scan 220 [analogous to a ‘zone reset command’ as claimed]) update a physical zone corresponding to the reset target zone among the plurality of physical zones to an invalid zone in a mapping table, and to sequentially trigger a block erase operation for an erase target memory block among a plurality of memory blocks included in the invalid zone in each period in which a foreground operation corresponding to a foreground command is not performed, (paragraph 19, where because each zone's LBAs are written to sequentially, rewriting data already stored in the zone requires invalidating the entire zone (by, e.g., moving a write pointer to the starting LBA of the zone) [i.e. sequentially from the start]; and paragraph 44, during background scan 220, the memory sub-system controller 115 can identify blocks that are at an elevated risk of having too many bits corrupted so that the error-correction code (ECC) may eventually be unable to repair the data stored thereon. Such blocks can be folded (copied to new locations with old locations erased or invalidated, i.e., scheduled for erasure) to other blocks, e.g., to blocks having a lower EC. Upon completion (or, in some embodiments, during execution) of the static GC 218 and/or background scan 220, the controller 115 can update the memory look-up table 212 (as indicated by the corresponding dashed lines) with the new memory translations; and where background scan 220 can include a zone-aware background scan 236)
However, the Bhardwaj reference does not explicitly teach wherein the memory controller is further configured to, when receiving an additional foreground command in the period in which the block erase operation is performed on a current memory block, trigger an additional foreground operation corresponding to the additional foreground command after the block erase operation for the current memory block is completed.
The Kim reference teaches it is conventional to have wherein the memory controller is further configured to, when receiving an additional foreground command in the period in which the block erase operation is performed on a current memory block, trigger an additional foreground operation corresponding to the additional foreground command after the block erase operation for the current memory block is completed. (paragraph 54, where when the semiconductor memory device 100 is in the busy state, it may mean that the semiconductor memory device 100 is still performing the internal operation. For example, when the semiconductor memory device 100 is in the busy state, it may mean that the semiconductor memory device 100 is still performing the program, read or erase operation corresponding to a current command and is not yet ready for serving a next command to be provided thereto. In the busy state, the ready-busy signal becomes the “busy state.”)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Bhardwaj reference to have wherein the memory controller is further configured to, when receiving an additional foreground command in the period in which the block erase operation is performed on a current memory block, trigger an additional foreground operation corresponding to the additional foreground command after the block erase operation for the current memory block is completed, as taught by the Kim reference.
The suggestion/motivation for doing so would have been to control, regardless of the actual state of the semiconductor memory device 100, a time at which the state of the ready-busy signal is changed from the busy state to the ready state according to an internal temperature of the semiconductor memory device 100. (Kim, paragraph 55)
Therefore it would have been obvious to combine the Bhardwaj and Kim references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of Bhardwaj and Kim references teaches the storage device of claim 1, wherein the mapping table indicates a relationship between a plurality of logical zones and the plurality of physical zones, and the memory controller is configured to select the erase target memory block from among the plurality of memory blocks included in the invalid zone with reference to an address value of a write pointer of the invalid zone. (Bhardwaj, paragraph 19, where because each zone's LBAs are written to sequentially, rewriting data already stored in the zone requires invalidating the entire zone (by, e.g., moving a write pointer to the starting LBA of the zone). Using zoned namespaces allows more efficient (faster) read, write, and erase operations and reduces the need for over-provisioning of memory blocks to various applications (by reducing the number of blocks that otherwise would store invalid data and which have to be factored in when memory is allocated to the applications))
With respect to claim 3, the combination of Bhardwaj and Kim references teaches the storage device of claim 2, wherein the memory controller is configured to select a memory block including a page mapped to an address value smaller than an address value of the write pointer as the erase target memory block. (Bhardwaj, paragraph 19, where the application can specify an identifier of the zone, which can be a starting (lowest) LBA of the zone or any other pointer that specifies the zone; and paragraph 43, where The LBA 210 can be used by the memory sub-system controller 115 to identify a physical memory partition (block, page, plane, etc.) to which the received memory request [i.e. an erase command] is related. For example, the memory sub-system controller 115 can access a memory look-up table 212 to determine the PBA 216 that corresponds to the LBA 210)
With respect to claim 4, the combination of Bhardwaj and Kim references teaches the storage device of claim 1, wherein the memory controller is configured to select a memory block in which data is written from among the plurality of memory blocks included in the invalid zone as the erase target memory block. (Bhardwaj, paragraph 19, where the application can specify an identifier of the zone, which can be a starting (lowest) LBA of the zone or any other pointer that specifies the zone; and paragraph 43, where The LBA 210 can be used by the memory sub-system controller 115 to identify a physical memory partition (block, page, plane, etc.) to which the received memory request [i.e. an erase command] is related. For example, the memory sub-system controller 115 can access a memory look-up table 212 to determine the PBA 216 that corresponds to the LBA 210)
With respect to claim 5, the combination of Bhardwaj and Kim references teaches the storage device of claim 1, wherein the memory controller is configured to sequentially select a block having a smaller mapped address value from among a plurality of erase target memory blocks as the current memory block and to trigger the block erase operation for the current memory block. (Bhardwaj, paragraph 19, where the application can specify an identifier of the zone, which can be a starting (lowest) LBA of the zone or any other pointer that specifies the zone; and paragraph 43, where The LBA 210 can be used by the memory sub-system controller 115 to identify a physical memory partition (block, page, plane, etc.) to which the received memory request [i.e. an erase command] is related. For example, the memory sub-system controller 115 can access a memory look-up table 212 to determine the PBA 216 that corresponds to the LBA 210)
With respect to claim 6, the combination of Bhardwaj and Kim references teaches the storage device of claim 1, wherein the memory controller is configured to, when the block erase operation for the current memory block is completed, update a memory block mapped to a subsequent address value of an address value of the current memory block among a plurality of erase target memory blocks to the current memory block. (Bhardwaj, paragraph 44, during background scan 220, the memory sub-system controller 115 can identify blocks that are at an elevated risk of having too many bits corrupted so that the error-correction code (ECC) may eventually be unable to repair the data stored thereon. Such blocks can be folded (copied to new locations with old locations erased or invalidated, i.e., scheduled for erasure) to other blocks, e.g., to blocks having a lower EC. Upon completion (or, in some embodiments, during execution) of the static GC 218 and/or background scan 220, the controller 115 can update the memory look-up table 212 (as indicated by the corresponding dashed lines) with the new memory translations; and where background scan 220 can include a zone-aware background scan 236)
Claim 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bhardwaj (US 20210397562) in view of Kim (US 20200057580) as shown in the rejections above, and further view in Ji (US 20180349240).
With respect to claim 7, the combination of the Bhardwaj and Kim references does not explicitly the storage device of claim 6, wherein the memory controller is configured to suspend a block erase operation for the memory block mapped to the subsequent address value in a period in which the additional foreground operation corresponding to the additional foreground command is performed.
The Ji reference teaches it is conventional to have wherein the memory controller is configured to suspend a block erase operation for the memory block mapped to the subsequent address value in a period in which the additional foreground operation corresponding to the additional foreground command is performed. (paragraph 43, where In this respect, a non-volatile memory device in the suspend state can be transitioned from the suspend state back to a programming state based on the subsequent program command. In regard to erase commands, the controller 114 issues either a reset command or an erase stop command to stop the erase operation from occurring. The controller 114 then monitors the status poll from the non-volatile memory device to detect a ready signal. Upon detecting the ready signal, the controller 114 may resume the stopped erase command by issuing a same erase command to a same address in the non-volatile memory device (e.g., an address pointing to a physical block of the non-volatile memory device). In this respect, a non-volatile memory device in the terminate state can be transitioned from the terminate state back to an erase state based on the subsequent erase command)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify combination of the Bhardwaj and Kim references to have wherein the memory controller is configured to suspend a block erase operation for the memory block mapped to the subsequent address value in a period in which the additional foreground operation corresponding to the additional foreground command is performed, as taught by the Ji reference.
The suggestion/motivation for doing so would have been to allow a non-volatile memory device in the terminate state to be transitioned from the terminate state back to an erase state based on the subsequent erase command. (Ji, paragraph 43)
Therefore it would have been obvious to combine the Bhardwaj, Kim, and Ji references for the benefits shown above to obtain the invention as specified in the claim.
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-9) and amendments with respect to claims 1-7 have been considered but not persuasive. The applicant argues that the prior art does not the teach the limitations of “wherein the memory controller is configured to ... sequentially trigger a block erase operation for an erase target memory block among a plurality of memory blocks included in the invalid zone in each period in which a foreground operation corresponding to a foreground command is not performed”. (emphasis added) The Examiner respectfully disagrees. The Bhardwaj reference teaches (paragraph 19) because each zone's LBAs are written to sequentially, rewriting data already stored in the zone requires invalidating the entire zone (by, e.g., moving a write pointer to the starting LBA of the zone); and further teaches (paragraph 44) after the memory request is executed, e.g. during a downtime or a scheduled GC time, the controller 115 can perform static GC 218 and/or background scan 220; and during background scan 220, the memory sub-system controller 115 can identify blocks that are at an elevated risk of having too many bits corrupted so that the error-correction code (ECC) may eventually be unable to repair the data stored thereon. Such blocks can be folded (copied to new locations with old locations erased or invalidated, i.e., scheduled for erasure) to other blocks, e.g., to blocks having a lower EC. Upon completion (or, in some embodiments, during execution) of the static GC 218 and/or background scan 220, the controller 115 can update the memory look-up table 212 (as indicated by the corresponding dashed lines) with the new memory translations; and where background scan 220 can include a zone-aware background scan 236. Thus, based on the citations above, the Bhardwaj reference teaches invalidating the entire zone by moving a write pointer to the starting LBA of the zone [i.e. sequentially from the start] and further this is done during background periods [analogous to ‘each period in which a foreground operation corresponding to a foreground command is not performed’]. Therefore, the rejections have been maintained for the reasons set forth above.
3. RELEVANT ART CITED BY THE EXAMINER
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant's art and those arts considered reasonably pertinent to applicant's disclosure. See MPEP 707.05(c).
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. These references include:
Choi (US 20150277795), which teaches a method of operating a nonvolatile memory (NVM) is provided which includes calculating an assignment interval between successive assignments of erase blocks to free blocks from among a plurality of memory blocks of the NVM, and adjusting a number of erase blocks of the plurality of memory blocks according to the assignment interval. The erase blocks are memory blocks, having an erased state, from among the plurality of memory blocks, and the free blocks are memory blocks, which are selected to write data, from among the erase blocks.
4. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Arpan Savla can be reached on (571) 272-1077. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137