DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 8-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kothandaraman et al. (US 2019/0120708 A1).
Considering claim 1, Kothandaraman discloses a method of measuring a strain in a semiconductor substrate of a semiconductor die ([0003-4]), the semiconductor die further including a Back End of Line (BEOL) metallization ([0028]; [0036]) on the semiconductor substrate that includes a metallic structure ([0018], metal material), the method comprising:
- transmitting a measurement signal into the metallic structure (Figure 1; [0018-20], strain gauge in a Wheatstone configuration inherently requires a voltage input, which is considered the measurement signal; [0034], remains dormant until a measurement is desired; Figure 8; [0035], scheduled or continuous monitoring of strain triggered by external signal);
- detecting a resistance of the metallic structure in response to the transmission of the measurement signal ([0018-20]; [0034-35]); and
- determining the strain of the semiconductor die based on the resistance of the metallic structure ([0035]).
Considering claim 8, Kothandaraman discloses that detecting the resistance of the metallic structure in response to the transmission of the measurement signal comprises detecting the resistance of the metallic structure in response to the transmission of the measurement signal with a resistance detection circuit ([0018-20]; [0023]; [0025]).
Considering claim 9, Kothandaraman discloses that the resistance detection circuit has a Wheatstone Bridge configuration ([0018-20]; [0023]; [0025]).
Considering claim 10, Kothandaraman discloses that the semiconductor die is mounted on a package body ([0003-4]; [0030]) and the resistance detection circuit is formed by the metallic structure integrated into the package body ([0029-30]).
Considering claim 11, Kothandaraman discloses mounting the semiconductor die on a package substrate prior to transmitting the measurement signal into the metallic structure ([0029-30]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Kothandaraman et al. (US 2019/0120708 A1) in view of Kumar et al. (NPL - Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor).
Considering claim 2, it is noted that the strain determination process, already disclosed in Kothandaraman, is repeated after the thinning, and this is not a new process. The invention by Kothandaraman fails to disclose reducing the first thickness of the semiconductor die to a second thickness that is less than the first thickness, retransmitting the measurement signal into the metallic structure when the semiconductor die is at the second thickness, detecting a second resistance of the metallic structure in response to the retransmission of the measurement signal, and determining a second strain of the semiconductor die based on the second resistance of the metallic structure.
However, Kumar teaches the concept of monitoring of stress (related to strain through elastic modulus) in a semiconductor die/wafer at a first thickness and again at subsequent thinned thicknesses (Abstract; 4.1 Stresses after Wafer Thinning, Pages 1272-1274). The general concept is shown to repeat the measurements at subsequent thinned thicknesses to monitor changes in the stress/strain by measuring a resistance of the applied piezoelectric sensors.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to thin the semiconductor die and repeat the measurement process of Kothandaraman, as taught by Kumar. The motivation for doing so, as suggested by Kumar, is to monitor the effects of thinning on the properties of the wafer (1. Introduction, Page 1270).
Considering claim 3, Kothandaraman fails to explicitly disclose that the second resistance is higher than the first resistance, thereby indicating that the second strain is higher than the first strain.
However, Kumar teaches that the stress/strain increases as the semiconductor die is thinned (Figure 10; Page 1273, “average values of stresses plotted as a function of wafer thickness (Fig. 10) reveal that with the decrease in wafer thickness, the amount of in-plane stresses (compressive) increase exponentially”), whereby the resistance of the piezoelectric sensors thereon show an increased resistance with increased compressive stress (Page 1272, Table 1, n-type stress sensor have negative Piezoresistive coefficients, thus increasing resistance under compression).
The invention by Kothandaraman teaches a proportional relationship between strain and stress, but fails to explicitly disclose that the relationship between resistance and strain/stress is proportional. The invention by Kumar utilizes the known technique of calibrated piezoresistive relationships for converting resistance change to mechanical stress/strain information through a linear relationship. One of ordinary skill in the art could have applied the known technique of Kumar to the invention by Kothandaraman, whereby a linear relationship between resistance and strain would exist to monitor the effect of thinning on strain, based on a detected change in resistance that increases with increased strain, and the results of the combination would have been predictable and repeatable. Therefore, it would have been obvious to one of ordinary kill in the art, before the effective filing date of the claimed invention, to utilize a linear relationship between the resistance and strain, whereby an increase in strain increases resistance, as suggested by Kumar, in the invention by Kothandaraman.
Claims 4-7 and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kothandaraman et al. (US 2019/0120708 A1) in view of Irving et al. (US 2009/0114030 A1).
Considering claim 4, Kothandaraman fails to disclose that the metallic structure has a meandering conductive path wherein the meandering conductive path defines a long path axis and the strain is measured around the long path axis.
However, Irving teaches the use of a metallic structure for measuring strain based on changes in resistance of the metallic structure (Abstract), whereby the metallic structure has a meandering conductive path (Figures 1, 3A; [0028]; [0033]) wherein the meandering conductive path defining a long path axis and the strain is measured around the long path axis ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
Considering claim 5, Kothandaraman, as modified by Irving, already discloses that the meandering conductive path is a first meandering conductive path, the long path axis is a first long path axis, the strain is a first strain, a strain axis is a first strain axis, and the measurement signal is a first measurement signal, as illustrated in the rejection of claim 4, above.
With respect to the metallic structure further comprising a second meandering conductive path defining a second long path axis that is substantially orthogonal to the first long path axis, Kothandaraman fails to disclose that the metallic structure has a second meandering conductive path.
However, Irving teaches a plurality of meandering conductive paths, including a second defining a second long path axis that is substantially orthogonal to the first long path axis (Figures 1-3; [0032-33], specifically measuring in three dimensions).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a second meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the entire layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
Considering claim 6, Kothandaraman discloses the use of a plurality of spaced strain gauges for measuring strain in the same fabrication level or distributed in multiple levels for measuring a distributed strain (Figure 6; [0029]), whereby at least one strain gauge is connected with a strain gauge sensor circuit that selectively quantifies the strain from that strain gauge (Claim 8), there are a plurality of strain gauges (Claim 10; Figure 9), and there are a plurality of strain gauge sensor circuits each monitoring a local IC stress (Claim 10). Therefore, the individual measurement signals would be sent to each strain gauge sensor circuit in the invention by Kothandaraman.
Furthermore, the combination of Kothandaraman, as modified by Irving, already teaches that the second strain gauge is a meandering conductive path defining a second long path axis, as illustrated in the rejection of claim 5, above.
With respect to the additional claimed limitations, Kothandaraman discloses transmitting a second measurement signal into the second strain gauge (Figure 1; [0018-20], strain gauge in a Wheatstone configuration inherently require a voltage input, which is considered the measurement signal; [0034], remains dormant until a measurement is desired; Figure 8; [0035], scheduled or continuous monitoring of strain triggered by external signal), detecting a second resistance of the second strain gauge in response to the transmission of the second measurement signal ([0018-20]; [0034-35]), and determining a second strain of the semiconductor die based on the second resistance of the second strain gauge, wherein the second strain is measured around a second long path axis ([0035]).
Therefore, the combination of Kothandaraman, as modified by Irving, has already been shown to provide all of the claimed features.
Considering claim 7, Kothandaraman discloses that the first conductive path is in a first layer and the second conductive path is in a second layer ([0036], any single strain sensor may be in any chip layer including the BEOL; [0032], forming strain gauges in subsequent manufacturing layers; [0028], strain sensor may be added at the end of chip fabrication in the BEOL), but fails to explicitly disclose that the first and second layers are BEOL layers.
However, Irving teaches that a via 41 running through multiple buried layers 47 ([0031]; “surfaces at different depths within a chip where etched conductor runs, contacts and connections to vias may be found”) connects resistive runs placed on any layer ([0033]). Irving, therefore, teaches placing strain gauges on multiple layers of electrical interconnections.
In combination, Kothandaraman already discloses that the strain sensors are in multiple layers, including the BEOL, while Irving teaches including strain sensors on multiple layers of electrical interconnections, thus, it is shown that the combination teaches all of the claimed subject matter of conductive paths on multiple layers of the BEOL.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize multiple layers of BEOL, as suggested by Irving, in the invention by Kothandaraman. The motivation for doing so, as understood in the art, is to increase the routing density by use of vertical layers of interconnects, whereby Irving additionally provides the motivation that it would be desirable to map the strain throughout an integrated circuit chip by employing resistive, metallic runs distributed in any buried layer ([0012]).
Considering claim 12, Kothandaraman discloses a method of measuring a strain in a semiconductor substrate of a semiconductor die ([0003-4]), the semiconductor die further including a Back End of Line (BEOL) metallization ([0028]; [0036]), the method comprising:
- transmitting a measurement signal into a BEOL metallization metallic structure (Figure 1; [0018-20], strain gauge in a Wheatstone configuration inherently requires a voltage input, which is considered the measurement signal; [0034], remains dormant until a measurement is desired; Figure 8; [0035], scheduled or continuous monitoring of strain triggered by external signal);
- detecting a resistance of the metallic structure in response to the transmission of the measurement signal ([0018-20]; [0034-35]); and
- determining the strain of the semiconductor die based on the resistance of the metallic structure ([0035]).
The invention by Kothandaraman fails to disclose that the BEOL metallization metallic structure has a meandering conductive path wherein the meandering conductive path defines a long path axis and the strain is measured around the long path axis.
However, Irving teaches the use of a metallic structure for measuring strain based on changes in resistance of the metallic structure (Abstract), whereby the metallic structure has a meandering conductive path (Figures 1, 3A; [0028]; [0033]) wherein the meandering conductive path defining a long path axis and the strain is measured around the long path axis ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
Considering claim 13, the invention by Kothandaraman fails to disclose the meandering conductive path
However, Irving teaches that the meandering conductive path comprises:
- a first plurality of conductive segments, each of the first plurality of conductive segments has a long segment axis that extends parallel to the long path axis (Figure 1; [0028]); and
- a second plurality of conductive segments, each of the second plurality of conductive segments connects different pairs of the first plurality of conductive segments (Figure 1).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
Considering claim 14, Kothandaraman discloses that the strain gauge conductive path is positioned in at least a first layer of the BEOL metallization, but fails to disclose that the BEOL metallization metallic structure has a meandering conductive path.
However, Irving teaches the use of a metallic structure for measuring strain based on changes in resistance of the metallic structure (Abstract), whereby the metallic structure has a meandering conductive path (Figures 1, 3A; [0028]; [0033]) wherein the meandering conductive path defining a long path axis and the strain is measured around the long path axis ([0028]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
Considering claim 15, Kothandaraman discloses the use of a plurality of spaced strain gauges for measuring strain in the same fabrication level or distributed in multiple levels for measuring a distributed strain (Figure 6; [0029]), whereby at least one strain gauge is connected with a strain gauge sensor circuit that selectively quantifies the strain from that strain gauge (Claim 8), there are a plurality of strain gauges (Claim 10; Figure 9), and there are a plurality of strain gauge sensor circuits each monitoring a local IC stress (Claim 10). Therefore, the individual measurement signals would be sent to each strain gauge sensor circuit in the invention by Kothandaraman.
Kothandaraman, as modified by Irving, already discloses that the meandering conductive path is a first meandering conductive path, the long path axis is a first long path axis, the strain is a first strain, a strain axis is a first strain axis, and the measurement signal is a first measurement signal, as illustrated in the rejection of claim 12, above.
Kothandaraman fails to disclose that the BEOL metallization has a second meandering conductive path.
However, Irving teaches a plurality of meandering conductive paths, including a second defining a second long path axis that is substantially orthogonal to the first long path axis (Figures 1-3; [0032-33], specifically measuring in three dimensions).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize a second meandering conductive path in the invention by Kothandaraman, as taught by Irving. The motivation for doing so, as suggested by Irving, is to map the strain across the entire layers of the IC package ([0006]) and directly measure three-dimensional strain throughout the body of the chip ([0032]).
With respect to the additional claimed limitations, Kothandaraman discloses transmitting a second measurement signal into the second strain gauge (Figure 1; [0018-20], strain gauge in a Wheatstone configuration inherently require a voltage input, which is considered the measurement signal; [0034], remains dormant until a measurement is desired; Figure 8; [0035], scheduled or continuous monitoring of strain triggered by external signal), detecting a second resistance of the second strain gauge in response to the transmission of the second measurement signal ([0018-20]; [0034-35]), and determining a second strain of the semiconductor die based on the second resistance of the second strain gauge, wherein the second strain is measured around a second long path axis ([0035]).
Therefore, the combination of Kothandaraman, as modified by Irving, has already been shown to provide all of the claimed features.
Considering claim 16, Kothandaraman discloses that the first conductive path is in a first layer and the second conductive path is in a second layer ([0036], any single strain sensor may be in any chip layer including the BEOL; [0032], forming strain gauges in subsequent manufacturing layers; [0028], strain sensor may be added at the end of chip fabrication in the BEOL), but fails to explicitly disclose that the layers are BEOL layers with.
The invention by Kothandaraman, as modified by Irving, already discloses the plurality of meandering paths, as illustrated in the rejection of claim 15, above.
However, Irving teaches that a via 41 running through multiple buried layers 47 ([0031]; “surfaces at different depths within a chip where etched conductor runs, contacts and connections to vias may be found”) connects resistive runs placed on any layer ([0033]). Irving, therefore, teaches placing strain gauges on multiple layers of electrical interconnections.
In combination, Kothandaraman already discloses that the strain sensors are in multiple layers, including the BEOL, while Irving teaches including strain sensors on multiple layers of electrical interconnections, thus, it is shown that the combination teaches all of the claimed subject matter of conductive paths on multiple layers of the BEOL.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize multiple layers of BEOL, as suggested by Irving, in the invention by Kothandaraman. The motivation for doing so, as understood in the art, is to increase the routing density by use of vertical layers of interconnects, whereby Irving additionally provides the motivation that it would be desirable to map the strain throughout an integrated circuit chip by employing resistive, metallic runs distributed in any buried layer ([0012]).
Considering claim 17, Kothandaraman discloses transmitting the first measurement signal into the first conductive path comprises transmitting the first measurement signal into the first conductive path with a first Wheatstone Bridge circuit, and transmitting the second measurement signal into the second conductive path comprises transmitting the second measurement signal into the second conductive path with a second Wheatstone Bridge circuit ([0020]; [0029], each strain gauge can be used as a resistor in a Wheatstone bridge, suggesting plural Wheatstone bridges).
The invention by Kothandaraman, as modified by Irving, already discloses the plurality of meandering paths, as illustrated in the rejection of claim 15, above.
Considering claim 18, Kothandaraman discloses transmitting the first measurement signal into the first conductive path comprises transmitting the first measurement signal into the first meandering path with a Wheatstone Bridge circuit ([0020]; [0029]), but fails to discloses transmitting the second measurement signal into the second meandering conductive path comprises transmitting the second measurement signal into the second meandering conductive path with the Wheatstone Bridge circuit.
The invention by Kothandaraman, as modified by Irving, already discloses the plurality of meandering paths, as illustrated in the rejection of claim 15, above.
However, Irving teaches placing multiple different meandering conductive paths within the same Wheatstone Bridge circuit ([0005]; [0035]).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to utilize the same Wheatstone bridge for the first and second meandering conductive paths, as suggested by Irving, in the invention by Kothandaraman. The motivation for doing so, as understood in the art, is to provide common-mode rejection of temperature factors and provides an increase sensitivity to through thickness bending strain rather than single plane strain.
Considering claim 19, Kothandaraman discloses that the semiconductor die is mounted on a package body ([0003-4]; [0030]), transmitting the measurement signal into the conductive path comprises transmitting the measurement signal into the conductive path with a Wheatstone Bridge circuit ([0018-20]; [0023]; [0025]; [0029]), and the Wheatstone Bridge circuit is formed in a conductive structure integrated into the package body ([0029-30]).
The invention by Kothandaraman, as modified by Irving, already discloses the meandering conductive path, as illustrated in claim 12, above.
Considering claim 20, Kothandaraman discloses mounting the semiconductor die on a package substrate prior to transmitting the measurement signal into the conductive path ([0029-30]).
The invention by Kothandaraman, as modified by Irving, already discloses the meandering conductive path, as illustrated in claim 12, above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Briggs et al. (US 9941211 B1) discloses modification of a resistance of metallic interconnects in a BEOL structure by application of compressive strain, thus indicating a relationship between strain and resistance in BEOL metallization.
Hiblot et al. (US 11038067 B2) discloses an FET stress sensor located in a BEOL, whereby a drain current is proportional to the resistance of an interconnect via, between layers of the BEOL, thus indicating vertical stress changes with respect to current/resistance.
Hsu et al. (2025/0369809 A1), while not prior art, discloses monitoring stress/strain across layers of a circuit using interconnect vias with a resistive property that changes based on applied strain/stress.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jonathan M Dunlap whose telephone number is (571)270-1335. The examiner can normally be reached Mon-Fri 10AM - 7PM.
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/JONATHAN M DUNLAP/Primary Examiner, Art Unit 2855 June 26, 2026
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