DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/05/24, 10/31/24, 04/10/25, 11/07/25, and 04/07/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 12-17 and 20 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Ravi (US 2023/0216409 A1).
Regarding claim 1, Ravi teaches a multi-voltage power management integrated circuit (PMIC) (Figures 1-4; Paragraph 0106 highlights the system is an integrated chip) comprising: a plurality of holding capacitors (Figure 3 Component Capacitors connected to Components Vo1, Vo2, Vo3 and Vo4; Figure 4 shows each Component 302a-302n in detail), each configured to provide a respective one of a plurality of voltages (Figure 3 Components Vo1, Vo2, Vo3 and Vo4) during a respective one of a plurality of voltage steps in each of a plurality of voltage generation cycles (Figure 26 shows a timing diagram that shows Components Vo1, Vo2, Vo3 and Vo4 are provided in voltage steps in each of the generation cycles); and a control circuit (Figure 4 Components 404+406; Figure 25 shows the overall controller used in Figures 3-4; Paragraph 0291 “FIG. 25 illustrates a block diagram of an example system 2500 that includes the SIMO 104… SIMO 104 may correspond to the SIMO 104 described above in relation to FIG. 4”; Figure 25 Components 2502+2504) configured to: receive a plurality of voltage targets, each indicating a respective level of the plurality of voltages in a respective one of the plurality of voltage generation cycles (Figure 4 Components 404 and 406 have voltage references; Figure 4 shows one Component 302 seen in Figure 3 therefore each Component 302 has Components 404 and 406 having reference voltages); assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with the plurality of voltage targets (Figure 3 Components Vo1-Vo4 are set based on the comparator controls seen in Figure 4); and cause each of the plurality of holding capacitors to discharge during the respective one of the plurality of voltage steps and recharge outside the respective one of the plurality of voltage steps in each of the plurality of voltage generation cycles (Figures 15-16 and 26-28 show timing diagrams wherein during a certain portion Vo1-Vo4 are discharged and outside of that portion the capacitors are charged).
Regarding claim 2, Ravi teaches all the limitations of claim 1. Ravi further teaches wherein the control circuit is further configured to cause the plurality of holding capacitors to concurrently provide the plurality of voltages in each of the plurality of voltage generation cycles (Paragraphs 0203 “Multiple switches 204a may be simultaneously or concurrently closed, thereby simultaneously or concurrently providing an identical voltage (based on the parallel connection to the inductor 202) to the corresponding output rails”).
Regarding claim 3, Ravi teaches all the limitations of claim 1. Ravi further teaches wherein the plurality of voltages is generated monotonically in the plurality of voltage steps (Figure 26 shows that the plurality of voltages are generated monotonically).
Regarding claim 4, Ravi teaches all the limitations of claim 1. Ravi further teaches wherein the control circuit is further configured to assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with one of: a sequential order and a non-sequential order (Figure 26 shows that the plurality of voltages are generated in a sequential order; Paragraph 0203 highlights an operation of concurrent operation thus teaching a non-sequential order).
Regarding claim 5, Ravi teaches all the limitations of claim 1. Ravi further teaches wherein the control circuit is further configured to assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with one of: an ascending order and a descending order (Figure 26 shows that the plurality of voltages are generated one after another thus showing an ascending order).
Regarding claim 6, Ravi teaches all the limitations of claim 1. Ravi further teaches a charging circuit coupled between a common node and the plurality of holding capacitors (Figure 25 Components 204a-204n; Figure 25 Component 202 output is the common node), wherein the control circuit is further configured to: receive a reference voltage at the common node in each of the plurality of voltage steps that indicates the respective level of the plurality of voltages (Figure 4 shows each Component 204a; Component 202 output is outputting Component Vo1-Vo4; Figure 4 Components 404 and 406 receive the voltage at the output of Component 202); and control the charging circuit to thereby cause each of the plurality of holding capacitors to discharge during the respective one of the plurality of voltage steps and recharge outside the respective one of the plurality of voltage steps in each of the plurality of voltage generation cycles (Figures 15-16 and 26-28 show timing diagrams wherein during a certain portion Vo1-Vo4 are discharged and outside of that portion the capacitors are charged).
Regarding claim 7, Ravi teaches all the limitations of claim 7. Ravi further teaches a voltage supply circuit coupled to the common node (Figure 25 Components 206+208+202+210), wherein the control circuit is further configured to determine a duty cycle signal for each of the plurality of voltage steps to thereby cause the voltage supply circuit to generate the reference voltage at the common node in each of the plurality of voltage steps (Figure 18 shows Figure 4 in further detail; Paragraph 0206 “The system 1800 may also include a switch controller 1802. The SIMO converter 104 may correspond to the SIMO converter 104 described above in relation to FIG. 4.”; Figure 18 Component 1838 is a signal that determines the duty cycle of Components 206+208+202+210 which are used to generate the voltage at the output of Component 202).
Regarding claim 12, Ravi teaches a wireless device comprising a multi-voltage power management integrated circuit (Figures 3-4; Paragraph 0106 highlights the system is an integrated chip; Figures 57 and 60 shows that the converter can be within a wireless device) (PMIC), the multi-voltage PMIC comprises: a plurality of holding capacitors (Figure 3 Component Capacitors connected to Components Vo1, Vo2, Vo3 and Vo4; Figure 4 shows each Component 302a-302n in detail), each configured to provide a respective one of a plurality of voltages (Figure 3 Components Vo1, Vo2, Vo3 and Vo4) during a respective one of a plurality of voltage steps in each of a plurality of voltage generation cycles (Figure 26 shows a timing diagram that shows Components Vo1, Vo2, Vo3 and Vo4 are provided in voltage steps in each of the generation cycles); and a control circuit (Figure 4 Components 404+406; Figure 25 shows the overall controller used in Figures 3-4; Paragraph 0291 “FIG. 25 illustrates a block diagram of an example system 2500 that includes the SIMO 104… SIMO 104 may correspond to the SIMO 104 described above in relation to FIG. 4”; Figure 25 Components 2502+2504) configured to: receive a plurality of voltage targets, each indicating a respective level of the plurality of voltages in a respective one of the plurality of voltage generation cycles (Figure 4 Components 404 and 406 have voltage references; Figure 4 shows one Component 302 seen in Figure 3 therefore each Component 302 has Components 404 and 406 having reference voltages); assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with the plurality of voltage targets (Figure 3 Components Vo1-Vo4 are set based on the comparator controls seen in Figure 4); and cause each of the plurality of holding capacitors to discharge during the respective one of the plurality of voltage steps and recharge outside the respective one of the plurality of voltage steps in each of the plurality of voltage generation cycles (Figures 15-16 and 26-28 show timing diagrams wherein during a certain portion Vo1-Vo4 are discharged and outside of that portion the capacitors are charged).
Regarding claim 13, Ravi teaches all the limitations of claim 12. Ravi further teaches wherein the control circuit is further configured to cause the plurality of holding capacitors to concurrently provide the plurality of voltages in each of the plurality of voltage generation cycles (Paragraphs 0203 “Multiple switches 204a may be simultaneously or concurrently closed, thereby simultaneously or concurrently providing an identical voltage (based on the parallel connection to the inductor 202) to the corresponding output rails”).
Regarding claim 14, Ravi teaches all the limitations of claim 12. Ravi further teaches wherein the control circuit is further configured to assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with one of: a sequential order and a non-sequential order (Figure 26 shows that the plurality of voltages are generated in a sequential order; Paragraph 0203 highlights an operation of concurrent operation thus teaching a non-sequential order).
Regarding claim 15, Ravi teaches all the limitations of claim 12. Ravi further teaches wherein the control circuit is further configured to assign each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with one of: an ascending order and a descending order (Figure 26 shows that the plurality of voltages are generated one after another thus showing an ascending order).
Regarding claim 16, Ravi teaches all the limitations of claim 12. Ravi further teaches wherein the multi-voltage PMIC further comprises a charging circuit coupled between a common node and the plurality of holding capacitors (Figure 25 Components 204a-204n; Figure 25 Component 202 output is the common node), wherein the control circuit is further configured to: receive a reference voltage at the common node in each of the plurality of voltage steps that indicates the respective level of the plurality of voltages (Figure 4 shows each Component 204a; Component 202 output is outputting Component Vo1-Vo4; Figure 4 Components 404 and 406 receive the voltage at the output of Component 202); and control the charging circuit to thereby cause each of the plurality of holding capacitors to discharge during the respective one of the plurality of voltage steps and recharge outside the respective one of the plurality of voltage steps in each of the plurality of voltage generation cycles (Figures 15-16 and 26-28 show timing diagrams wherein during a certain portion Vo1-Vo4 are discharged and outside of that portion the capacitors are charged).
Regarding claim 17, Ravi teaches all the limitations of claim 16. Ravi further teaches wherein the multi-voltage PMIC further comprises a voltage supply circuit coupled to the common node (Figure 25 Components 206+208+202+210), wherein the control circuit is further configured to determine a duty cycle signal for each of the plurality of voltage steps to thereby cause the voltage supply circuit to generate the reference voltage at the common node in each of the plurality of voltage steps (Figure 18 shows Figure 4 in further detail; Paragraph 0206 “The system 1800 may also include a switch controller 1802. The SIMO converter 104 may correspond to the SIMO converter 104 described above in relation to FIG. 4.”; Figure 18 Component 1838 is a signal that determines the duty cycle of Components 206+208+202+210 which are used to generate the voltage at the output of Component 202).
Regarding claim 20, Ravi teaches a method for concurrently providing multiple voltages (Figures 3-4, 15-16 and 25-28; Figure 26 shows that Vo1, Vo2, Vo3 and Vo4 are outputted within one cycle thus within that cycle they are concurrently provided; Paragraph 0203 “Multiple switches 204a may be simultaneously or concurrently closed, thereby simultaneously or concurrently providing an identical voltage (based on the parallel connection to the inductor 202) to the corresponding output rails”) comprising: configuring a plurality of holding capacitors to each provide a respective one of a plurality of voltages (Figure 3 Component Capacitors connected to Components Vo1, Vo2, Vo3 and Vo4; Figure 4 shows each Component 302a-302n in detail) during a respective one of a plurality of voltage steps in each of a plurality of voltage generation cycles (Figure 3 Components Vo1, Vo2, Vo3 and Vo4); receiving (Figure 4 Components 404+406; Figure 25 shows the overall controller used in Figures 3-4; Paragraph 0291 “FIG. 25 illustrates a block diagram of an example system 2500 that includes the SIMO 104… SIMO 104 may correspond to the SIMO 104 described above in relation to FIG. 4”; Figure 25 Components 2502+2504) a plurality of voltage targets, each indicating a respective level of the plurality of voltages in a respective one of the plurality of voltage generation cycles (Figure 4 Components 404 and 406 have voltage references; Figure 4 shows one Component 302 seen in Figure 3 therefore each Component 302 has Components 404 and 406 having reference voltages); assigning each of the plurality of holding capacitors to the respective one of the plurality of voltage steps in accordance with the plurality of voltage targets (Figure 3 Components Vo1-Vo4 are set based on the comparator controls seen in Figure 4); and causing each of the plurality of holding capacitors to discharge during the respective one of the plurality of voltage steps and recharge outside the respective one of the plurality of voltage steps in each of the plurality of voltage generation cycles (Figures 15-16 and 26-28 show timing diagrams wherein during a certain portion Vo1-Vo4 are discharged and outside of that portion the capacitors are charged).
Allowable Subject Matter
Claims 8-11 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 8, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the charging circuit comprises: a plurality of input switches, each corresponding to a respective one of the plurality of holding capacitors and coupled to the common node; a plurality of output switches, each coupled to a respective one of the plurality of holding capacitors; and a charging current switching circuit provided in between the plurality of input switches and the plurality of output switches. Claims 9-11 depend upon claim 8.
Regarding claim 18, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the charging circuit comprises: a plurality of input switches, each corresponding to a respective one of the plurality of holding capacitors and coupled to the common node; a plurality of output switches, each coupled to a respective one of the plurality of holding capacitors; and a charging current switching circuit provided in between the plurality of input switches and the plurality of output switches. Claim 19 depends upon claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Khlat (US 2022/0200447 A1) teaches a fast-switching power management circuit operable to prolong battery life is provided. The power management circuit includes a voltage circuit that can generate an output voltage for amplifying an analog signal in a number of time intervals and a pair of hybrid circuits each causing the output voltage to change in any of the time intervals. A control circuit is configured to activate any one of the hybrid circuits during a preceding one of the time intervals to cause the output voltage to change in an immediately succeeding one of the time intervals. By starting the output voltage change earlier in the preceding time interval, it is possible to complete the output voltage change within a switching window in the succeeding time interval while concurrently reducing rush current associated with the output voltage change, thus helping to prolong battery life in a device employing the power management circuit.
Khlat (US 2022/0123744 A1) teaches a fast-switching power management circuit is provided. The fast-switching power management circuit is configured to generate an output voltage(s) based on an output voltage target that may change on a per-frame or per-symbol basis. In embodiments disclosed herein, the fast-switching power management circuit can be configured to adapt (increase or decrease) the output voltage(s) within a very short switching interval (e.g., less than one microsecond). As a result, when the fast-switching power management circuit is employed in a wireless communication apparatus to supply the output voltage(s) to a power amplifier circuit(s), the fast-switching power management circuit can quickly adapt the output voltage(s) to help improve operating efficiency and linearity of the power amplifier circuit(s).
Hang (US 2017/0194857 A1) teaches a voltage regulation circuit can include: a power stage circuit with a single inductor and a plurality of output circuits; each output circuit having an output control switch configured to control a duration of an on time of the output circuit, and an output switch control circuit configured to control the output control switch in accordance with an output voltage sampling signal, a reference current signal that represents an output current of the output circuit, and a clock signal, in order to maintain an output voltage of the output circuit as constant and to decrease interference from load variations of any other of the plurality of output circuits; and where the output control switches are controlled to be on in sequence in each switching period.
Perreault (US 9634577 B2) teaches an RF circuit that comprises a switched capacitor circuit to provide multiple outputs.
Perreault (US 11637531 B1) teaches a supply generator for wireless devices using a multi-output switched capacitor circuit.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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