NON-FINAL ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3, 4, 6-8, 11, 13-15, 18 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, 4, 6-8, 11, 13-15, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baumeister (US 20150089305 ) in view of Sagar (US 20210326229).
Regarding claim 1, Baumeister teaches An interrupt checker circuit, comprising: a timestamp checker circuit having a first input terminal coupled to an interrupt signal (“in the embodiment shown in FIG. 1 the interrupt checker device 22 may be connected to the first and second interrupt request output lines 16, 18 and may directly receive the signals sent on the interrupt request output lines 16, 18 and may be arranged to detect the selected interrupt request for confirmation” ¶23); a second input terminal of the timestamp checker circuit configured to receive a global time reference (“At least on of the one or more interrupt checker devices 22, 32 may comprise a timer unit 34 arranged to measure the assigned latency period and may also comprise a third memory unit 36 for storing a latency value associated with the particular selected interrupt request.” ¶32); the timestamp checker circuit configured to: record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference and compare a time difference between the second timestamp and the first timestamp to an expected duration and, based thereon, generate an error signal in response to the time difference being outside the expected duration (“The timer unit 34 may be arranged to measure a period of time between reception of the reception indication and reception of a confirmation of an output of the corresponding selected interrupt request on the one or more output lines 16, 18. The interrupt checker device 22, 32 may be arranged to compare the measured time until reception of confirmation with the latency value (which defines the assigned latency) stored in the third memory unit 36, and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32).
Baumeister does not teach the timestamp checker circuit configured to: record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference
Sagar teaches the timestamp checker circuit configured to: record a first timestamp corresponding to a first interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, record a second timestamp corresponding to a second interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference, (“The example global timestamp counter 724 contains a counter indicating the current timestamp for the SoC 302. In response to the statistics generator 720 requesting the current timestamp, the global timestamp counter 724 transmits the current time in a timestamp to the statistics generator 720” ¶52, figure 7). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the interrupt checking methods of Baumeister with the use of timestamps received from an external global time reference as taught by Sagar. Timestamps are one of multiple ways to record software events along with interrupts, which can be used to determine when failures occur (Sagar ¶27).
Regarding claim 3, Baumeister teaches wherein the timestamp checker circuit is further configured to: record a third timestamp corresponding to a third interrupt event at the first input terminal of the timestamp checker circuit based on the global time reference and compare a second time difference between the third timestamp and the second timestamp to the expected duration and, based thereon generate a second error signal in response to the second time difference being outside the expected duration (“the interrupt checker device 22 may, for example, be connected to multiple of the plurality of interrupt request input lines 14, for example all interrupt request input lines” ¶26 “…This may allow to check other or more than the highest priority IRQ, as well as to check what the actual latencies are.” ¶32).
Regarding claim 4, Baumeister teaches wherein the expected duration includes a tolerance value, and wherein the error signal is generated in response to the time difference being outside the tolerance value (“and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32).
Regarding claim 6, Baumeister teaches wherein the interrupt signal is an asynchronous interrupt signal, and wherein the first interrupt event corresponds to completion of an activation of a function and an interrupt event for the function (“At least one of the one or more interrupt checker devices 22, 32 may be connected to the processing device 20, to receive from the processing device 20 an indication confirming completion of an interrupt service routine (ISR) associated with the corresponding selected interrupt service request.” ¶34). The indication of a completed interrupt service routine upon completion without mention of any synchronization is interpreted as an asynchronous signal.
Regarding claim 7, Baumeister teaches further comprising a plurality of registers for configuring the timestamp checker circuit and storing the first timestamp and the second timestamp (“A memory unit 24, 26 may, for example, be a register.” ¶24, “and may also comprise a third memory unit 36 for storing a latency value associated with the particular selected interrupt request.” ¶32).
Regarding claim 8, Baumeister teaches An interrupt checker circuit, comprising: a first timestamp checker circuit having a first input terminal coupled to a first interrupt signal, …for the first interrupt signal and generate a first error signal in response to the first elapsed time being outside a first expected duration (“The interrupt checker device 22, 32 may be arranged to compare the measured time until reception of confirmation with the latency value (which defines the assigned latency) stored in the third memory unit 36, and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32); and a second timestamp checker circuit having a first input terminal coupled to a second interrupt signal, the second timestamp checker circuit configured to determine a second elapsed time between two consecutive interrupt events for the second interrupt signal and generate a second error signal in response to the second elapsed time being outside a second expected duration (“At least on of the one or more interrupt checker devices 22, 32 may comprise a timer unit 34 arranged to measure the assigned latency period and may also comprise a third memory unit 36 for storing a latency value associated with the particular selected interrupt request.” ¶32). Sagar teaches the first timestamp checker circuit configured to determine a first elapsed time between two consecutive interrupt events (“The example global timestamp counter 724 contains a counter indicating the current timestamp for the SoC 302. In response to the statistics generator 720 requesting the current timestamp, the global timestamp counter 724 transmits the current time in a timestamp to the statistics generator 720” ¶52).
Regarding claim 11, Baumeister teaches he interrupt checker circuit of claim 8, wherein the first expected duration and the second expected duration include a corresponding tolerance value, and wherein the first error signal and the second error signal are generated in response to the respective elapsed time being outside the corresponding tolerance value (“and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32).
Regarding claim 13, Baumeister teaches wherein the first interrupt signal is an asynchronous interrupt signal, and wherein a first interrupt event of the two consecutive interrupt events corresponds to completion of an activation of a function and a second interrupt event of the two consecutive interrupt events correspond to an interrupt event for the function (“ At least one of the one or more interrupt checker devices 22, 32 may be connected to the processing device 20, to receive from the processing device 20 an indication confirming completion of an interrupt service routine (ISR) associated with the corresponding selected interrupt service request.” ¶34).
Regarding claim 14, Baumeister teaches , further comprising a plurality of registers for configuring the first timestamp checker circuit and the second timestamp checker circuit. (“A memory unit 24, 26 may, for example, be a register.” ¶24, “and may also comprise a third memory unit 36 for storing a latency value associated with the particular selected interrupt request.” ¶32).
Regarding claim 15, Baumeister teaches A method of operating an interrupt checker circuit, the method comprising: determining, ….determining, by a second timestamp checker circuit of the interrupt checker circuit, a second elapsed time between two consecutive interrupt events for a second interrupt signal; (“The timer unit 34 may be arranged to measure a period of time between reception of the reception indication and reception of a confirmation of an output of the corresponding selected interrupt request on the one or more output lines 16, 18. The interrupt checker device 22, 32 may be arranged to compare the measured time until reception of confirmation with the latency value (which defines the assigned latency) stored in the third memory unit 36” ¶32); generating, by the first timestamp checker circuit, a first error signal in response to the first elapsed time being outside a first expected duration; and generating, by the second timestamp checker circuit, a second error signal in response to the second elapsed time being outside a second expected duration (“and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32). Sagar teaches by a first timestamp checker circuit of the interrupt checker circuit, a first elapsed time between two consecutive interrupt events for a first interrupt signal; (“The example global timestamp counter 724 contains a counter indicating the current timestamp for the SoC 302. In response to the statistics generator 720 requesting the current timestamp, the global timestamp counter 724 transmits the current time in a timestamp to the statistics generator 720” ¶52).
Regarding claim 18, Baumeister teaches The method of claim 15, wherein the first expected duration and the second expected duration include a corresponding tolerance value, and wherein the first error signal and the second error signal are generated in response to the respective elapsed time being outside the corresponding tolerance value (“and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32).
Regarding claim 20, Baumeister teaches wherein the first interrupt signal is an asynchronous interrupt signal, and wherein a first interrupt event of the two consecutive interrupt events corresponds to completion of an activation of a function and a second interrupt event of the two consecutive interrupt events correspond to an interrupt event for the function (“At least one of the one or more interrupt checker devices 22, 32 may be connected to the processing device 20, to receive from the processing device 20 an indication confirming completion of an interrupt service routine (ISR) associated with the corresponding selected interrupt service request.” ¶34).
Claim(s) 2, 10 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baumeister and Sagar in view of Bollu (US 20210406111).
Regarding claim 2, Baumeister teaches a multiplexer having a first input terminal coupled to the output of the free-running counter circuit (“Also, plurality of connections may be replaced with a single connections that transfers multiple signals serially or in a time multiplexed manner.” ¶45); a second input terminal of the multiplexer coupled to an output terminal of an external time base, the external time base configured to provide a second reference timestamp at the output of the external time base, the multiplexer configured to select between the first reference timestamp and the second reference timestamp to forward to the timestamp checker circuit as the global time reference (“For instance when directly monitoring the output of the interrupt controller device 12, the latency period may refer to a maximum period of time allowed between receiving the reception indication by the interrupt checker device 12 and observing the selected interrupt request on the one or more output lines 16, 18.” ¶28). Baumeister does not teach a free-running counter circuit configured to generate a first reference timestamp at an output of the free-running counter circuit.
Bollu teaches a free-running counter circuit configured to generate a first reference timestamp at an output of the free-running counter circuit (“In other exemplary embodiments, the predefined global watchdog reference criterion and predefined local watchdog reference criteria may for example be larger than zero, the counter value may be incremented during each watchdog cycle” ¶33, “The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock. In other embodiments, the system clock may be used for providing the clock signal” ¶34). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the time based integrity checking circuits taught by Baumeister with the use of a free-running counter circuit as taught by Bollu. A watchdog counter is another example of a global reference or timer, which Baumeister already teaches (¶32). Therefore, it would have been obvious to substitute an interrupt timer with a watchdog using a free-running timer, both keep track of a time period between interrupt events.
Regarding claim 10, Bollu teaches a free-running counter circuit configured to generate a first reference timestamp at an output of the free-running counter circuit (“In other exemplary embodiments, the predefined global watchdog reference criterion and predefined local watchdog reference criteria may for example be larger than zero, the counter value may be incremented during each watchdog cycle” ¶33, “The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock. In other embodiments, the system clock may be used for providing the clock signal” ¶34).. Baumeister teaches a multiplexer having a first input terminal coupled to the output of the free-running counter circuit (“Also, plurality of connections may be replaced with a single connections that transfers multiple signals serially or in a time multiplexed manner.” ¶45); a second input terminal of the multiplexer coupled to an output terminal of an external time base, the external time base configured to provide a second reference timestamp at the output of the external time base, the multiplexer configured to select between the first reference timestamp and the second reference timestamp to forward to the first timestamp checker circuit and the second timestamp checker circuit as a global time reference to determine the first elapsed time and the second elapsed time (“For instance when directly monitoring the output of the interrupt controller device 12, the latency period may refer to a maximum period of time allowed between receiving the reception indication by the interrupt checker device 12 and observing the selected interrupt request on the one or more output lines 16, 18.” ¶28).
Regarding claim 17, Bollu teaches further comprising: generating, by a free-running counter circuit of the interrupt checker circuit, a first reference timestamp at an output of the free-running counter circuit; (“In other exemplary embodiments, the predefined global watchdog reference criterion and predefined local watchdog reference criteria may for example be larger than zero, the counter value may be incremented during each watchdog cycle” ¶33, “The clock signal may in various embodiments be provided by a free-running timer 108, which may be part of the watchdog circuit 200, e.g. decoupled from a system clock. In other embodiments, the system clock may be used for providing the clock signal” ¶34). Baumeister teaches and forwarding, by a multiplexer of the interrupt checker circuit, the first reference timestamp or a second reference timestamp as a global time reference for the first timestamp checker circuit and the second timestamp checker circuit to determine the first elapsed time and the second elapsed time, wherein the second reference timestamp is generated externally to the interrupt checker circuit (“For instance when directly monitoring the output of the interrupt controller device 12, the latency period may refer to a maximum period of time allowed between receiving the reception indication by the interrupt checker device 12 and observing the selected interrupt request on the one or more output lines 16, 18.” ¶28).
Claim(s) 5, 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baumeister and Sagar in view of Nishimura (US 20080010563).
Regarding claim 5, Baumeister does not teach wherein the interrupt signal is a synchronous interrupt signal, and wherein the second interrupt event and the first interrupt event are periodic interrupt events of the synchronous interrupt signal.
Nishimura teaches wherein the interrupt signal is a synchronous interrupt signal, and wherein the second interrupt event and the first interrupt event are periodic interrupt events of the synchronous interrupt signal(“The initial task T1 instructs the CPU 21 to activate a timer 29 for generating a periodic timer interrupt at regular intervals. In the first embodiment, the timer 29 is, for example, configured to generate a periodic timer interrupt at 1 ms (millisecond). The timer 29 can be installed as a hardware component or a software component in the microcomputer 3.” ¶88). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the interrupt checking methods of Baumeister with the synchronous interrupts of Nishimura. This would allow the control unit to quickly detect hang-ups in program execution (Nishimura ¶257).
Regarding claim 12, Nishimura teaches wherein the first interrupt signal is a synchronous interrupt signal, and wherein the two consecutive interrupt events are periodic interrupt events of the synchronous interrupt signal. (“The initial task T1 instructs the CPU 21 to activate a timer 29 for generating a periodic timer interrupt at regular intervals. In the first embodiment, the timer 29 is, for example, configured to generate a periodic timer interrupt at 1 ms (millisecond). The timer 29 can be installed as a hardware component or a software component in the microcomputer 3.” ¶88).
Regarding claim 19, Nishimura teaches wherein the first interrupt signal is a synchronous interrupt signal, and wherein the two consecutive interrupt events are periodic interrupt events of the synchronous interrupt signal (“The initial task T1 instructs the CPU 21 to activate a timer 29 for generating a periodic timer interrupt at regular intervals. In the first embodiment, the timer 29 is, for example, configured to generate a periodic timer interrupt at 1 ms (millisecond). The timer 29 can be installed as a hardware component or a software component in the microcomputer 3.” ¶88).
Claim(s) 9 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Baumeister and Sagar in view of Chowdhary (US 20200167222).
Regarding claim 9, Baumeister teaches wherein the interrupt checker circuit further comprises a coupled interrupt checker circuit configured to: determine a time difference between an arrival of a first interrupt event of the first interrupt signal and an arrival of a first interrupt event of the second interrupt signal; compare the time difference to a third expected duration; and generate a third error signal in response to the time difference being outside the third expected duration (“The timer unit 34 may be arranged to measure a period of time between reception of the reception indication and reception of a confirmation of an output of the corresponding selected interrupt request on the one or more output lines 16, 18. The interrupt checker device 22, 32 may be arranged to compare the measured time until reception of confirmation with the latency value (which defines the assigned latency) stored in the third memory unit 36, and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32). Baumeister does not teach wherein the first interrupt signal and the second interrupt signal are redundant interrupt signals.
Chowdhary teaches wherein the first interrupt signal and the second interrupt signal are redundant interrupt signals (“In certain examples, a computing device may include a completely redundant interrupt system that is configured to identify error conditions, generate interrupts, transmit interrupts, and handle interrupts in response to a “primary” interrupt system failing in the manner described above.” ¶14). It would have been obvious for one of ordinary skill in the art prior to the filing of the claimed invention to combine the interrupt checking methods of Baumeister with the use of redundancy as taught by Chowdhary. In the event of an error, the separate redundant signal can be used in the event one has an error (Chowdhary ¶14).
Regarding claim 16, Chowdhary teaches wherein the first interrupt signal and the second interrupt signal are redundant interrupt signals (“In certain examples, a computing device may include a completely redundant interrupt system that is configured to identify error conditions, generate interrupts, transmit interrupts, and handle interrupts in response to a “primary” interrupt system failing in the manner described above.” ¶14). Baumeister teaches he method further comprising: determining, by a coupled interrupt checker circuit of the interrupt checker circuit, a time difference between an arrival of a first interrupt event of the first interrupt signal and an arrival of a first interrupt event of the second interrupt signal; comparing, by the coupled interrupt checker circuit, the time difference to a third expected duration; and generating, by the coupled interrupt checker circuit, a third error signal in response to the time difference being outside the third expected duration. (“The timer unit 34 may be arranged to measure a period of time between reception of the reception indication and reception of a confirmation of an output of the corresponding selected interrupt request on the one or more output lines 16, 18. The interrupt checker device 22, 32 may be arranged to compare the measured time until reception of confirmation with the latency value (which defines the assigned latency) stored in the third memory unit 36, and may generate the error indication if the measured period of time exceeds the stored latency value.” ¶32).
Conclusion
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/SEAN KEVIN MCNAMARA/Examiner, Art Unit 2113
/PHILIP GUYTON/Primary Examiner, Art Unit 2113