DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 26 is objected to because of the following informalities:
Claim 26 recites a “default secure destination” and that this “default secure destination is an unassigned address” in lines 1-2 of Claim 26. It is recommended by the Examiner to further clarify the role of this default secure destination in the context of Claim 16 which Claim 26 depends upon: Claim 26 does not currently recite how this default secure destination is used with regards to data preloading, nor does it explain how this address is considered unassigned.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 23 and 35 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claims 23 and 35, both claims recite “an error correction code, in particular a cyclic redundancy check”. The phrase “in particular” is akin to indefinite language such as “for example” and “such as”, and the phrase "in particular" therefore renders the claim indefinite because it is unclear whether the limitations following the phrase are part of the claimed invention. See MPEP § 2173.05(d).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 16, 25-28 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Jauss et al. (U.S. Pub. No. 2023/0021594 A1) hereinafter referred to as “Jauss”.
Regarding Claim 16:
Jauss teaches the following limitations:
A storage device, comprising: one or more special function registers (Par. [0039], Par. [0046], Par. [0229], Par. [0243]). Jauss teaches a computing device which is shown to have multiple memories for storage, including special function registers.
a preloading stage comprising a first preload register [first zone], wherein the preloading stage is configured to preload data in the first preload register before loading the preloaded data into the special function registers [second zone] (Par. [0065], Par. [0071], Par. [0072], Par. [0075], Par. [0079]). Jauss teaches receiving data in a first zone and validating such data in a buffer storage area before transmitting it to a second zone, which is considered trustworthy. Jauss teaches inter-core zone separation and implementation with register memories, therefore this suggests that the second trustworthy zone can be implemented using the special function registers.
wherein the preloading stage is further configured to perform a verification of the integrity of the preloaded data before loading said preloaded data into the special function registers (Par. [0079], Par. [0105], Par. [0168], Par. [0246]). Jauss teaches validating the data in the buffer storage area before loading the data into the second zone.
Regarding Claim 25:
Jauss teaches the following limitations:
wherein the preloading stage is further configured to generate an error message upon or after an unsuccessful verification of the integrity of the preloaded data (Par. [0097], Par. [0098], Par. [0246], Par. [0247]). Jauss teaches generating an error response in response to compromises in authenticity verifications, i.e. including that of the preloaded data.
Regarding Claim 26:
Jauss teaches the following limitations:
further comprising a default secure destination, wherein said default secure destination is an unassigned address (Par. [0039], Par. [0063]). Jauss teaches the device having different memory devices with memory addresses, and these can be considered default secure destinations and unassigned under the broadest reasonable interpretation, as the claims do not specify how this destination is considered default or unassigned in the context of independent claim 16, nor does the applicant’s specification define a default secure destination.
Regarding Claim 27:
Jauss teaches the following limitations:
An interface unit comprising a storage device, wherein the storage device comprises: one or more special function registers (Par. [0039], Par. [0046], Par. [0229], Par. [0243]).
a preloading stage comprising a first preload register, wherein the preloading stage is configured to preload data in the first preload register before loading the preloaded data into the special function registers (Par. [0065], Par. [0071], Par. [0072], Par. [0075], Par. [0079]).
wherein the preloading stage is further configured to perform a verification of the integrity of the preloaded data before loading said preloaded data into the special function registers (Par. [0079], Par. [0105], Par. [0168], Par. [0246]).
Regarding Claim 28:
Jauss teaches the following limitations:
A method of operating a storage device, wherein: (Par. [0039], Par. [0046], Par. [0229], Par. [0243]).
a preloading stage comprised in the storage device preloads data in a first preload register before loading the preloaded data into one or more special function registers comprised in the storage device (Par. [0065], Par. [0071], Par. [0072], Par. [0075], Par. [0079]).
the preloading stage performs a verification of the integrity of the preloaded data before loading said preloaded data into the special function registers (Par. [0079], Par. [0105], Par. [0168], Par. [0246]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17, 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jauss as applied to claim 16 above, and further in view of Critelli et al. (U.S. Pub. No. 2019/0354726 A1) hereinafter referred to as “Critelli”.
Regarding Claim 17:
Critelli teaches the following limitations:
wherein the preloading stage further comprises a second preload register (Par. [0103], Par. [0104], Par. [0105], Par. [0117]). Critelli teaches that the data integrity of a register can be verified using a cyclic redundancy check (CRC) register which stores a checksum.
and wherein the preloading stage is configured to perform the verification by calculating a checksum on the preloaded data and comparing said checksum with a reference checksum stored in the second preload register (Par. [0103], Par. [0104], Par. [0105], Par. [0117]). This CRC register is compared with a computed checksum for integrity verification.
Jauss teaches integrity verification by preloading data using registers but does not teach second register storing a checksum. Critelli however teaches that register data validation can be implemented by storing an expected cyclic redundancy check value in a separate register. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the integrity validation of Jauss with the CRC checking of Critelli in order to gain the predictable result of verifying preloaded data using a checksum stored in a second register. One of ordinary skill in the art would have recognized that the integrity verification of Jauss and Critelli are alternative substitutes as Jauss teaches hash/signature verification and Critelli teaches using a CRC, and that Critelli is compatible with the system of Jauss as both are directed towards verifying data. Therefore, one of ordinary skill in the art would have recognized that the preloaded data can be verified using a CRC checksum in a second register as done in Critelli in combination with the system of Jauss.
Regarding Claim 22:
Critelli teaches the following limitations:
wherein the reference checksum is a pre-calculated checksum (Par. [0103], Par. [0104], Par. [0105], Par. [0117]). The checksum in Critelli is a pre-calculated CRC checksum.
The reasons for motivation/combination of references remain the same as in Claim 17 above.
Regarding Claim 23:
Critelli teaches the following limitations:
wherein the pre-calculated checksum is based on an error detection code, in particular a cyclic redundancy check, or on an XOR- based longitudinal parity check (Par. [0103], Par. [0104], Par. [0105], Par. [0117]). The checksum in Critelli is a CRC checksum.
The reasons for motivation/combination of references remain the same as in Claim 17 above.
Regarding Claim 24:
Jauss teaches the following limitations:
wherein the reference checksum has been pre-calculated by software or firmware (Par. [0168], Par. [0169], Par. [0221]). Jauss teaches a hardware security module for integrity verification which suggests software/firmware being used for calculation in combination with Critelli.
Claims 29, 34-35 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jauss as applied to claim 28 above, and further in view of Critelli.
Regarding Claim 29:
Critelli teaches the following limitations:
further comprising storing a reference checksum in a second preload register comprised in the preloading stage (Par. [0103], Par. [0104], Par. [0105], Par. [0117]).
wherein the preloading stage performs the verification by calculating a checksum on the preloaded data and comparing said checksum with the reference checksum stored in the second preload register (Par. [0103], Par. [0104], Par. [0105], Par. [0117]).
Jauss teaches integrity verification by preloading data using registers but does not teach second register storing a checksum. Critelli however teaches that register data validation can be implemented by storing an expected cyclic redundancy check value in a separate register. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to substitute the integrity validation of Jauss with the CRC checking of Critelli in order to gain the predictable result of verifying preloaded data using a checksum stored in a second register. One of ordinary skill in the art would have recognized that the integrity verification of Jauss and Critelli are alternative substitutes as Jauss teaches hash/signature verification and Critelli teaches using a CRC, and that Critelli is compatible with the system of Jauss as both are directed towards verifying data. Therefore, one of ordinary skill in the art would have recognized that the preloaded data can be verified using a CRC checksum in a second register as done in Critelli in combination with the system of Jauss.
Regarding Claim 34:
Critelli teaches the following limitations:
wherein the reference checksum is a pre-calculated checksum (Par. [0103], Par. [0104], Par. [0105], Par. [0117]).
The reasons for motivation/combination of references remain the same as in Claim 29 above.
Regarding Claim 35:
Critelli teaches the following limitations:
wherein the pre-calculated checksum is based on an error detection code, in particular a cyclic redundancy check, or on an XOR- based longitudinal parity check (Par. [0103], Par. [0104], Par. [0105], Par. [0117]).
The reasons for motivation/combination of references remain the same as in Claim 29 above.
Allowable Subject Matter
Claims 18-21, 30-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Related Art
The following prior art made of record and cited on PTO-892, but not relied upon, is considered pertinent to applicant’s disclosure:
Yazdani (U.S. Pub. No. 2013/0160121 A1) – Includes methods regarding checksums in registers
Hampel et al. (U.S. Pub. No. 2016/0028728 A1) – Includes methods regarding protected registers
Li et al. (U.S. Pub. No. 2021/0240382 A1) – Includes methods regarding checking register data
Berger et al. (U.S. Pub. No. 2018/0121117 A1) – Includes methods regarding error correction codes for registers
Narala (U.S. Pub. No. 2021/0406207 A1) – Includes methods regarding preload registers
Marinet et al. (U.S. Pub. No. 2013/0159791 A1) – Includes methods regarding fault detection
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN V VO whose telephone number is (571)272-2505. The examiner can normally be reached M-F 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynn Feild can be reached on (571)272-2092. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/E.V.V./Examiner, Art Unit 2431 /MICHAEL R VAUGHAN/Primary Examiner, Art Unit 2431