DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 8, 11-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ko (US 2014/0239270) in view of Cho (US 2022/0037447) and Zhang (US 2022/0344448)
Regarding claim 1, Ko teaches A display panel, comprising: a substrate (Figs. 5-6 substrate 110); a first light emitting transistor (Figs. 5-6 transistor T6) and a driving transistor (Fig. 5-6 transistor T1) formed over the substrate (Figs. 5-6); an interlayer insulating film formed to cover the first light emitting transistor and the driving transistor (Fig. 5-6 layer ILD2 and ILD3 are insulating layer); a first planarization layer formed on the interlayer insulating film (Figs. 5-6 layer PL); a link line formed on the first planarization layer and electrically connected to the first light emitting transistor through the first planarization layer and the interlayer insulating film (Figs. 5-6 link line CM3,CM2,CM1 extend from first planarization layer PL to drain of emission transistor T6); a second insulation layer formed to cover the link line (Fig. 5-6 ILD3) ; and a light emitting element formed on the second insulation layer (anode 120 of OLED seen in Fig. 2), in which a anode ode electrode is electrically connected to the link line through a drilling area (Figs. 5-6 hole path for CM1-3 to connect the OLED element to the drain of the emission transistor T6). Although Ko teaches the limitations as discussed above, he does not explicitly teach a cathode electrode electrically connected to a link connected to a light emitting transistor and the light emitting element including an anode electrode, and emission layer, and a cathode electrode sequentially stacked on a planarization layer.
However in the field of manufacturing a display device, Cho teaches a cathode electrode electrically connected to a link connected to a light emitting transistor and the light emitting element including an anode electrode ([0208] upper electrode 1340 can be cathode or anode electrode), and emission layer (light emitting layer 1330), and a cathode electrode ([0205] lower electrode 1291 can be cathode or anode electrode) sequentially stacked on a planarization layer(Fig. 16 show elements sequentially stacked on planarization layer 1275. [0205]. lower electrode 1291 can be an anode electrode or a cathode).
Therefore it would have been obvious to one of ordinary skill in the art to combine the display device as taught by Ko with the display device as taught by Lee. This combination would provide improved display quality as taught by Cho. Although the combination teaches the limitations as discussed above, they fail to teach a second planarization layer to cover the link line.
However in the field of manufacturing a display device, Zhang teaches a second planarization layer to cover the link line (Fig. 5 second planarization layer 17 covers connection electrode 106 (link line), which connects OLED to transistor 101).
Therefore it would have been obvious to one of ordinary skill in the art to combine the display device as taught by Ko with the display device as taught by Cho and the manufacturing method as taught by Zhang. This combination would provide improved display quality as taught by Cho. Although the combination teaches the limitations as discussed above, they fail to teach a second planarization layer to cover the link line.
Regarding claim 11, Ko teaches A display device, comprising: a display panel including a plurality of subpixels (Fig. 1); a gate driving circuit configured to supply a plurality of gate signals to the display panel through a plurality of gate lines (Fig. 1 scan driving unit 200); a data driving circuit configured to supply a plurality of data voltages to the display panel through a plurality of data lines (Fig. 2 data driving unit 300); and a timing controller configured to control the gate driving circuit and the data driving circuit (control unit 500), display panel, comprising: a substrate (Figs. 5-6 substrate 110); a first light emitting transistor (Figs. 5-6 transistor T6) and a driving transistor (Fig. 5-6 transistor T1) formed over the substrate (Figs. 5-6); an interlayer insulating film formed to cover the first light emitting transistor and the driving transistor (Fig. 5-6 layer ILD2 and ILD3 are insulating layer); a first planarization layer formed on the interlayer insulating film (Figs. 5-6 layer PL); a link line formed on the first planarization layer and electrically connected to the first light emitting transistor through the first planarization layer and the interlayer insulating film (Figs. 5-6 link line CM3,CM2,CM1 extend from first planarization layer PL to drain of emission transistor T6); a second insulation layer formed to cover the link line (Fig. 5-6 ILD3) ; and a light emitting element formed on the second insulation layer (anode 120 of OLED seen in Fig. 2), in which a anode ode electrode is electrically connected to the link line through a drilling area (Figs. 5-6 hole path for CM1-3 to connect the OLED element to the drain of the emission transistor T6). Although Ko teaches the limitations as discussed above, he does not explicitly teach a cathode electrode electrically connected to a link connected to a light emitting transistor and the light emitting element including an anode electrode, and emission layer, and a cathode electrode sequentially stacked on a planarization layer.
However in the field of manufacturing a display device, Cho teaches a cathode electrode electrically connected to a link connected to a light emitting transistor and the light emitting element including an anode electrode ([0208] upper electrode 1340 can be cathode or anode electrode), and emission layer (light emitting layer 1330), and a cathode electrode ([0205] lower electrode 1291 can be cathode or anode electrode) sequentially stacked on a planarization layer(Fig. 16 show elements sequentially stacked on planarization layer 1275. [0205]. lower electrode 1291 can be an anode electrode or a cathode).
Therefore it would have been obvious to one of ordinary skill in the art to combine the display device as taught by Ko with the display device as taught by Lee. This combination would provide improved display quality as taught by Cho. Although the combination teaches the limitations as discussed above, they fail to teach a second planarization layer to cover the link line.
However in the field of manufacturing a display device, Lee teaches a second planarization layer to cover the link line (Fig. 5 second planarization layer 17 covers connection electrode 106 (link line), which connects OLED to transistor 101).
Therefore it would have been obvious to one of ordinary skill in the art to combine the display device as taught by Ko with the display device as taught by Cho and the manufacturing method as taught by Zhang. This combination would provide improved display quality as taught by Cho. Although the combination teaches the limitations as discussed above, they fail to teach a second planarization layer to cover the link line.
Regarding claims 2 and 12, Ko teaches wherein the interlayer insulating film includes: a first interlayer insulating film covering the first light emitting transistor (Figs. 5-6 ILD1 covers emission transistor T6); and a second interlayer insulating film covering the driving transistor formed on the first interlayer insulating film (Figs. 5-6 ILD2 covering driving transistor T1).
Regarding claims 3 and 13, Ko teaches a first conductive electrode formed over the substrate (Fig. 5-6 Cst2); and a second conductive electrode formed on the first interlayer insulating film and located between the first conductive electrode and the driving transistor( Figs. 5-6 Cst1).
Regarding claims 4 and 14, Ko teaches wherein the link line includes: a first link line formed on the interlayer insulating film and electrically connected to the first light emitting transistor through the interlayer insulating film (Figs. 5-6 CM2); and a second link line formed on the first planarization layer and electrically connected to the first link line through the first planarization layer (Figs. 5-6 CM3).
Regarding claims 5 and 15, Zhang teaches wherein the light emitting element includes: an anode electrode formed on the second planarization layer and extended to a bezel area (Fig. 5 anode 21); an emission layer formed in an open area of a bank on the anode electrode (Fig. 5 emission layer 24); and the cathode electrode formed to cover the emission layer( Fig. 5 cathode layer 25).
Regarding claims 8 and 18, Ko teaches a scan transistor configured to be controlled by a first scan signal and configured to transmit a data voltage through a data line (Fig. 2 transistor T2); a storage capacitor (Fig. 2 capacitor Cst); and a control circuit located between the cathode electrode of the light emitting element and a low-potential base voltage and configured to control operations of the driving transistor, the scan transistor, and the storage capacitor (Fig. 2 Transistor T4).
Allowable Subject Matter
Claims 6-7, 9-10, 16-17, and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ANDRE L MATTHEWS/ Primary Examiner, Art Unit 2621
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