DETAILED ACTION
This Office Action is in response to the Application filed 26 June 2026. Claims 1-20 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 5, 11, 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 5, Claim 4 (from which Claim 5 depends) claims “additional sub-staircase structures” and Claim 5 claims “further additional sub-staircase structures”. Claim 5 then claims “at least some of the steps of the additional sub-staircase structures”. It is unclear to which additional sub-staircase structures this is meant to refer.
For examination purposes, when Claim 5 claims “at least some of the steps of the additional sub-staircase structures” it will be treated as referring to the further additional sub-staircase structures of Claim 5.
Examiner suggests changing the “sub-staircase structures”, “additional sub-staircase structures”, and “further additional sub-staircase structures” to “first sub-staircase structures”, “second sub-staircase structures”, and “third sub-staircase structures” respectively.
Regarding Claim 11, Claim 11 claims “a conductive routing region”. It is unclear whether this refers to the routing structure (190) which is conductive or the isolation structures (148) which “form conductive routing structure regions for routing of conductive interconnections (e.g., electrical connections) of various components of the microelectronic device 100 to circuitry”. For purposes of examination, “a conductive routing region” will be treated as referring to the isolation structures (148).
Regarding Claim 19, Claim 19 claims “a first array region comprising first vertical stacks of memory cells comprising first vertical stacks of access devices horizontally neighboring first vertical stacks of access devices”. This appears to be a mistake as it is unclear how “first vertical stacks of access devices horizontally neighboring first vertical stacks of access devices”. The Claim will be interpreted as requiring “a first array region comprising first vertical stacks of memory cells comprising first vertical stacks of storage devices horizontally neighboring first vertical stacks of access devices” as in Claim 1.
Claim 19 further claims “a second array region comprising second vertical stacks of memory cells comprising second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices”. This appears to be a mistake as it is unclear how “second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices”. The Claim will be interpreted as requiring “a second array region comprising second vertical stacks of memory cells comprising second vertical stacks of storage devices horizontally neighboring second vertical stacks of access devices” to conform to the vertical stack in Claim 1.
Regarding Claim 20, Claim 20 depends from Claim 19 and is rejected for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-9, 12-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (US 2023/0309289 A1) in view of Kim et. al (US 2018/0174661 A1) and Son et. al (US 2024/0334699 A1)
.
Regarding Claim 1, Choi discloses (as shown in Fig. 6, 25C) A microelectronic device, comprising:
a memory array region ([0029] memory cell array 1) comprising vertical stacks of dynamic random access memory (DRAM) cells, ([0030] Each of the memory cells MC may include a switching device TR and a data storage element DS, which are electrically connected to each other in series. The switching device TR may be a field effect transistor FET, and the data storage element DS may be realized by a capacitor or a variable resistor.)
each of the DRAM cells (MC) comprising a storage device ([0085] In an embodiment, the data storage element DS may be a capacitor, and the data storage element DS may include the storage electrode SE, the plate electrode PE, and a capacitor dielectric layer CIL therebetween.) of a vertical stack of storage devices ([0086] the storage electrodes SE may be stacked in the third direction D3) and a horizontally neighboring access device of a vertical stack of access devices; ([0086] The storage electrode SE may be in contact with the second end portion of each channel pattern SP.)
a staircase region ([0040] may have a staircase structure on the second region WCR) substantially horizontally neighboring the memory array region (1) in a first horizontal direction, ([0065] The stacks ST may extend from the first region BCR to the second region WCR in the first direction D1)
the staircase region (WCR) comprising: a vertical stack of first conductive structures ([0065] word lines WLa and WLb) horizontally extending through the staircase region (WCR) in the first horizontal direction (D1), ([0065] Each of the stacks ST may include pad insulating patterns PLD and the word line pads PAD of the word lines WLa and WLb, which are alternately stacked in the second region WCR) (see An. Fig. 25C below, showing the staircase structure extending in the D1 direction)
the first conductive structures (WL) in contact with the DRAM cells; ([0039] In an embodiment, the switching device TR may include a transistor including a gate electrode, which is connected to the word line WL)
and sub-staircase structures (See An. Fig. 25C, showing the sub-staircase structure comprising adjacent word line pads in the D2 direction) individually comprising second conductive structures ([0065] word line pads PAD of the word lines WLa and WLb) in contact with the first conductive structures (WL) and horizontally extending from the first conductive structures (WL) in a second horizontal direction substantially perpendicular to the first horizontal direction, (See An. Fig. 25C, showing the PADS extending from the word lines WL in the WCR region)
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However, Choi fails to disclose:
each of the sub-staircase structures individually comprising at least four steps, each step of the at least four steps defined at horizontal boundaries of one of the second conductive structures defining the step.
Kim discloses (as shown in Fig. 4, 12) each of the sub-staircase structures individually comprising at least four steps, ([0054] For example, the pads P1 to P4 of the sequentially stacked electrodes ELa to ELd may form the first and second stair structures SS1 and SS2 on one of the first and second connection regions CNR1 and CNR2.)
each step of the at least four steps (P1 to P4) defined at horizontal boundaries of one of the second conductive structures defining the step. (Fig. 4, showing the pads PD1 to PD4 stacked on each other and extending the same distance in the D1 direction)
Son teaches that forming sub-staircase patterns can reduce the overall area of the memory device. ([0094] Meanwhile, in some implementations, a staircase pattern extending in the second direction D2 may be provided in plural and first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases, and thus an area of a single memory block BLK may be significantly reduced) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the second staircase structures of Kim with the sub-staircase structure in Choi in order to further reduce the area of the memory block by increasing the number of pads in the second staircase structure to be 4 as in Kim.
Regarding Claim 2, Choi further discloses (as shown in Fig. 25C) conductive contact structures ([0042] cell contact plugs CPLG) individually in contact with the second conductive structure (PAD) of each step of the sub-staircase structures. ([0042] The word lines WL may include pads PAD (e.g., “word line pads”), which are provided on the second region WCR and are connected to cell contact plugs CPLG)
Regarding Claim 3, Choi further discloses (as shown in Fig. 5B) wherein each conductive contact structure (CPLG) individually contacts the second conductive structure (PAD) on a first surface of the conductive contact structure horizontally extending in the second horizontal direction (See Fig. 5B)
However, Choi fails to disclose wherein each conductive contact structure individually contacts the second conductive structure on a vertically extending second surface.
It would have been obvious to a person having ordinary skill in the art before the effective filing date to have each conductive contact structure individually contacts the second conductive structure on a vertically extending second surface. Embedding contacts is a commonly used technique that decreases contact resistance. It would have been obvious to embed the cell contact plugs in the word line pads in order to reduce contact resistance. Doing so would result in the cell contact plugs contacting the word line pads on a vertical surface as shown in the Fig. below.
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Regarding Claim 4, Choi further discloses (as shown in Fig. 25C) additional sub-staircase structures horizontally spaced from the sub-staircase structures in the second horizontal direction, (See Fig. An. 25C, showing sub-staircase structures SS2)
at least some of the steps of the additional sub-staircase structures (SS22) vertically offset and within horizontal boundaries in the first horizontal direction of a corresponding step of the sub-staircase structures (SS1). (See An. Fig. 4)
Regarding Claim 5, Choi further discloses (as shown in Fig. 25C) further additional sub-staircase structures (SS3) horizontally spaced from the sub-staircase structures (SS2) in the second horizontal direction,
at least some of the steps of the additional sub-staircase structures (SS3) vertically aligned and within horizontal boundaries in the first horizontal direction of a corresponding step of the sub-staircase structures (SS1). (See An. Fig. 4)
Regarding Claim 6, Son discloses (as shown in Fig. 6) an additional memory array region ([0074] second staircase pattern SP2) spaced from the memory array region ([0074] first staircase pattern SP1) in the first horizontal direction ([0074] second direction D2) by the staircase region. ([0074] In this case, the staircase pattern may include a first stair pattern SP1, descending in the second direction D2, and a second staircase pattern SP2 ascending in the second direction D2)
Son teaches that having a descending staircase pattern next to an ascending staircase pattern can reduce the overall length of the staircases. ([0094] first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the descending and ascending staircase patterns of Son with Choi in view of Kim in order to reduce the length of the staircases.
Regarding Claim 7, Son further discloses (as shown in Fig. 6, 13) wherein at least one of the second conductive structures is in contact with at least one of the first conductive structures in contact with some of the DRAM cells of the memory array region (SP1) and some of additional DRAM cells of the additional memory array region (SP2). (See Fig. 13, showing the lowermost word line of the staircase is shared between both staircases)
Regarding Claim 8, Kim further discloses (as shown in Fig. 4) wherein a pitch of the sub-staircase structures ([0049] pad sections PS) in the first horizontal direction is about two times a pitch of the vertical stacks of DRAM cells ([0049] electrode structures ST1 and ST2) in the first horizontal direction. ([0049] the electrode structures ST1 and ST2 may be arranged along the second direction D2 at a pitch corresponding to a first horizontal distance Hd1, and the pad sections PS of the electrode structures ST1 and ST2 and other pad sections PS of other electrode structures ST1 and ST2 may be arranged along the second direction D2 at a pitch corresponding to a second horizontal distance Hd2 greater than the first horizontal distance Hd1. For example, the second horizontal distance Hd2 may be more than about twice the first horizontal distance Hd1.)
Regarding Claim 9, Choi further discloses (as shown in Fig. 5B, 25C) a liner material ([0160] etch stop layer ESL) overlying the at least four steps of each of the sub-staircase structures. ([0160] an etch stop layer ESL may be formed to conformally cover the staircase structure)
Regarding Claim 12, Choi discloses (as shown in Fig. 6, 25C) A microelectronic device, comprising:
a memory array region ([0029] memory cell array 1) comprising vertical stacks of dynamic memory cells, ([0030] Each of the memory cells MC may include a switching device TR and a data storage element DS, which are electrically connected to each other in series. The switching device TR may be a field effect transistor FET, and the data storage element DS may be realized by a capacitor or a variable resistor.)
vertical stacks of access devices; ([0030] Each of the memory cells MC may include a switching device TR)
vertical stacks of storage devices ([0085] In an embodiment, the data storage element DS may be a capacitor, and the data storage element DS may include the storage electrode SE, the plate electrode PE, and a capacitor dielectric layer CIL therebetween.) ([0086] the storage electrodes SE may be stacked in the third direction D3) horizontally neighboring the vertical stacks of access devices; ([0086] The storage electrode SE may be in contact with the second end portion of each channel pattern SP.)
and portion of a vertical stack structure ([0065] word lines WLa and WLb) ([0065] Each of the stacks ST may include pad insulating patterns PLD and the word line pads PAD of the word lines WLa and WLb, which are alternately stacked in the second region WCR) comprising substantially linear first conductive structures ([0042] The word lines WL may extend in the first direction D1 that is parallel to the first surface of the lower insulating layer 300.) horizontally extending through the vertical stacks of memory cells, ([0041] The word lines WL may extend from the first region BCR to the second region WCR)
the substantially linear first conductive structures (WL) neighboring the memory cells of the vertical stack of memory cells; ([0039] In an embodiment, the switching device TR may include a transistor including a gate electrode, which is connected to the word line WL)
and a staircase region ([0040] may have a staircase structure on the second region WCR) horizontally neighboring the memory array region (1), ([0065] The stacks ST may extend from the first region BCR to the second region WCR in the first direction D1)
the staircase region comprising a staircase structure comprising: an additional portion of the vertical stack structure horizontally extending in a first direction from the memory array region through the staircase region; (see An. Fig. 25C below, showing the staircase structure extending in the D1 direction)
and sub-staircase structures (See An. Fig. 25C, showing the sub-staircase structure comprising adjacent word line pads in the D2 direction) horizontally extending from the vertical stack structure in a second direction different than the first direction, (See An. Fig. 25C, showing the PADS extending from the word lines WL in the WCR region)
However, Choi fails to disclose: the sub-staircase structures individually comprising second conductive structures defining at least three steps of the sub-staircase structures.
Kim discloses (as shown in Fig. 4, 12) the sub-staircase structures individually comprising second conductive structures defining at least three steps of the sub-staircase structures. ([0054] For example, the pads P1 to P4 of the sequentially stacked electrodes ELa to ELd may form the first and second stair structures SS1 and SS2 on one of the first and second connection regions CNR1 and CNR2.)
Son teaches that forming sub-staircase patterns can reduce the overall area of the memory device. ([0094] Meanwhile, in some implementations, a staircase pattern extending in the second direction D2 may be provided in plural and first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases, and thus an area of a single memory block BLK may be significantly reduced) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the second staircase structures of Kim with the sub-staircase structure in Choi in order to further reduce the area of the memory block by increasing the number of pads in the second staircase structure to at least 3 as in Kim.
Regarding Claim 13, Son discloses (as shown in Fig. 6, 13) wherein the additional portion of the vertical stack structure ([0039] word lines WL1 to WLm (WL)) horizontally extends from the memory array region ([0074] first staircase pattern SP1), through the staircase region, and to an additional memory array region ([0074] second staircase pattern SP2). (See Fig. 13, showing the lowermost word line of the staircase is shared between both staircases)
Son teaches that having a descending staircase pattern next to an ascending staircase pattern can reduce the overall length of the staircases. ([0094] first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the descending and ascending staircase patterns of Son with Choi in view of Kim in order to reduce the length of the staircases.
Regarding Claim 14, Kim further discloses (as shown in Fig. 4) wherein the sub-staircase structures individually comprise four steps vertically descending in the second direction. ([0054] For example, the pads P1 to P4 of the sequentially stacked electrodes ELa to ELd may form the first and second stair structures SS1 and SS2 on one of the first and second connection regions CNR1 and CNR2.)
Regarding Claim 15, Choi further discloses (as shown in Fig. 25C) wherein the second conductive structures of the sub-staircase structures vertically descend in the first direction in a direction from the memory array region towards the staircase region. (See An. Fig. 25C, showing the pads descending in vertical location along the staircase region)
Regarding Claim 16, Son discloses (as shown in Fig. 7, 13) an additional portion of an additional stack structure (See An. Fig 7, showing the first and second stack structures) comprising
additional first conductive structures (See An. Fig. 7, showing Additional vertical stack structures in the second cell region CA2) horizontally extending in the first direction (D2) from the memory array region through the staircase region; (See An. Fig. 7)
and additional sub-staircase structures (See Fig. 13, showing both the ascending and descending stairs of ST2 have sub-staircases) comprising additional second conductive structures horizontally extending from the additional first conductive structures in the second direction, (See Fig. 13, showing the sub-staircases descend in the direction perpendicular the staircases)
the additional sub-staircase structures comprising a stadium structure in the first direction. ([0123] The first staircase ST1 and the second staircase ST2 may have a shape depressed from an upper surface in a third direction D3)
Regarding Claim 17, Son further discloses (as shown in Fig. 7, 13) wherein a vertically lowermost step of the additional sub-staircase structures is horizontally offset in the first direction from a vertically lowermost step of the sub-staircase structures. (See Fig. 7, showing the bottommost word lines (WL12) separated from each other)
Regarding Claim 18, Choi further discloses (as shown in Fig. 25C) conductive contact structures ([0042] cell contact plugs CPLG) individually in contact with the second conductive structures (PAD) in the second direction and in a vertical direction. ([0042] The word lines WL may include pads PAD (e.g., “word line pads”), which are provided on the second region WCR and are connected to cell contact plugs CPLG)
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (US 2023/0309289 A1) in view of Kim et. al (US 2018/0174661 A1) and Son et. al (US 2024/0334699 A1) as in Claim 9, and further in view of Lee (US 2017/0256551 A1)
Regarding Claim 11, Choi in view of Kim and Son fails to disclose a conductive routing region horizontally between the memory array region and the staircase region.
Lee discloses (as shown in Fig. 1E) a conductive routing region ([0044] remaining portions 128 (e.g., unremoved portions) of the additional insulating structures 106) horizontally between the memory array region and the staircase region. ([0046] the first opening 120a may be separated from an additional conductive structure 126 associated with the second stadium structure 118b and the second opening 120b by the remaining portion 128 of the additional insulating structure 106.)
Lee teaches that the remaining portion 128 laterally isolates adjacent stacks. ([0053] As a non-limiting example, as shown in FIG. 1F, in embodiments wherein each of the tiers 108 includes multiple conductive structures 126 (e.g., multiple conductive structures 126 laterally isolated from one another by the remaining portion 128 of one of the additional insulating structures 106 (FIG. 1D))) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the remaining portion 128 of Lee with Choi in view of Kim and Son in order to isolate multiple conductive structures.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (US 2023/0309289 A1) in view Son et. al (US 2024/0334699 A1) and Lee (US 2017/0256551 A1)
Regarding Claim 19, Choi discloses (as shown in Fig. 2, 6) a microelectronic device comprising:
a first array region ([0039] the cell array region CAR may include a first region or bit line connection region BCR) comprising first vertical stacks of memory cells comprising first vertical stacks of storage devices horizontally neighboring first vertical stacks of access devices; ([0030] Each of the memory cells MC may include a switching device TR and a data storage element DS, which are electrically connected to each other in series. The switching device TR may be a field effect transistor FET, and the data storage element DS may be realized by a capacitor or a variable resistor.)
a staircase region horizontally comprising staircase structures ( ([0040] The stack ST may extend in the first direction D1, which is parallel to the first surface of the lower insulating layer 300, and may have a staircase structure on the second region WCR.))
at least one of the staircase structures ([0040] The stack ST may extend in the first direction D1, which is parallel to the first surface of the lower insulating layer 300, and may have a staircase structure on the second region WCR.) comprising: a vertical stack comprising first conductive structures ([0040] The stack ST may include interlayer insulating patterns ILD and word lines WL, which are alternately stacked.) horizontally extending through the staircase region (WCR.) and through the first array region;
and conductive contact structures in ([0042] cell contact plugs CPLG) contact with the second conductive structures in the horizontal direction ([0042] The word lines WL may include pads PAD (e.g., “word line pads”), which are provided on the second region WCR and are connected to cell contact plugs CPLG) (See Fig. 25C)
extending away from the vertical stack and in a vertical direction. (See Fig. 25C)
sub-staircase structures (See An. Fig. 25C, showing the sub-staircase structure comprising adjacent word line pads in the D2 direction) comprising second conductive structures ([0065] word line pads PAD of the word lines WLa and WLb) horizontally extending in a horizontal direction extending away from the vertical stack, (See An. Fig. 25C, showing the PADS extending from the word lines WL in the WCR region)
the sub-staircase structures individually comprising steps vertically descending in the horizontal direction extending away from the vertical stack and defined by edges of the second conductive structures; (See An. Fig. 25C, showing the PADS extending from the word lines WL in the WCR region and forming steps in the D2 direction.)
and conductive contact structures ([0201] cell contact plug CPLGa or CPLGb) in contact with the second conductive structures (PAD) in the horizontal direction extending away from the vertical stack and in a vertical direction. ([0042] cell contact plugs CPLG) contact with the second conductive structures in the horizontal direction ([0042] The word lines WL may include pads PAD (e.g., “word line pads”), which are provided on the second region WCR and are connected to cell contact plugs CPLG) (See Fig. 25C)
However, Choi fails to disclose:
An electronic system, comprising: an input device; an output device;
a processor device operably coupled to the input device and the output device;
and a microelectronic device coupled to the processor device
a second array region comprising second vertical stacks of memory cells comprising second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices;
a staircase region horizontally between the first array region and the second array region and comprising staircase structures,
at least one of the staircase structures horizontally extending through the staircase region () and through the first array region and the second array region;
Son discloses (as shown in Fig. 7, 13) a second array region comprising second vertical stacks of memory cells ([0074] second staircase pattern SP2)
a staircase region horizontally between the first array region and the second array region and comprising staircase structures, (See Fig. 13, staircase patterns SP1, SP2 forming a depressed region)
at least one of the staircase structures horizontally extending through the staircase region and through the first array region (SP1) and the second array region (SP2); (See Fig. 13, showing the lowermost word line of the staircase is shared between both staircases)
Son teaches that having a descending staircase pattern next to an ascending staircase pattern can reduce the overall length of the staircases. ([0094] first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the descending and ascending staircase patterns of Son with Choi in view of Kim in order to reduce the length of the staircases.
While Son fails to disclose the second array region comprising second vertical stacks of memory cells comprising second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices, this would be obvious to a person having ordinary skill in the art before the effective filing date of the application from the combination of Choi and Son. Choi is directed to DRAM which has storage devices and access devices, while Son is directed to NAND devices which does not. Combining the arrangement in Son, which saves space, with the DRAM devices in Choi would obviously result in both vertical stacks containing storage devices next to access devices as shown in the vertical stack of Choi.
However, Son fails to disclose
An electronic system, comprising: an input device; an output device;
a processor device operably coupled to the input device and the output device;
and a microelectronic device coupled to the processor device
Lee discloses (as shown in Fig. 2, 6) An electronic system ([0123] The electronic system 600), comprising:
an input device ([0123] The electronic system 600 may further include one or more input devices 606);
an output device ([0123] The electronic system 600 may further include one or more output devices 608);
a processor device ([0123] The electronic system 600 may further include at least one electronic signal processor device 604 (often referred to as a “microprocessor”)) operably coupled to the input device and the output device; ([0123] The one or more input devices 606 and output devices 608 may communicate electrically with at least one of the memory device 602 and the electronic signal processor device 604.)
and a microelectronic device coupled to the processor device ([0123] The electronic signal processor device 604 may, optionally, include a semiconductor device structure substantially similar to an embodiment of one or more of the semiconductor device structures 100, 200, 300, 400, 500 shown in FIGS. 1A through 5) and comprising:
Neither Choi nor Son describe the system which the memory device is part of. Lee teaches that the memory device is part of a system including an input device, an output device, and a processor device operably coupled to the input device and the output device. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the teachings of Lee with Choi in view of Son in order to make an integrated device using the memory device of Choi in view of Son.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (US 2023/0309289 A1) in view of Son et. al (US 2024/0334699 A1) and Lee (US 2017/0256551 A1) as in Claim 19, and further in view of Kim et. al (US 2018/0174661 A1)
Regarding Claim 20, Choi in view of Son and Lee fails to disclose wherein each sub-staircase structure is defined by edges of four of the second conductive structures.
Kim discloses (as shown in Figs. 4, 12) wherein each sub-staircase structure is defined by edges of four of the second conductive structures. ([0054] For example, the pads P1 to P4 of the sequentially stacked electrodes ELa to ELd may form the first and second stair structures SS1 and SS2 on one of the first and second connection regions CNR1 and CNR2.)
Son teaches that forming sub-staircase patterns can reduce the overall area of the memory device. ([0094] Meanwhile, in some implementations, a staircase pattern extending in the second direction D2 may be provided in plural and first and second staircase patterns SP1 and SP2 in descending and ascending directions may be combined to reduce the overall length of staircases, and thus an area of a single memory block BLK may be significantly reduced) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to combine the second staircase structures of Kim with the sub-staircase structure in Choi in order to further reduce the area of the memory block by increasing the number of pads in the second staircase structure to be 4 as in Kim.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi et. al (US 2023/0309289 A1) in view of Kim et. al (US 2018/0174661 A1) and Son et. al (US 2024/0334699 A1) as in Claim 9, and further in view of Lee (Study of Etch Stop Layer on Characteristics of Amorphous Aluminum Oxide Thin Film)
Regarding Claim 10, Choi in view of Kim and Son fails to disclose wherein the liner material (ESL) comprises aluminum oxide.
Choi (Study of Etch Stop Layer) discloses wherein the etch stop layer comprises aluminum oxide. ([Abstract Line] Aluminum oxide compounds (AlOx, AlOC, AlON, etc.) are highly suitable for use as ESL)
Choi fails to disclose the material of the etch stop layer. Lee (Study of Etch Stop Layer) teaches that Aluminum Oxides are particularly suitable as etch stop layers in BEOL processes because due to the low dielectric constant between about 4 and 9, high etch selectivity, high density (2.5-3.8 g/cm ³ ) and pattern transfer capability. ([Abstract Lines] Aluminum oxide compounds (AlOx, AlOC, AlON, etc.) are highly suitable for use as ESL due to the low dielectric constant between about 4 and 9, high etch selectivity, high density (2.5-3.8 g/cm ³ ) and pattern transfer capability) Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to use Aluminum Oxide as the material of the etch stop layer in Choi due to the properties disclosed in Lee.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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