DETAILED ACTION
This action is in response to the application filed on 06/24/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 1 objected to because of the following informalities:
Regarding claim 1, it appears “a first supply” (line 4) should read “a first power supply”.
Regarding claim 1, it appears “a second supply (lines 6-7) should read “a second power supply”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 12 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 12, it is unclear if “a core” (line 1) refers to “one of the plurality of processor cores” (claim 10, line 2). The limitation will be interpreted as a core being one of the plurality of processor cores.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-7, & 17-19 are rejected under 35 U.S.C. 103 as being unpatentable over US Doc Id. US20180275704A1 (Hereinafter Li) in view of US Doc Id. US20080209236A1 (Hereinafter Shaver).
Regarding claim 1, Li discloses a multiple input linear voltage regulator [e.g. Figs. 2-5, element 210] comprising: an output port [e.g. Figs. 3 & 5, element OUT] configured to supply an output voltage to one or more processor components [e.g. Fig. 2, MCU]; a first regulating transistor [e.g. Fig. 5, element 512] operable to receive a first input voltage from a first supply [e.g. Fig. 5, element In1] and provide a first regulated voltage range to the output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”]; a second regulating transistor [e.g. Fig. 5, element 522] operable to receive a second input voltage from a second supply [e.g. Fig. 5, element In2] and provide a second regulated voltage range to the output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”], wherein the first input voltage is different from the second input voltage [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”].
Li fails to disclose a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage
Shaver teaches a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage [e.g. paragraph 0011, “The gate drive selector 20 provides a gate drive signal 22 (e.g., a voltage) to the controller 25. The controller 25 uses the gate drive signal 22 to turn on each of the power transistors Q1 and Q2 in an alternating fashion”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage as taught by Shaver to reduce power consumption.
Regarding claim 2, Li fails to disclose wherein the control circuit receives a signal indicative of the target output voltage from a power management controller of the one or more processor components.
Shaver teaches wherein the control circuit [e.g. Fig. 1, element 20] receives a signal indicative of the target output voltage [e.g. Fig, 1, element 32] from a power management controller [e.g. Fig. 1, element 25] of the one or more processor components [e.g. Fig. 1, element 30].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein the control circuit receives a signal indicative of the target output voltage from a power management controller of the one or more processor components as taught by Shaver to reduce power consumption.
Regarding claim 3, Li discloses the multiple input linear voltage regulator of claim 1 [e.g. Fig. 2-5, element 210], wherein the control circuit [e.g. Fig. 3, element 310] is configured to: operate only the first regulating transistor based on the target output voltage falling within the first regulated voltage range corresponding to the first regulating transistor [e.g. Table 1, second row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage]; and operate only the second regulating transistor based on the target output voltage falling within the second regulated voltage range corresponding to the second regulating transistor [e.g. Table 1, third row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage].
Regarding claim 4, Li fails to disclose the multiple input linear voltage regulator of claim 3, wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range.
Shaker teaches wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range [e.g. Fig. 3, element 72; paragraph 0027, “Accordingly, in the hysterisis section 72, either of the input voltages 18 and 19 may be used as the gate drive signal 22 depending on direction (downward or upward) that the processor current draw is changing”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”}.
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range as taught by Shaver to reduce power consumption.
Regarding claim 6, the multiple input linear voltage regulator of claim 1, wherein the first regulating transistor and the second regulating transistor are field effect transistors [e.g. paragraph 0038, “A switch transistor (e.g., an n-type MOS transistor) 531 is connected to the output stage unit 510 , and is controlled by the priority signal PRI 1 from the priority determination module 31”].
Regarding claim 7, Li discloses the multiple input linear voltage regulator of claim 1, wherein the multiple input linear voltage regulator is located in one of a substrate and an interposer of a processor [e.g. paragraph 0003, “the MCU has multiple input/output interfaces (I/O) and proper firmware to control those discrete components. Thus, this is a high cost, high power consumption, high complexity solution and requires large Printed Circuit Board (PCB) space”].
Regarding claim 17, Li discloses a method comprising: receiving , by a control circuit [e.g. Fig. 2, MCU]of a multiple input linear voltage regulator [e.g. Fig. 2, Dual Input Power Regulator], an indication of a target output voltage [e.g. Fig. 2-3, element EN] for one or more components of a processor [e.g. Fig. 2, element MCU], wherein the multiple input linear voltage regulator includes: a first regulating transistor [e.g. Fig. 5, element 512] operable to receive a first input voltage from a first supply [e.g. Fig. 5, element In1] and provide a first regulated voltage range to an output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”]; and a second regulating transistor [e.g. Fig. 5, element 522] operable to receive a second input voltage from a second supply [e.g. Fig. 5, element In2] and provide a second regulated voltage range to the output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”], and wherein the first input voltage is different from the second input voltage [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”].
Li fails to disclose a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage
Shaver teaches a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage [e.g. paragraph 0011, “The gate drive selector 20 provides a gate drive signal 22 (e.g., a voltage) to the controller 25. The controller 25 uses the gate drive signal 22 to turn on each of the power transistors Q1 and Q2 in an alternating fashion”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage as taught by Shaver to reduce power consumption.
Regarding claim 18, Li discloses operating only the first regulating transistor based on the target output voltage falling within the first regulated voltage range corresponding to the first regulating transistor [e.g. Table 1, second row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage]; and operating only the second regulating transistor based on the target output voltage falling within the second regulated voltage range corresponding to the second regulating transistor transistor [e.g. Table 1, third row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage].
Li fails to disclose selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage.
Shaver teaches selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage [e.g. paragraph 0011, “The gate drive selector 20 provides a gate drive signal 22 (e.g., a voltage) to the controller 25. The controller 25 uses the gate drive signal 22 to turn on each of the power transistors Q1 and Q2 in an alternating fashion”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a method selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage as taught by Shaver to reduce power consumption.
Regarding claim 19, Li fails to disclose the method of claim 18, wherein selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage includes: operating both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area between the first regulated voltage range and the second regulated voltage range.
Shaker teaches wherein selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage includes: operating both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area between the first regulated voltage range and the second regulated voltage range [e.g. Fig. 3, element 72; paragraph 0027, “Accordingly, in the hysterisis section 72, either of the input voltages 18 and 19 may be used as the gate drive signal 22 depending on direction (downward or upward) that the processor current draw is changing”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”}.
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage includes: operating both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area between the first regulated voltage range and the second regulated voltage range as taught by Shaver to reduce power consumption.
Claims 5 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over US Doc Id. US20180275704A1 (Hereinafter Li) in view of US Doc Id. US20080209236A1 (Hereinafter Shaver) and US Doc Id. US20230288949A1 (Hereinafter Bhuiyan).
Regarding claim 5, Li fails to disclose the multiple input linear voltage regulator of claim 1, wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on detecting a spike in power demand.
Bhuiyan teaches a multiple input linear voltage regulator wherein the control circuit [e.g. Fig. 2, element 235] is configured to: operate both the first regulating transistor [e.g. Fig. 2, element 244] and the second regulating transistor [e.g. Fig. 2, element 246] based on detecting a spike in power demand [e.g. Fig. 5, element 582; paragraph 0012, “The current sharing ratio, which refers to the ratio of the load current provided by the different supply voltages once the current sharing point is reached, is also programmable and can be a constant value or variable as the load current increases”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include the multiple input linear voltage regulator, wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on detecting a spike in power demand as taught by Bhuiyan to improve system performance.
Regarding claim 20, Li discloses the method of claim 17, wherein selectively driving, by the control circuit, the first regulating transistor and the second regulating transistor of the multiple input linear voltage regulator based on the target output voltage [e.g. paragraph 0018, “Based on the first monitor signal, the second monitor signal, and the enable signal EN, the dual input power regulator 210 determines the input priority of the first input terminal IN 1 and the second input terminal IN 2”; paragraph 0021, “if the output voltage VOUT on the output terminal OUT is out of the normal range, then the power good signal PG is pulled low”].
Li fails to disclose operating both the first regulating transistor and the second regulating transistor based on detecting a spike in power demand
Bhuiyan teaches operating both the first regulating transistor [e.g. Fig. 2, element 244] and the second regulating transistor [e.g. Fig. 2, element 246] based on detecting a spike in power demand [e.g. Fig. 5, element 582; paragraph 0012, “The current sharing ratio, which refers to the ratio of the load current provided by the different supply voltages once the current sharing point is reached, is also programmable and can be a constant value or variable as the load current increases”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator operating both the first regulating transistor and the second regulating transistor based on detecting a spike in power demand as taught by Bhuiyan to improve system performance.
Claims 8-16 are rejected under 35 U.S.C. 103 as being unpatentable over US Doc Id. US20180275704A1 (Hereinafter Li) in view of US Doc Id. US20080209236A1 (Hereinafter Shaver) and US Doc Id. US9081577B2 (Hereinafter Conrad).
Regarding claim 8, Li fails to disclose wherein the multiple input linear voltage regulator is located on a die.
Conrad teaches wherein the multiple input linear voltage regulator is located on a die [e.g. paragraph 0014, “the retention voltage may be determined from information stored, e.g., in fuses or other non-volatile storage of the processor as written or fused during manufacture of the semiconductor die”; Fig. 5, VR’s 512 as a part of processor 500].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a microprocessor wherein the multiple input linear voltage regulator is located on a die as taught by Conrad to reduce power consumption.
Regarding claim 9, Li discloses a processor [e.g. Fig. 2, element MCU]; and a multiple input linear voltage regulator [e.g. Figs. 2-5, element 210] comprising: an output port [e.g. Figs. 3 & 5, element OUT] configured to supply an output voltage to at least one of the plurality of processor cores [e.g. Fig. 2, MCU]; a first regulating transistor [e.g. Fig. 5, element 512] operable to receive a first input voltage from a first supply [e.g. Fig. 5, element In1] and provide a first regulated voltage range to the output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”]; a second regulating transistor [e.g. Fig. 5, element 522] operable to receive a second input voltage from a second supply [e.g. Fig. 5, element In2] and provide a second regulated voltage range to the output port [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”; paragraph 0036, “The preset monitor thresholds TH 1 and TH 2 can be the same (e.g., both equal to 1.2V) or they can be different. Furthermore, the resistance ratios of the voltage dividers 411 and 421 can be the same or different (e.g., 1 : 4 and 1 : 3 , respectively). These values are examples only; the invention is not so limited”], wherein the first input voltage is different from the second input voltage [e.g. paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V)”].
Li fails to disclose a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage
Shaver teaches a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage [e.g. paragraph 0011, “The gate drive selector 20 provides a gate drive signal 22 (e.g., a voltage) to the controller 25. The controller 25 uses the gate drive signal 22 to turn on each of the power transistors Q1 and Q2 in an alternating fashion”; paragraph 0013, “the average current output signal 32 comprises a voltage level which is proportional to the average current draw of the processor over a period of time (e.g., 1 millisecond). The average current output signal 32 from the controller 25 is provided to the gate drive selector 20 of the voltage regulator 12. The gate drive selector 20 selects one of the input voltages 18 and 19 for the gate drive signal 22 based on the voltage level of the average current output signal from the controller 25”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein a control circuit operable to selectively drive the first regulating transistor and the second regulating transistor based on at least a target output voltage as taught by Shaver to reduce power consumption.
Li fails to disclose a plurality of processor cores.
Conrad teaches a processor [e.g. Fig. 5, element 500] with a plurality of processor cores [e.g. Fig. 5, element 510].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a microprocessor with a plurality of processor cores as taught by Conrad to reduce power consumption.
Regarding claim 10, Li discloses the processor of claim 9 [e.g. Fig. 2, element MCU], wherein the multiple input linear voltage regulator [e.g. Figs. 2-5, element 210]
Li fails to disclose a plurality of multiple input linear voltage regulators, and wherein each of the plurality of multiple input linear voltage regulators provides an output voltage to a respective one of the plurality of processor cores.
Conrad teaches a plurality of multiple input linear voltage regulators [e.g. Fig. 5, elements 512], and wherein each of the plurality of multiple input linear voltage regulators provides an output voltage [e.g. paragraph 0028, “In addition, each core may be independently controlled to operate at a selected voltage and/or frequency, as discussed above. To this end, each core may be associated with a corresponding voltage regulator 512 a - 512 n”] to a respective one of the plurality of processor cores [e.g Fig. 5, elements 510].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a microprocessor a plurality of multiple input linear voltage regulators, and wherein each of the plurality of multiple input linear voltage regulators provides an output voltage to a respective one of the plurality of processor cores as taught by Conrad to reduce power consumption.
Regarding claim 11, Li fails to disclose the processor of claim 10, wherein the control circuit receives a signal indicative of the target output voltage from a power management controller of one or more of the plurality of processor cores.
Shaver teaches wherein the control circuit [e.g. Fig. 1, element 20] receives a signal indicative of the target output voltage [e.g. Fig, 1, element 32] from a power management controller [e.g. Fig. 1, element 25] of the one or more processor components [e.g. Fig. 1, element 30].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein the control circuit receives a signal indicative of the target output voltage from a power management controller of the one or more processor components as taught by Shaver to reduce power consumption.
Regarding claim 12, Li fails to disclose wherein the control circuit is configured to turn a core off via a respective multiple input linear voltage regulator.
Conrad teaches wherein the control circuit is configured to turn a core off via a respective multiple input linear voltage regulator [e.g. paragraph 0029, “the voltage control logic 556 may generate a plurality of control signals to cause the voltage regulators to control the voltage provided to the corresponding cores, e.g., reduce voltage supplied to one of the cores to a retention voltage that is less than an idle state voltage of a requested idle state, which can result in reduced power loss due to leakage effects while stored data is retained in registers of the idled core”].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a microprocessor wherein the control circuit is configured to turn a core off via a respective multiple input linear voltage regulator as taught by Conrad to reduce power loss.
Regarding claim 13, Li discloses the processor of claim 9, wherein the control circuit [e.g. Fig. 3, element 310] is configured to: operate only the first regulating transistor based on the target output voltage falling within the first regulated voltage range corresponding to the first regulating transistor [e.g. Table 1, second row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage]; and operate only the second regulating transistor based on the target output voltage falling within the second regulated voltage range corresponding to the second regulating transistor [e.g. Table 1, third row; paragraph 0018, “Specifically, the dual input power regulator 210 monitors whether a first input terminal IN 1 (e.g., 6V) has a power supply and whether a second input terminal IN 2 (e.g., 4.5V) has a power supply”; Differing inputs means differing output voltage].
Regarding claim 14, Li fails to disclose the processor of claim 13, wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range.
Shaker teaches wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range [e.g. paragraph 0027, “Accordingly, in the hysterisis section 72, either of the input voltages 18 and 19 may be used as the gate drive signal 22 depending on direction (downward or upward) that the processor current draw is changing”}
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a multi-input voltage regulator wherein the control circuit is configured to: operate both the first regulating transistor and the second regulating transistor based on the target output voltage falling within a boundary area of the first regulated voltage range and the second regulated voltage range as taught by Shaver to reduce power consumption.
Regarding claim 15, Li discloses the processor of claim 9, wherein the multiple input linear voltage regulator is located in one of a substrate and an interposer of the processor [e.g. paragraph 0003, “the MCU has multiple input/output interfaces (I/O) and proper firmware to control those discrete components. Thus, this is a high cost, high power consumption, high complexity solution and requires large Printed Circuit Board (PCB) space”].
Regarding claim 16, Li fails to disclose wherein the multiple input linear voltage regulator is located on a die of the processor.
Conrad teaches wherein the multiple input linear voltage regulator is located on a die of the processor [e.g. paragraph 0014, “the retention voltage may be determined from information stored, e.g., in fuses or other non-volatile storage of the processor as written or fused during manufacture of the semiconductor die”; Fig. 5, VR’s 512 as a part of processor 500].
It would be obvious to someone having ordinary skill in the art, before the effective filing date, to modify Li to further include a microprocessor wherein the multiple input linear voltage regulator is located on a die of the processor as taught by Conrad to reduce power consumption.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
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