Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action.
Applicant’s election without traverse of Group I (claims 1-13) in response/amendment is acknowledged. The requirement is still deemed proper and is therefore made FINAL.
Information Disclosure Statement
The prior art documents submitted by Applicant(s) in the information Disclosure Statement(s) have all been considered and made of record (note the attached copy of form(s) PTO-1449).
Claim Objection
Claim 6 is objected for reciting approximately 90 degrees, as such limitation is indefinite and may connected by citing i.e., substantially 90 degrees .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-4, 6-10 and 12-13 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by “Brouckaert”; Joost et al. US 20170075063 A1.
Regarding claim 1, Brouckaert teaches a polarisation converter for a photonic integrated circuit (see at least abstract), comprising:
PNG
media_image1.png
367
509
media_image1.png
Greyscale
PNG
media_image2.png
282
549
media_image2.png
Greyscale
PNG
media_image3.png
414
566
media_image3.png
Greyscale
a first semiconductor layer (clearly shown in at least figs. 1, 3-5.and 7, i.e., top semiconductor layer); a second semiconductor layer comprising, when viewed in a cross-sectional plane perpendicular a light propagation axis, a first portion thicker than a second portion of the second semiconductor layer (clearly shown in at least figs. 3-5.and 7, i.e., the middle semiconductor layer); and a third semiconductor layer , the second semiconductor layer between, and in contact with, the first semiconductor layer and the third semiconductor layer (clearly shown in at least figs. 1, 3-5.and 7, i.e., bottom semiconductor layer).
2. (Original) The polarisation converter of claim 1, comprising a region between the first semiconductor layer and the third semiconductor layer, the second semiconductor layer absent from the region (shown in at least figs. 3-5.and 7, the middle semiconductor layer have portion absent after its tapered portion there between).
3. (Original) The polarisation converter of claim 1, wherein the second semiconductor layer contacts a first surface area of the first semiconductor layer and a second surface area of the third semiconductor layer, the first surface area larger than the second surface area, or the second surface area larger than the first surface area (see at least figs. 3-5.and 7).
4. (Original) The polarisation converter of claim 1, the second semiconductor layer comprising: a first surface not in contact with the first semiconductor layer and the third semiconductor layer; a second surface not in contact with the first semiconductor layer and the third semiconductor layer, the second surface non-parallel the first surface; and a third surface in contact with the first semiconductor layer (see at least figs. 3-5.and 7 and summary on the thickness where the tapering of the layer occurs).
6. (Original) The polarisation converter of claim 4, the second surface angled relative to the third surface by an internal angle of approximately 90 degrees .
7. (Original) The polarisation converter of claim 4, the second semiconductor layer comprising a fourth surface in contact with the third semiconductor layer, the fourth surface substantially parallel the third surface.
8. (Original) The polarisation converter of claim 4, wherein the second semiconductor layer comprises a crystalline material and the first surface of the second semiconductor layer is angled in correspondence with a plane of the crystalline material, for example the { III} plane of the crystalline material (see at least figs. 3-5.and 7 the middle layer has a width that since that forms 90 degree angle with respect to the to/bottom/3rd-layer). .
9. (Original) The polarisation converter of claim 4, wherein a first surface of the first semiconductor layer and a first side of the third semiconductor layer are substantially coplanar in a first plane, the first surface of the second semiconductor layer at least partly recessed from the first plane (clearly shown in at least figs. 1, 3-5. And 7).
10. (Original) The polarisation converter of claim 4, wherein a second surface of the first semiconductor layer, the second surface of the second semiconductor layer, and a second surface of the third semiconductor layer are substantially coplanar in a second plane (clearly shown in at least figs. 1, 3-5. And 7).
12. (Original) The polarisation converter of claim 1, wherein the second semiconductor layer is a core layer of a waveguide, the core layer having a different refractive index from each of the first semiconductor layer and the second semiconductor layer (see at least figs. 1, 3-5. and 7 and abstract/summary).
.
Regarding claim 13, Brouckaert teaches a photonic integrated circuit (see background/summary, col. 4);comprising:
PNG
media_image1.png
367
509
media_image1.png
Greyscale
PNG
media_image2.png
282
549
media_image2.png
Greyscale
PNG
media_image3.png
414
566
media_image3.png
Greyscale
a first semiconductor layer (clearly shown in at least figs. 1, 3-5.and 7, i.e., top semiconductor layer); a second semiconductor layer comprising, when viewed in a cross-sectional plane perpendicular a light propagation axis, a first portion thicker than a second portion of the second semiconductor layer (clearly shown in at least figs. 3-5.and 7, i.e., the middle semiconductor layer); and a third semiconductor layer , the second semiconductor layer between, and in contact with, the first semiconductor layer and the third semiconductor layer (clearly shown in at least figs. 1, 3-5.and 7, i.e., bottom semiconductor layer).
Allowable Subject Matter
Claims 5 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 5 and 11 are allowable because the prior art of record, taken alone or in combination, fails to disclose or render obvious its respective limitations in combination with the rest of the limitations of the base claim.
Citation of Relevant Prior Art
Prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. In accordance with MPEP 707.05 the following references are pertinent in rejection of this application since they provide substantially the same information disclosure as this patent does. These references are:
US 20170075063 A1
US 20120163750 A1
US 20120076465 A1
US 9170373 B2
US 20170199330 A1
US 20190064439 A1
US 20130322813 A1
US 5790583 A
US 5878070 A
US 20190011800 A1
US 20220120966 A1
US 20230040355 A1
US 9766404 B1
US 5065390 A
US 20140126855 A1
US 20180120504 A1
US 20170104109 A1
US 11409038 B1
US 20190384135 A1
US 6166372 A
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAVEH KIANNI whose telephone number is (571)272-2417. The examiner can normally be reached on 9-19.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas Hollweg can be reached on571-270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KAVEH C KIANNI/ Primary Examiner, Art Unit 2874
Prosecution Insights