DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hiraoka et al. (US 2019/0295774).
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Regarding claim 1, Hiraoka et al. disclose in fig. 1-2, a thin film capacitor (100) comprising:
a first electrode layer (10);
a second electrode layer (50); and
a dielectric layer (20) provided between the first electrode layer (10) and the second electrode layer (50),
wherein
the thin film capacitor (100) comprises an intermediate layer (40) between the dielectric layer (20) and the second electrode layer (50),
the intermediate layer (40) comprises at least one stacking unit (40m) including a first intermediate layer (40a) and a second intermediate layer (40b) stacked in (direct) contact with the first intermediate layer (40a),
the first intermediate layer (40a) of the at least one stacking unit (40m) closest to the dielectric layer (20) is stacked in contact (indirect contact) with the dielectric layer (20),
the first intermediate layer (40a) comprises a first metal (M1) as a main component [0039], and
the second intermediate layer (40b) comprises a second metal (M2), different from the first metal, as a main component [0039].
Regarding claim 2, Hiraoka et al. disclose the first intermediate layer (40a) has a thickness of 8 to 80 nm [0043], and
the second intermediate layer has a thickness of 8 to 80 nm [0043].
Regarding claim 3, Hiraoka et al. disclose the first metal (M1) comprises at least one selected from a group consisting of Cu, Cr, Au, Ru, Rh, Ir, Mo, Ti, and W [0040], and
the second metal (M2) comprises at least one selected from a group consisting of Ni, Pd, Pt, Au, Ru, Rh, and Ir [0041].
Regarding claim 4, Hiraoka et al. disclose the at least one stacking unit comprises stacking units repeatedly stacked in a range of 2 to 10 in the intermediate layer (40m (4) – Fig. 2).
Regarding claim 5, Hiraoka et al. disclose a ratio (t2/t1) of a thickness (t2) of the second intermediate layer to a thickness (t1) of the first intermediate layer is 0.2 to 1.0 [0077].
Regarding claim 6, Hiraoka et al. disclose a thin film capacitor (100) comprising:
a first electrode layer (10);
a second electrode layer (50); and
a dielectric layer (20) provided between the first electrode layer (10) and the second electrode layer (50),
wherein
the thin film capacitor (100) comprises an intermediate layer (40) between the dielectric layer (20) and the second electrode layer (50),
the intermediate layer (40) comprises at least one stacking unit (40m) including a first intermediate layer (40a) and a second intermediate layer (40b) stacked in (direct) contact with the first intermediate layer (40a),
the first intermediate layer (40a) of the at least one stacking unit (40m) closest to the dielectric layer (20) is stacked in (indirect) contact with the dielectric layer (20),
the first intermediate layer (40a) comprises a second metal (M2) as a main
component,
the second intermediate layer (40b) comprises a first metal (M1), different from the second metal [0039], as a main component,
the first intermediate layer (40a) has a thickness of 8 to 80 nm [0043], and
the second intermediate layer has a thickness of 8 to 80 nm [0043].
Regarding claim 7, Hiraoka et al. disclose the at least one stacking unit (40m) comprises stacking units (40m) repeatedly stacked in a range of 4 to 10 in the intermediate layer (4) – Fig. 2.
Regarding claim 8, Hiraoka et al. disclose a substrate comprising the thin film capacitor according to claim 1 [0034].
Regarding claim 9, Hiraoka et al. disclose an electronic device (not illustrated – but inherent to the capacitor) comprising the thin film capacitor according to claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 5,005,102 A – Multilayered electrodes for a capacitor
US 2020/0243266 – MIM thin film capacitor
US 2019/0287726 – thin film capacitor
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/ERIC W THOMAS/Primary Examiner, Art Unit 2847
ERIC THOMAS
Primary Examiner
Art Unit 2847
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