DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/04/2024, 01/28/2025 and 06/26/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 0061 recites “V2 represents a voltage of an inverting input end of the error amplifier” appears twice in succession therefore one should be deleted.
Paragraph 0066 recites language regarding a decade and decades which is unclear and specifically recites “FIG. 5 further shows that, as a frequency increases, a decade of the amplitude of the signal amplified by the error amplifier gradually increases. For example, when the frequency changes from a low frequency f1 to a high frequency f2, the amplitude of the signal decades by 20 dB” which seem inconsistent with the drawing. This should be changed to “FIG. 5 further shows that, as frequency increases, the amplitude of the signal amplified by the error amplifier decreases. For example, when the frequency changes from a low frequency f1 to a high frequency f2, the amplitude decreases by 20 dB per decade.”
Paragraph 0070 highlights details regarding Figure 1 and highlights a transistor “Mpass” being a “PMOS Transistor” however Figure 1 does not contain an element Mpass. This should be changed to Mp instead as this is the component meant to be highlighted in this passage.
Appropriate correction is required.
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Deng (CN 105549672 A – Translation Attached) in view of Liu (CN 104820459 A – Translation Attached).
Regarding claim 1, Deng teaches a low-dropout regulator (Figure 4), comprising: an error amplifier (Figure 4 Component MC1) configured to generate a first feedback voltage (Figure 4 Component VD) based on a reference voltage (Figure 4 Component Vset) and an output voltage for a load (Figure 4 Component Vo), wherein the error amplifier is a common-gate amplifier (Figure 4 Component MC1 is a common-gate amplifier); a power supply end (Figure 4 Component Vin); a first power transistor (Figure 4 Component MP1), wherein the first power transistor is a first P-channel metal-oxide-semiconductor (PMOS) transistor (Figure 4 Component MP1 is a PMOS transistor) comprising: a first source coupled to the power supply end (Figure 4 Component MP1 source is coupled to Component Vin); a first drain configured to provide an output current for the load (Figure 4 Component MP1 has a drain terminal providing an output current); and a first gate (Figure 4 Component MP1 gate terminal) configured to receive a second feedback voltage (Figure 4 Component MP1 gate terminal receives the second feedback voltage outputted by Component MP2); and a loop gain amplifier (Figure 4 Component MP2) configured to generate the second feedback voltage based on the first feedback voltage (Figure 4 Component MP2 generates a second feedback voltage based on the gate voltage VD being applied which is the first feedback voltage), wherein the loop gain amplifier is a common-source amplifier (Figure 4 Component MP2 is a common-source amplifier).
Deng does not teach wherein the first transistor is a NMOS transistor having a first drain coupled to the power supply end, a first source configured to provide an output current.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Regarding claim 2, Deng and Liu teach all the limitations of claim 1. Deng further teaches a first bias voltage source configured to provide the reference voltage (Figure 4 Component Vset is generated by the voltage source there), wherein the error amplifier is a P-channel metal-oxide-semiconductor (PMOS) transistor (Figure 4 Component MC1) comprising: a second source coupled to the first drain and the load at one point (Figure 4 Component MC1 has a source terminal coupled to the load and the drain terminal of Component MP1); a second gate coupled to the first bias voltage source (Figure 4 Component MP1 has a gate terminal coupled to Component Vset); and a second drain configured to output the first feedback voltage (Figure 4 Component MC1 has a drain terminal that outputs Component VD).
Deng does not teach the first transistor being an NMOS transistor have a first source terminal coupled to the load.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Regarding claim 3, Deng and Liu teach all the limitations of claim 2. Deng further teaches a ground (Figure 4 Component Ground Terminals), wherein the loop gain amplifier is a second PMOS transistor (Figure 4 Component MP2) comprising: a third gate coupled to the second drain (Figure 4 Component MP2 has a gate terminal coupled to Component MC1 Drain Terminal); a third drain coupled to the ground (Figure 4 Component MP2 has a Drain Terminal coupled to ground); and a third source configured to output the second feedback voltage (Figure 4 Component MP2 Source Terminal outputs the second feedback voltage).
Deng does not teach wherein the loop gain amplifier is an NMOS transistor having a third source coupled to ground and a third drain configured to output the second feedback voltage.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Regarding claim 4, Deng and Liu teach all the limitations of claim 3. Deng does not teach wherein the third drain is coupled to the first gate.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Regarding claim 5, Deng and Liu teach all the limitations of claim 3. Deng further teaches a first bias current source comprising: a first end coupled to the second drain; and a second end coupled to the ground (Figure 3 Component IBIAS2 has a first end coupled to the drain terminal of Component MC1 and a second end coupled to the ground terminal).
Regarding claim 6, Deng and Liu teach all the limitations of claim 5. Deng further teaches a second bias current source comprising: a third end coupled to the power supply end; and a fourth end coupled to the third source and the first gate at one point (Figure 3 Component IBIAS1 has a third end coupled to Component Vin and fourth end coupled to the first gate of Component MP1 and the source terminal of Component MP2).
Deng does not teach wherein the loop gain amplifier is an NMOS transistor having third drain configured to output the second feedback voltage to the gate of the first power transistor.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Deng (CN 105549672 A – Translation Attached) in view of Liu (CN 104820459 A – Translation Attached) and in further view of Motz (US 9448574 B2).
Regarding claim 7, Deng and Liu teach all the limitations of claim 1. Deng does not teach a second power transistor, wherein the second power transistor is a third NMOS transistor, and wherein the first drain is coupled to the power supply end through the third NMOS transistor.
Motz teaches a low drop-out regulator (Figure 4) including a pass first transistor that is an NMOS transistor (Figure 4 Component 204) have a first drain terminal coupled to a supply voltage (Figure 4 Component 204 is connected to Component 208 through Component 202) and a first source terminal coupled to an output voltage (Figure 4 Component 204 has a source terminal coupled to Component 210) and a second power transistor that is a NMOS transistor (Figure 4 Component 202) wherein the first drain is coupled to the power supply end through the second power transistor (Figure 4 Component 204 is coupled to Component 208 through Component 202), wherein the second power transistor includes a second source coupled to the first drain (Figure 4 Component 202 has a source terminal coupled to the drain terminal of Component 204) and a second drain coupled to the power supply node (Figure 4 Component 202 has a drain terminal coupled to Component 208).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate a cascaded serially connected NMOS transistor above the pass transistor as taught by Motz. The advantage of this design is that it provides supply-noise isolation and increases the effective output resistance of the pass device stack which would in turn improve high frequency PSRR.
Regarding claim 8, Deng and Liu teach all the limitations of claim 7. Deng further teaches wherein the third NMOS transistor comprises: a second source coupled to the first drain; and a second drain coupled to the power supply end.
Motz teaches a low drop-out regulator (Figure 4) including a pass first transistor that is an NMOS transistor (Figure 4 Component 204) have a first drain terminal coupled to a supply voltage (Figure 4 Component 204 is connected to Component 208 through Component 202) and a first source terminal coupled to an output voltage (Figure 4 Component 204 has a source terminal coupled to Component 210) and a second power transistor that is a NMOS transistor (Figure 4 Component 202) wherein the first drain is coupled to the power supply end through the second power transistor (Figure 4 Component 204 is coupled to Component 208 through Component 202), wherein the second power transistor includes a second source coupled to the first drain (Figure 4 Component 202 has a source terminal coupled to the drain terminal of Component 204) and a second drain coupled to the power supply node (Figure 4 Component 202 has a drain terminal coupled to Component 208).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate a cascaded serially connected NMOS transistor above the pass transistor as taught by Motz. The advantage of this design is that it provides supply-noise isolation and increases the effective output resistance of the pass device stack which would in turn improve high frequency PSRR.
Claims 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Deng (CN 105549672 A – Translation Attached) in view of Liu (CN 104820459 A – Translation Attached) and in further view of Jiang (US 2022/0206520 A1).
Regarding claim 11, Deng teaches a chip (Figure 4 is a regulator that is on a chip; Paragraph 5 implies a chip is present and that the LDO is a system on chip design) comprising: a supply voltage input end configured to provide a supply voltage (Figure 4 Component Vin); and a low-dropout regulator (Figure 4) configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load (Figure 4 Component Vo), comprising: an error amplifier (Figure 4 Component MC1) configured to generate a first feedback voltage (Figure 4 Component VD) based on a reference voltage (Figure 4 Component Vset) and the output voltage (Figure 4 Component Vo), wherein the error amplifier is a common-gate amplifier (Figure 4 Component MC1 is a common-gate amplifier); a power supply end (Figure 4 Component Vin); a first power transistor (Figure 4 Component MP1), wherein the first power transistor is a first P-channel metal-oxide-semiconductor (PMOS) transistor (Figure 4 Component MP1 is a PMOS transistor) comprising: a first source coupled to the power supply end (Figure 4 Component MP1 source is coupled to Component Vin); a first drain configured to provide an output current for the load (Figure 4 Component MP1 has a drain terminal providing an output current); and a first gate (Figure 4 Component MP1 gate terminal) configured to receive a second feedback voltage (Figure 4 Component MP1 gate terminal receives the second feedback voltage outputted by Component MP2); and a loop gain amplifier (Figure 4 Component MP2) configured to generate the second feedback voltage based on the first feedback voltage (Figure 4 Component MP2 generates a second feedback voltage based on the gate voltage VD being applied which is the first feedback voltage), wherein the loop gain amplifier is a common-source amplifier (Figure 4 Component MP2 is a common-source amplifier).
Deng does not teach an analog circuit wherein the low-dropout regulator configured to supply power to the analog circuit; and wherein the first transistor is a NMOS transistor having a first drain coupled to the power supply end, a first source configured to provide an output current.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 12, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the chip is a radio frequency transceiver.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the chip is a radio frequency transceiver (Paragraph 0068 and Paragraph 0025).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 13, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the chip is a Wi-Fi chip.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the chip is a Wi-Fi chip (Paragraph 0004).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 14, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the analog circuit is a low-noise amplifier.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the analog circuit is a low-noise amplifier (Paragraph 0025).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 15, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the analog circuit is a voltage-controlled oscillator.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the analog circuit is a voltage-controlled oscillator (Paragraph 0067).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 16, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the analog circuit is a phase-locked loop.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the analog circuit is a phase-locked loop (Paragraph 0067).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 17, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach wherein the analog circuit is a frequency mixer.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), wherein the analog circuit is a frequency mixer (Paragraph 0025).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 18, Deng, Liu and Jiang teach all the limitations of claim 11. Deng does not teach a digital circuit coupled to the supply voltage input end.
Jiang teaches a chip (Figures 1 and 6; Paragraph 0023 “the power management circuit 100 may be an integrated circuit (such as a power management integrated circuit (PMIC)) or integrated with another circuit such as a system-on-a-chip”), comprising: an analog circuit (Figure 1 Components 114; Paragraph 0025 “The external outputs 114 of linear regulators 104e, 104f, 104g may be coupled to analog circuitry”); and a low-dropout regulator configured to perform low-dropout regulation on the supply voltage to generate an output voltage for a load, configured to supply power to the analog circuit based on the output voltage (Figure 1 Components 104), and a digital circuit coupled to the supply voltage input end (Figure 6; Paragraph 0025 “the external outputs 114 of linear regulators 104a, 104b may be coupled to digital circuitry such as a processor (e.g., a digital signal processor), modem, memory device”; ‘coupled’ is a broad term that can be broadly interpreted as connected in any manner or through many components as well therefore the connection through the LDO is valid too).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng as modified in view of Liu to incorporate having an integrated chip environment with an analog circuitry output as taught by Jiang. The design would allow the regulator topology to be used in analog/RF domains while meeting the low-noise and isolation requirements for analog subsystems.
Regarding claim 19, Deng, Liu and Jiang teach all the limitations of claim 11. Deng further teaches wherein the low-dropout regulator further comprises a first bias voltage source configured to provide the reference voltage (Figure 4 Component Vset is generated by the voltage source there), wherein the error amplifier is a P-channel metal-oxide-semiconductor (PMOS) transistor (Figure 4 Component MC1) comprising: a second source coupled to the first drain and the load at one point (Figure 4 Component MC1 has a source terminal coupled to the load and the drain terminal of Component MP1); a second gate coupled to the first bias voltage source (Figure 4 Component MP1 has a gate terminal coupled to Component Vset); and a second drain configured to output the first feedback voltage (Figure 4 Component MC1 has a drain terminal that outputs Component VD).
Deng does not teach the first transistor being an NMOS transistor have a first source terminal coupled to the load.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Regarding claim 20, Deng, Liu and Jiang teach all the limitations of claim 19. Deng further teaches wherein the low-dropout regulator further comprises a ground (Figure 4 Component Ground Terminals), wherein the loop gain amplifier is a second PMOS transistor (Figure 4 Component MP2) comprising: a third gate coupled to the second drain (Figure 4 Component MP2 has a gate terminal coupled to Component MC1 Drain Terminal); a third drain coupled to the ground (Figure 4 Component MP2 has a Drain Terminal coupled to ground); and a third source configured to output the second feedback voltage (Figure 4 Component MP2 Source Terminal outputs the second feedback voltage).
Deng does not teach wherein the loop gain amplifier is an NMOS transistor having a third source coupled to ground and a third drain configured to output the second feedback voltage.
Liu teaches a low-dropout regulator (Figure 1) including a power supply end (Figure 1 Component VDD); a first pass transistor (Figure 1 Component MN0), wherein the first pass transistor is a first N-channel metal-oxide-semiconductor (NMOS) transistor (Figure 1 Component MN0 is a NMOS transistor) having a first drain coupled to the power supply end (Figure 1 Component MN0 has a drain terminal coupled to Component VDD), a first source configured to provide an output current for the load (Figure 1 Component MN0 has a source terminal outputting a current for a load receiving the output voltage Vo), and a first gate configured to receive a feedback control voltage (Figure 1 Component MN0 has a gate terminal receiving a feedback voltage from Component MN2); and a loop gain amplifier configured to generate the feedback control voltage (Figure 1 Component MN2 generates a feedback voltage), wherein the loop gain amplifier is implemented as a common source NMOS transistor (Figure 1 Component MN2 is a NMOS transistor) having a source coupled to ground (Figure 1 Component MN2 has a source terminal coupled to ground) and a drain providing the feedback control voltage to the first gate of the first pass transistor (Figure 1 Component MN0 receives the feedback control voltage from the drain of Component MN2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Deng to incorporate implementing the pass transistor and the common-source loop gain amplifier transistor with NMOS devices instead of PMOS devices as taught by Liu. The advantage of this design is that NMOS transistor provide higher carrier mobility and correspondingly higher transconductance and gate per unit bias current and therefore provide higher drive capabilities and faster response.
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests a low-pass filter separately coupled to the power supply end and a second gate of the third NMOS transistor. Claim 10 depends upon claim 9.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached at 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Shahzeb K Ahmad/Examiner, Art Unit 2838