DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to communication from applicant received on May 1, 2026.
Response to Amendment
Applicant's submission filed on May 1, 2026 has been entered. Claims 1-20 are pending in the current application. Claims 1-20 are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 recites “filtering requests to a backend for accesses that are near each other in both address space and period or access series order”. The specification does not adequately disclose how requests are filtered for accesses that are near each other in both address space and period or access series order. That is, one of ordinary skilled in the art would not be able to ascertain how the requests are filtered for accesses that are near each other in both address space and period or access series order based on applicant’s disclosure. Paragraphs [0022] and [0054] of applicant’s original specification merely recite the limitations of recites “filtering requests to a backend for accesses that are near each other in both address space and period or access series order” without reciting how the limitation is being performed, which is insufficient disclosure for the claimed limitation. Claim 15 is rejected for the same reasons as claim 1. All dependent claims are rejected for having the same deficiency as the claim(s) that they depend on.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 recites “filtering requests to a backend for accesses that are near each other in both address space and period or access series order”. It is unclear as to exactly how requests are filtered for accesses that are near each other in both address space and period or access series order. Claim 15 is rejected for the same reasons as claim 1. All dependent claims are rejected for having the same deficiency as the claim(s) that they depend on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5 and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Vishne et al. (Hereinafter Vishne, U.S. Publication No. 2023/0289093) in view of Flett et al. (Hereinafter Flett, U.S. Publication No. 2025/0110759).
Regarding claim 1, Vishne teaches:
A method for maintaining the integrity of a memory component, the method comprising:
receiving, by a memory controller, a plurality of memory requests including at least one write request (See [0034] “The controller 206 includes a host interface module (HIM) 210 configured to receive and send data between the host device 202 and the controller 206. The controller 206 further includes a command executer 212 coupled to the HIM 210. The command executer 212 may be configured to execute read and write commands received from the host device 202.”);
allocating a data block into a buffer cache to cache the at least one write request (See [0031] “the controller 108 may use volatile memory 112 as a cache. For instance, the controller 108 may store cached information in volatile memory 112 until cached information is written to non-volatile memory 110.”);
detecting whether sufficient time has elapsed beyond a predetermined threshold (See Figure 8, step 802 “Receive command to send to memory device at predetermined timer setting” See [0007] “set a value for a timer that predicts availability of the memory device; receive a first command; send the command for processing to the memory device; check status of the memory device; determine the memory device is available;”),
in response to sufficient time having elapsed beyond the predetermined threshold,
flagging a backend memory as being available (See Figure 8, steps 806, in which the memory device is determined to not be busy (i.e. No) and thus determined/flagged to be “available”. See [0044] “Once the memory device is not busy at 806, the command is processed at 810” See [0007] “set a value for a timer that predicts availability of the memory device; receive a first command; send the command for processing to the memory device; check status of the memory device; determine the memory device is available); and
in response to the flagging, fetching the at least one write request to write data to the memory component (See [0044] “The command is to be sent to the memory device through the FIM over the data bus at a predetermined time set by a timer.” See [0044] “Once the memory device is not busy at 806, the command is processed at 810”), wherein the buffer cache is configured to reduce the number of backend reads and writes (See [0031] “the controller 108 may use volatile memory 112 as a cache. For instance, the controller 108 may store cached information in volatile memory 112 until cached information is written to non-volatile memory 110.” Cache storage is used to reduce the number of reads and writes to the main storage device.).
Vishne does not explicitly disclose what Flett teaches:
filtering requests to a backend for accesses that are near each other in both address space and period or access series order (See [0040] “At step 720, the command data is preprocessed to clean the command data and produce an input dataset 722. Similar to in training, the preprocessing may perform filtering to filter commands on a predetermined list of “unimportant” commands, filter sequential commands that occur more than a threshold number of times, filter commands that occur less frequently than a threshold, and/or filter other commands that are not useful in inference. Again, empirically selected criteria and thresholds may be used in such filtering.”);
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the command processing method of Vishne with the command filtering method of Flett to reduce the amount of repeated/unnecessary commands (See [0031] and claim 8 of Flett).
Regarding claim 2, Vishne teaches:
The method of claim 1, further including determining whether unrelated requests have elapsed (See [0002] “The data storage device uses a controller having a flash interface module (FIM) to write the data to the memory device of the data storage device and deliver an indication to the host device that the write command was successful. To retrieve data, the host device sends a read command to the data storage device to read data from the memory device. The data storage device executes the read command and delivers an indication to the host device that the read was successful.” The system may determine whether previous/unrelated requests have completed/elapsed.).
Regarding claim 3, Vishne teaches:
The method of claim 1, further including determining whether sufficient time has elapsed beyond the predetermined threshold based on one or more measurements of past requests (See [0050] “adaptively adjusting timing of sending the commands based upon determining whether the memory means is busy. The adaptively adjusting timing comprises increasing an amount of time between sending commands upon determining that the memory means is busy and decreasing the amount of time between sending commands upon determining the memory means is not busy. The decreasing comprises decreasing the amount of time by a value equal to: (current amount of time between sending commands—mean of previous amounts of time between sending commands)/X, where “X” is a taregt for late predictions per every early prediction.” See Figure 8 in view of [0050], in which the predetermined timer is set based previous amounts of time between sending previous commands.”)
Regarding claim 4, Vishne teaches:
The method of claim 3, wherein the one or more measurements include a moving average of a request rate (See [0050] “adaptively adjusting timing of sending the commands based upon determining whether the memory means is busy. The adaptively adjusting timing comprises increasing an amount of time between sending commands upon determining that the memory means is busy and decreasing the amount of time between sending commands upon determining the memory means is not busy. The decreasing comprises decreasing the amount of time by a value equal to: (current amount of time between sending commands—mean of previous amounts of time between sending commands)/X, where “X” is a target for late predictions per every early prediction.” The “mean of previous amounts of time between sending commands” corresponds to the claimed “average request rate”.).
Regarding claim 5, Vishne teaches:
The method of claim 4, wherein the moving average of the request rate is computed within a variable time window (See [0050] “adaptively adjusting timing of sending the commands based upon determining whether the memory means is busy. The adaptively adjusting timing comprises increasing an amount of time between sending commands upon determining that the memory means is busy and decreasing the amount of time between sending commands upon determining the memory means is not busy. The decreasing comprises decreasing the amount of time by a value equal to: (current amount of time between sending commands—mean of previous amounts of time between sending commands)/X, where “X” is a taregt for late predictions per every early prediction.” The timing of sending commands may be adjusted based on a current amount of time between sending commands and a mean of pervious amounts of time between sending commands. These timings are constantly being adjusted/changed, thereby creating a variable time window.).
Claim 15 is rejected for the same reasons as claim 1. Claim 16 is rejected for the same reasons as claim 2. Claim 17 is rejected for the same reasons as claim 3. Claim 18 is rejected for the same reasons as claim 4. Claim 19 is rejected for the same reasons as claim 5.
Claims 6-7 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Vishne in view of Flett in view of Frey (U.S. Patent No. 6,725,392).
Regarding claim 6, Frey teaches:
The method of claim 1, further including reading old data when the backend memory is available (See Col. 24 lines 51-53 “Then this delta is sent to the data IOM and the new data is reconstructed in the cache of the data IOM by XORing the delta with the old data (read by using the old disk address).” See claim 5 of Frey “(a1) issuing a read command to read an old data block corresponding to the new data block if the old data block is not already in a first buffer in the first IOM, the old data block having a first location in a meta-data structure for the distributed file system that contains an old disk address for the old data block;”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the command processing method of Vishne with the RAID management system of Frey to enhance storage capabilities by implementing redundant storage drives for improved performance, data redundancy, and increased capacity.
Regarding claim 7, Frey teaches:
The method of claim 6, further including computing and storing a partial parity in the buffer cache (See Col. 19 lines 21-23 “For partial writes and partial parity updates, a second cache buffer (requiring a new disk address only if it would be required for a full buffer update) must be used.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the command processing method of Vishne with the RAID management system of Frey to avoid read-before-write of data by using partial parity updates, which would prevent data inconsistency and improve performance and scalability (See Col. 19, lines 47-50 of Frey).
Claim 20 is rejected for the same reasons as claim 6.
Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Vishne in view of Flett in view of Li et al. (Hereinafter Li, U.S. Publication No. 2019/0163409).
Regarding claim 8, Li teaches:
The method of claim 1, wherein the memory component is a RAID stripe (See Figures 1A-1E, which depict RAID stripes.).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the command processing method of Vishne with the writing method for a RAID storage system of Li to improve read/write management for RAID system when in a degraded mode, by reducing the number of times of reading/writing the storage disk while ensuring data consistency during a write operation, thereby reducing the response time of the write operation with respect to the disk array group in the degraded mode. Such combination can improve an overall throughput while the disk array group is in the degraded mode (See [0035] of Li).
Regarding claim 9, Li teaches:
The method of claim 8, further including waiting until data or a parity cache entry is to be victimized (See [0007] “The method further comprises: in response to receiving from the disk array a first indication that the to-be-written data has been written into the at least one cache page, marking the at least one cache page as to-be-flushed.”).
Regarding claim 10, Li teaches:
The method of claim 8, further including initiating victimization when the RAID stripe has been written and the backend memory is available (See [0007] “The method further comprises: in response to receiving from the disk array a first indication that the to-be-written data has been written into the at least one cache page, marking the at least one cache page as to-be-flushed. In addition, the method further comprises: sending to the disk array a second indication that the to-be-written data can be flushed to the at least one disk array group, so that the to-be-written data in the at least one cache page marked as to-be-flushed is flushed into the at least one storage block.”).
Regarding claim 11, Li teaches:
The method of claim 8, further including reading an original parity from the backend memory and computing a new stripe parity (See abstract “The method further comprises: determining new parity information associated with the new data based on the old data, the old parity information and the new data.”).
Regarding claim 12, Li teaches:
The method of claim 11, further including writing both the original parity and new data sectors to the backend memory (See abstract “this method further comprises: flushing the new data and the new parity information into the data block and the parity block in the at least one disk array group, respectively.” See [0059] “FIG. 7 illustrates a schematic diagram of a process 700 of the cache component 210 flushing a dirty page according to embodiments of the present disclosure.”).
Claims 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Vishne in view of Flett in view of Li in view of Jones (U.S. Patent No. 5506977)
Regarding claim 13, Jones teaches:
The method of claim 8, further including reading unwritten data sectors from the backend memory and computing a new stripe parity (See abstract “The present invention operates during writes to K blocks of a stripe where K is less than N, i.e., a partial stripe write. If K is greater than (N-1)/2, the N-K unwritten blocks are read in order to compute the new parity information before the actual write take place.”).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the command processing method of Vishne and the writing method for a RAID storage system of Li with the stripe write method of Jones to minimize the number of reads required to compute new parity information when performing partial stripe write operations (See abstract of Jones).
Regarding claim 14, Li teaches:
The method of claim 13, further including writing both the new parity and new data sectors to the backend memory (See abstract “this method further comprises: flushing the new data and the new parity information into the data block and the parity block in the at least one disk array group, respectively.”).
Response to Arguments
Applicant's arguments filed May 1, 2026 in regard to the amendments filed on May 1, 2026 have been fully considered and are persuasive. However, newly found prior art Flett has been used to teach the argued amendments filed on May 1, 2026. All pending claims in the instant application are rejected herein.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL L WESTBROOK whose telephone number is (571)270-5028. The examiner can normally be reached Mon-Fri 9am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached at (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL L WESTBROOK/Examiner, Art Unit 2139
/REGINALD G BRAGDON/Supervisory Patent Examiner, Art Unit 2139
