Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1. Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
2. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-6 and 9 are under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9, “time value” is unclear what value is comparing with wafer swap time…. Clarification requested.
Claim 5 recites the limitation "the filtered wafer data” in line 3. There is insufficient antecedent basis for this limitation in the claim.
As per claim 6, these claims are at least rejected for their dependencies, directly or indirectly, on the rejected claim 5. They are therefore rejected as set forth above.
Claim Rejections - 35 USC § 101
3. 35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefore, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an
abstract idea without significantly more.
Under step 2A prong one, determine whether a claim recites a judicial exception, see MPEP 2106.04 II.
Claim 1, recites a communication circuit; at least one processor; and at least one memory configured to store instructions, the at least one memory and instructions configured to, with the at least one processor, cause the electronic device to: receive equipment data of a semiconductor exposure equipment from an external database through the communication circuit, generate integrated data that integrates the equipment data by wafer and equipment model, generate a model that predicts daily wafer production of the semiconductor exposure equipment based on process time of the semiconductor exposure equipment for a wafer using the integrated data, the process time including wafer swap time for each equipment, lot swap time for each equipment, and exposure time for each equipment, and evaluate performance of the semiconductor exposure equipment based on the generated model.
The limitation of “…predicts daily wafer production…” and “evaluate performance of the semiconductor exposure equipment” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind (the group of "mental processes", abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. See MPEP 2106.04(a)(2)) “calculate wafer and lot swap time for each equipment and exposure time for each wafer and lot…” as drafted, is a process that, under its broadest reasonable interpretation, covers mathematical calculations (mathematical concepts - mathematical relationships, mathematical formulas or equations, mathematical calculations (see MPEP § 2106.04(a)(2), subsection I); but for the recitation of generic computer components, “electronic device”. That is, other than reciting “electronic device,” nothing in the claim element precludes the step from practically being performed in the mind. Accordingly, the claim recites an abstract idea.
Under step 2A prong two, determine if the recited abstract idea is integrated into a practical application. MPEP 2106.04 states:
This judicial exception is not integrated into a practical application. In particular, the claim
recites additional element, the electrical device including commination circuit, a processor and a memory to process the “received equipment information…” and “integrates the equipment data…”
The electrical device including commination circuit, a processor and a memory are recited at a high level of generality and given the broadest reasonable interpretation are simply generic computers performing generic computer functions. Generic computers performing generic computer functions, alone, do not amount to significantly more than the abstract idea and mere instructions to implement an abstract idea on a computer.
The computer is used as a tool to perform the generic computer function of “receiving data…” and “integrates the equipment data…” are merely reciting the words "apply it" (or an equivalent) with the judicial exception, merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). As discussed above in Step 2A, Prong One, such that it amounts to no more than mere instructions to apply the exception using a generic computer. In addition, “received equipment information…” and “integrates the equipment data…” merely serves as data collection, the recited judicial exceptions require such receiving data (data gathering), and integrating equipment data is considered insignificant extra-solution activity. The limitations do not impose any meaningful limits on the claim. This step found to be insignificant extra-solution activity in Step 2A, Prong Two, because they were determined to have insignificant limitations as necessary data gathering, See MPEP 2106.05(e). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Under step 2B, determine whether the claim adds a specific limitation other than what is well-understood, routine, conventional activity in the field - see MPEP 2106.05(d).
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a processor to perform both “receiving data…” and “integrates the equipment data…” amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Thus, independent claim 1 is not patent eligible.
Claim 12, recites a communication circuit; at least one processor; and at least one memory configured to store instructions, the at least one memory and instructions configured to, with the at least one processor, cause the electronic device to: receive equipment data of a semiconductor exposure equipment from an external database through the communication circuit, generate integrated data that integrates the equipment data by wafer and equipment model, preprocess the integrated data to obtain wafer data, lot data, and parameter data, calculate wafer swap time for each equipment, lot swap time for each equipment, and exposure time for each equipment based on the wafer data, the lot data, and the parameter data, generate a production prediction model that predicts daily wafer production based on the wafer swap time for each equipment, the lot swap time for each equipment, and the exposure time for each equipment, and evaluate performance of the semiconductor exposure equipment based on the production prediction model.
Under step 2A prong one, determine whether a claim recites a judicial exception, see MPEP 2106.04 II.
claim recites a communication circuit; at least one processor; and at least one memory configured to store instructions, the at least one memory and instructions configured to, with the at least one processor, cause the electronic device to: receive equipment data of a semiconductor exposure equipment from an external database through the communication circuit, generate integrated data that integrates the equipment data by wafer and equipment model, generate a model that predicts daily wafer production of the semiconductor exposure equipment based on process time of the semiconductor exposure equipment for a wafer using the integrated data, the process time including wafer swap time for each equipment, lot swap time for each equipment, and exposure time for each equipment, and evaluate performance of the semiconductor exposure equipment based on the generated model.
The limitation of “…predicts daily wafer production…” and “evaluate performance of the semiconductor exposure equipment” as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind (the group of "mental processes", abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. See MPEP 2106.04(a)(2)) but for the recitation of generic computer components, “electronic device”. That is, other than reciting “electronic device,” nothing in the claim element precludes the step from practically being performed in the mind. Accordingly, the claim recites an abstract idea.
Under step 2A prong two, determine if the recited abstract idea is integrated into a practical application. MPEP 2106.04 states:
This judicial exception is not integrated into a practical application. In particular, the claim
recites additional element, the electrical device including commination circuit, a processor and a memory to process the “received equipment information…”, “integrates the equipment data…” and “preprocess the integrated data….”.
The electrical device including commination circuit, a processor and a memory are recited at a high level of generality and given the broadest reasonable interpretation are simply generic computers performing generic computer functions. Generic computers performing generic computer functions, alone, do not amount to significantly more than the abstract idea and mere instructions to implement an abstract idea on a computer.
The computer is used as a tool to perform the generic computer function of “receiving data…” “integrates the equipment data…” and “preprocess the integrated data….” is merely reciting the words "apply it" (or an equivalent) with the judicial exception, merely including instructions to implement an abstract idea on a computer, or merely using a computer as a tool to perform an abstract idea, as discussed in MPEP § 2106.05(f). As discussed above in Step 2A, Prong One, it amounts to no more than mere instructions to apply the exception using a generic computer. In addition, “received equipment information…” “integrates the equipment data…” and “preprocess the integrated equipment data…” merely serves as data collection, the recited judicial exceptions require such receiving data (data gathering), integrating equipment data and preprocess the integrated equipment data… are considered insignificant extra-solution activity. The limitations do not impose any meaningful limits on the claim. This step found to be insignificant extra-solution activity in Step 2A, Prong Two, because they were determined to have insignificant limitations as necessary data gathering, See MPEP 2106.05(e). Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Under step 2B, determine whether the claim adds a specific limitation other than what is well-understood, routine, conventional activity in the field - see MPEP 2106.05(d).
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a processor to perform both “receiving data…” “integrates the equipment data…” and “preprocess the integrated equipment data…” amounts to no more than mere instructions to apply the exception using a generic computer component. Mere instructions to apply an exception using a generic computer component cannot provide an inventive concept. Thus, independent claim 12 is not patent eligible.
As the dependent claims 2-11 and 13-20, further limit the abstract idea of an analysis that can be performed mentally or certain methods of human activity that were already rejected in claims 1 and 12, but fail to remedy the deficiencies of the parent claim as they do not impose any limitations that amount to significantly more than the abstract idea itself.
As claims 2 and 13, recites a list of metrics … which is insignificant extra solution activity (see MPEP 2106.05(g). Thus, the claims are an abstract idea Thus, the claims are an abstract idea.
As claims 3 and 14, recites removing invalid data is group of "mental processes", abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. See MPEP 2106.04(a)(2). In addition, recites obtain data… considered a generic data gathering-insignificant extra-solution activity. See MPEP2106.05(g). Thus, the claims are an abstract idea.
As claims 4-7 and 15-17, recites calculating swap and lots time and exposure, covers mathematical calculations (mathematical concepts - mathematical relationships, mathematical formulas or equations, mathematical calculations (see MPEP § 2106.04(a)(2), subsection I).
As claims 8 and 18, recite predict the daily wafer and evaluate the performance is group of "mental processes", abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. See MPEP 2106.04(a)(2). In addition, generated equipment statistical data is considered a generic data gathering-insignificant extra-solution activity. See MPEP2106.05(g). Thus, the claims are an abstract idea.
As claims 9-10 and 19, recite determination, identify and evaluation is considered a group of "mental processes", abstract idea grouping is defined as concepts performed in the human mind, and examples of mental processes include observations, evaluations, judgments, and opinions. See MPEP 2106.04(a)(2).
As claims 11 and 20, recites outputting an equipment performance and an equipment solution is considered insignificant extra post-solution activity that does not meaningfully integrate an abstract idea into a practical application. See MPEP2106.05(g).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
4. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4.1 Claim(s) 1-4 and 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20080071405 A1) in view of Miwa et al. (JP2005190031A).
Regarding claim 1, Liu discloses electronic device (computer system 4), comprising: a communication circuit (Fig. 1, communicates via link 6); at least one processor ([0032], Fig. 1, processor in computer system 4); and at least one memory configured to store instructions (Abstract, a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded), the at least one memory and instructions configured to ([0032],Fig. 1, The computer readable medium is encoded with computer program code, wherein, when the computer program code is executed by a computer processor in computer system 4, with the at least one processor, cause the electronic device to:
receive equipment data (Fig. 1, [0029], tool event data, i.e. wafer time log data) of a semiconductor exposure equipment (Fig. 5, [0038], the exposure tool D4) from an external database([0030], Fig. 1, TP2 data from relational MES database 18) through the communication circuit ([0029], Semiconductor Equipment Communication Standard interface and communicates via link 6),
generate integrated data ([0008], [0030], Fig. 12, integrated the MES data and TS2 data in the MES database) that integrates the equipment data by wafer ([0029], Fig. 1, the event data, i.e. wafer time log data of lithography tools of) and equipment model ([0026], Fig. 1, lithography tools such as ILSC (I-line scanners), DUV scanners and other suitable tools), and
the process time including wafer swap time for each equipment ([0028], The wafer time log data provided to computer system 4 also includes times for transporting wafers), lot swap time for each equipment ([0028], lot-to-lot set up and transfer times) and exposure time for each equipment lithography tool 2 includes an exposure area in which a wafer is exposed, and lithography tool 2).
Liu fails to disclose generate a model that predicts daily wafer production of the semiconductor exposure equipment of the semiconductor exposure equipment for a wafer using the integrated data; and evaluate performance of the semiconductor exposure equipment based on the generated model.
Miwa discloses generate a model that predicts daily wafer production of the semiconductor exposure equipment (page 2, par. 3, the bottleneck device occurrence prediction processing unit is calculating the required number of wafers for each daily manufacturing apparatus; processing for acquiring wafer processing time for each product / process / manufacturing equipment, and daily information for each product) based on process time (page 13, par. 4, processing time per wafer) of the semiconductor exposure equipment for a wafer (page 13, par. 3, photolithography process and exposure apparatus calculate time per wafer) using the integrated data (page13, par. 4, page 9, par. 2, the bottleneck device prediction generation processing unit 7 receives production plan information, in-process lot information, process master information, and device master from the database unit 4), and
evaluate performance of the semiconductor exposure equipment based on the generated model (page 2, par. 3, obtaining a production plan to be evaluated; the production plan to be evaluated, the in-process lot information of the current production line, and each product / process Inter-process TAT, wafer processing time and statable manufacturing equipment information, processing for obtaining wafer processing time for each product/process/manufacturing equipment, processing for obtaining manufacturing equipment information to be bottlenecked).
Liu and Miwa are analogous art. They relate to the production plan information and in-process wafer and lot information. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify semiconductor device manufacturing for a photolithography process, taught by Miwa incorporated with lithography tools used in semiconductor manufacturing, taught by Liu, for avoiding bottlenecks in semiconductor device manufacturing, A reduction in processing time at any particular processing operation produces an increased WPH (wafers per hour) output for the processing tool and this increased manufacturing tool output improves the efficiency of the tool producing a cost savings.
Regarding claim 12, Liu discloses electronic device (computer system 4), comprising:
a communication circuit (Fig. 1, communicates via link 6);
at least one processor ([0032], Fig. 1, processor in computer system 4); and
at least one memory configured to store instructions (Abstract, a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded), the at least one memory and instructions configured to ([0032],Fig. 1, The computer readable medium is encoded with computer program code, wherein, when the computer program code is executed by a computer processor in computer system 4,, with the at least one processor, cause the electronic device to:
receive equipment data (Fig. 1, [0029], tool event data, i.e. wafer time log data) of a semiconductor exposure equipment (Fig. 5, [0038], the exposure tool D4) from an external database([0030], Fig. 1, TP2 data from relational MES database 18) through the communication circuit ([0029], Semiconductor Equipment Communication Standard interface and communicates via link 6),
preprocess the integrated data to obtain wafer data, lot data, and parameter data ([0007], the classifying the wafer time log data (wafer data, lot data) according to other of the fabrication parameters and responsive to the querying, and generating a data display that identifies at least one lithography operation bottleneck by comparing operation time data between at least one other of the fabrication parameters. The operation time data includes wafer processing and wafer transport times),
calculate wafer swap time for each equipment, lot swap time for each equipment, and exposure time for each equipment based on the wafer data, the lot data, and the parameter data ([0008], [0028],[0040], [0044], calculating LOT p-time, t-time, wafer number, start, end time divide into a sub-unit), of wafer swap time on the wafer data ([0028], the wafer time log data provided to computer system 4 also includes times for transporting wafers. Transport times include wafer-to-wafer transfer times at a particular sub-unit, station-to-station transfer times) and lot swap time on a lot data ([0028],[0036], lot-to-lot set up and transfer times) for each equipment model ( lithography tool 2, D0, D4, D5, E1 and E3 ) and lot swap time for each equipment model based on the lot data, respectively ([0024], wafer time log data is recorded for multiple lithographic tools in a fabrication area, multiple technologies, multiple device types, multiple recipes, and at multiple device levels. This data covers multiple lots. A lot is a group of wafers that are transported and processed together through a fabrication area, he wafer time log data includes processing and transport times for individual components of each lithography tool, the individual components including wafer coders, cooling plates, developer heads, hard bake units, soft bake units, post exposure bake units, exposure operations and adhesion treatment).
Liu fails to disclose generate a production prediction model that predicts daily wafer production based on the wafer swap time for each equipment, the lot swap time for each equipment, and the exposure time for each equipment, and evaluate performance of the semiconductor exposure equipment based on the production prediction model.
Miwa discloses a production prediction model that prdict daily wafer production of the semiconductor exposure equipment (page 2, par. 3, the bottleneck device occurrence prediction processing unit is calculating the required number of wafers for each daily manufacturing apparatus; processing for acquiring wafer processing time for each product / process / manufacturing equipment, and daily information for each product) based on process time (page 13, par. 4, processing time per wafer) of the semiconductor exposure equipment for a wafer (page 13, par. 3, photolithography process and exposure apparatus calculate time per wafer) using the integrated data (page13, par. 4, page 9, par. 2, the bottleneck device prediction generation processing unit 7 receives production plan information, in-process lot information, process master information, and device master from the database unit 4), and
evaluate performance of the semiconductor exposure equipment based on the generated model (page 2, par. 3, obtaining a production plan to be evaluated; the production plan to be evaluated, the in-process lot information of the current production line, and each product / process Inter-process TAT, wafer processing time and statable manufacturing equipment information, processing for obtaining wafer processing time for each product/process/manufacturing equipment, processing for obtaining manufacturing equipment information to be bottlenecked).
Liu and Miwa are analogous art. They relate to the production plan information and in-process wafer and lot information. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify semiconductor device manufacturing for a photolithography process, taught by Miwa incorporated with lithography tools used in semiconductor manufacturing, taught by Liu, for avoiding bottlenecks in semiconductor device manufacturing, A reduction in processing time at any particular processing operation produces an increased WPH (wafers per hour) output for the processing tool and this increased manufacturing tool output improves the efficiency of the tool producing a cost savings.
Regarding claims 2 and 13, Liu discloses generated data by integrating the process time (Fig. 2-Fig. 12, integrated the MES data and TS2 data into the SEM database of the process time) , measurement value of equipment sensor([0039], various operation time data is presented for I-line Scanner tools C2, C3, C4, C5 and E4), error and event information of equipment ([0038], analyst may conclude that the laser frequency calibration is incorrect for the exposure tool D4, tool E4 has the highest lost time), and parameter value of the equipment ([0038], fabrication parameter, and comparative data is shown for five lithography tools) and product among the equipment data for each wafer and equipment model (Fig. 2-Fig. 12, [0038], lithography tool D4 has the longest exposure time for similar energy produced and is a bottleneck. E3 has the fastest exposure time).
Regarding claims 3 and 14, the combination of Miwa and Liu disclose:
Miwa discloses removed invalid data of the integrated data (page 11, par. 6, statistical abnormality removal processing may be used to remove data that can be regarded as abnormal in the number of processed wafers and the apparatus operation rate compared to other days; page 13, par. 3, statistical anomaly removal processing may be used to remove data with an abnormal processing time compared to other lots).
Lui discloses obtain wafer data by sorting wafer-related data of the integrated data according to exposure time (Fig. 3-9, Fig. 12, [0007], [0008], obtaining wafer time log data from each of a plurality of lithography tools, parsing the wafer time log data and providing the wafer time log data to a database, classifying the wafer time log data according to other of the fabrication parameters and exposure operations); obtain lot data by sorting lot-related data of the integrated data according to time the wafer was input into the equipment (Fig. 3-9, Fig. 12, [0024], [0028], recorded for multiple lithographic tools in a fabrication area, multiple technologies, multiple device types, multiple recipes, and at multiple device levels. This data covers multiple lots. A lot is a group of wafers that are transported and processed together through a fabrication area) and obtain parameter data by sorting parameter value of equipment ([0032], [0033], obtain from user interface one or more fabrication parameters. Fabrication parameters include photolithography tool 2, device type, recipe, device level, lot number technology type, and pre-summarizes the data according to other fabrication parameters and responsive to the querying), and product of the integrated data (Fig. 12, integrated the MES data and TS2 data into the SEM database) and measured value of equipment sensor according to sensor measurement time ([0007], [0024], measured or recorded at semiconductor processing operations including process time and transfer time).
Regarding claim 4, Liu discloses calculate a first quartile ([0028],[0040], [0044], calculating LOT p-time, t-time, wafer number, start, end time divide into a sub-unit), of wafer swap time on the wafer data ([0028], the wafer time log data provided to computer system 4 also includes times for transporting wafers. Transport times include wafer-to-wafer transfer times at a particular sub-unit, station-to-station transfer times) and lot swap time on a lot data ([0028],[0036], lot-to-lot set up and transfer times) for each equipment model ( lithography tool 2, D0, D4, D5, E1 and E3 ) and lot swap time for each equipment model based on the lot data, respectively ([0024], wafer time log data is recorded for multiple lithographic tools in a fabrication area, multiple technologies, multiple device types, multiple recipes, and at multiple device levels. This data covers multiple lots. A lot is a group of wafers that are transported and processed together through a fabrication area).
Regarding claims 7 and 17, Lui discloses the wafer swap time for each equipment ([0003], [0028], wafer-to-wafer transfer times between the unit operations), the lot swap time for each equipment ([0003], [0028], lot-to-lot set up transfer times to consider), and the exposure time for each equipment are times for one wafer ([0028], as exposure operations which are programmed for exposure amount and for which time is a dependent variable. The wafer time log data provided to computer system 4 also includes times for transporting wafers. Transport times include wafer-to-wafer transfer times at a particular sub-unit, station-to-station transfer times and lot-to-lot set up and transfer times), and the model (is obtained by dividing time corresponding to a day by a sum of the wafer swap time for each equipment, the lot swap time for each equipment, and the exposure time for each equipment ([0036],[0037], Fig. 3, Fig. 4. operation time data for various identified lots (LOT_ID) processed through lithography tool. processed through lithography tool WPPHC5#1 using various (RETICLE_ID) and recipes (RECIPE_ID). The operation time data includes processing time (P_TIME), lost time, processing (P) average, maximum, and minimum times and transfer (T) average, maximum, and minimum times, as well as WPH. The duration, i.e. time-period analyzed; and average of WPH; average of P_TIME (processing time); average of AVG_P (average processing time); average of AVG T (wafer-to-wafer transfer time); and sum of BATCH--the number of lots run with these particulars).
Regarding claims 8, 16 and 18, Lui discloses predict the daily wafer production for each equipment based on the model ([0044], Fig. 3-9 and 12, the start daily monitoring 301 wafer production based on each number of lithography tools 2), generate equipment statistical data (Fig. 3-9, Fig. 12, [0044], calculate the lot p-time, t-time, wafer number…the 303-307 of the lithography tools 2) on production (wafer production- recipe, rerun time …303-307) for each equipment (each number of lithography tools 2) based on the integrated data (integrated or Join the number of lithography tools data and MES data in the MES database), and evaluate the performance for each equipment based on the equipment statistical data and the predicted production ([0044], Fig. 12, calculating LOT p-time, t-time, wafer number, start, end time, batch, avg., max, min. of wafer p-time, t-time).
Regarding claims 9 and 19, Lui discloses based on a determination that the performance of the equipment has deteriorated through the evaluation ([0038], The bottleneck in using lithography tool D4 would lead an analyst to consider aspects that cause the average processing AVG_P time in D4 to exceed that in the other tools. An analyst may conclude that the laser frequency calibration is incorrect for the exposure tool D4), identify a time value that is greater than or equal to a time value among the wafer swap time ([0032], Fig. 4, [0041], wafer transport times), the lot swap time (Fig.6, [0028], lot-to-lot set up and transfer times) and the exposure ([0032], time exposure time ([0032],[0038], identifies at one lithography processing bottleneck by comparing operation time data between the other fabrication parameters. The operation time data includes wafer processing times and wafer transport times, lithography tool D4 has the longest exposure time, Fig. 6 indicates that tool E4 has the highest lost time, significantly greater than the lost time for the other four tools), and determine a cause of loss of the equipment based on the identified time value ([0036], a bottleneck a lost time incident that is too great in duration, i.e. "lost time too long" as well as two lots that include a processing time that exceeds 17 minutes and which also represents a bottleneck. FIG. 3 also illustrates incidents in which AVG_T, average transfer time, represents an alarmingly high percentage of the average processing time, AVG_P, exposure time average for each of the wafers).
Regarding claim 10, Liu discloses identify error (0038], the laser frequency calibration is incorrect for the exposure tool D4) and event information of the equipment ([0038], lithography tool D4 would lead an analyst to consider aspects that cause the average processing AVG_P time in D4 to exceed that in the other tools), parameter values of the equipment ([0038], a fixed fabrication parameter), product from the integrated data ([0036] FIG. 3, integrated the WPH report 40 with the lithography tool WPPHC5#1 representing the fabrication parameter specified, i.e. fixed, and shows operation time data for various identified lots (LOT_ID) processed through lithography tool WPPHC5#1 using various (RETICLE_ID) and recipes (RECIPE_ID)), and determine the cause of loss of the equipment based on the identified information ([0038], An analyst may conclude that the laser frequency calibration is incorrect for the exposure tool D4).
Regarding claims 11 and 20, Liu discloses a display ([0039], Fig. 6, automatically highlighted in the data display), and wherein the electronic device (computer 4) is further configured to: output an equipment performance evaluation result obtained based on the evaluation ([0039], Fig. 6, An analyst is thus directed to troubleshoot E4. The bottleneck of the greatest lost time at tool E4 is identified) and the cause of loss ([0039], An analyst may conclude that the laser frequency calibration is incorrect for the exposure tool D4), and an equipment solution corresponding to the cause of loss on the display (Fig. 6, [0039], [0040], indicates that tool E4 has the highest lost time, significantly greater than the lost time for the other four tools. An analyst is thus directed to troubleshoot E4, Corrective action in the lithography process can then be taken responsive to the identified bottlenecks).
Regarding claim 15, Liu discloses calculate wafer swap time, lot swap time for each equipment model based on the wafer data and lot data, respectively, ([0008], [0028],[0040], [0044], calculating LOT p-time, t-time, wafer number, start, end time divide into a sub-unit), of wafer swap time on the wafer data ([0028], the wafer time log data provided to computer system 4 also includes times for transporting wafers. Transport times include wafer-to-wafer transfer times at a particular sub-unit, station-to-station transfer times) and lot swap time on a lot data ([0028],[0036], lot-to-lot set up and transfer times) for each equipment model ( lithography tool 2, D0, D4, D5, E1 and E3 ) and lot swap time for each equipment model based on the lot data, respectively ([0024], wafer time log data is recorded for multiple lithographic tools in a fabrication area, multiple technologies, multiple device types, multiple recipes, and at multiple device levels. This data covers multiple lots. A lot is a group of wafers that are transported and processed together through a fabrication area, he wafer time log data includes processing and transport times for individual components of each lithography tool, the individual components including wafer coders, cooling plates, developer heads, hard bake units, soft bake units, post exposure bake units, exposure operations and adhesion treatment), and calculate the exposure time for each equipment based on the wafer data and the parameter data([0008], the wafer time log data includes processing and transport times for individual components of each lithography tool, the individual components including wafer coders, cooling plates, developer heads, hard bake units, soft bake units, post exposure bake units, exposure operations and adhesion treatment).
4.2 Claim(s) s 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20080071405 A1) in view of Miwa et al. (JP 2005-190031 A) further in view of Zhang et al. (US20110156152A1).
Regarding claim 5, the combination of Liu and Miwa discloses the limitations of claim 1, in addition, regarding claim 5, Liu discloses learn a correlation (Fig. 3-9, wafer WPH report 40) between exposure time ([0036],[0038], exposure time average for each of the wafers) and equipment ([0036], Fig. 3, the lithography tool D0, D4, D5, E1 and E3) and product parameter using the filtered wafer data and the parameter data ([0007], [0008], one fixed fabrication parameter of a plurality of fabrication parameters and classifying the wafer time log data), and calculate the exposure time for each equipment based on the learned correlation (Fig. 3, Fig. 4, Fig. 12, [0027], [0028], calculate average of WPH; average of P_TIME (processing time) the wafer p-time t-time for each lithography tools, exposure operations which are programmed for exposure amount and for which time is a dependent variable), but Liu fails to disclose perform filtering on overlapping exposure on the wafer data.
However, Zhang discloses perform filtering on overlapping exposure on the wafer data (Abstract, [0023], A portion of the overlapping layer can be removed using CMP. The overlapping layer can have a higher polishing rate than the underlying layer so that the underlying layer remains substantially intact after removing the overlying layer).
Zhang, Liu and Miwa are analogous art. They relate to semiconductor manufacturing process. Therefore, before the effective filing date of the claimed invention, it would have been obvious to a person of ordinary skill in the art to modify an overlapping layer on a wafer and removing portions, taught by Zhang, incorporated with teaching of Miwa and Liu, as stated above, in order to planarize a semiconductor wafer having a patterned overlapping layer. Isotropic etching can remove a portion of the patterned overlapping layer to produce tapered sidewalls of reduced height.
Regarding claim 6, Liu discloses calculate exposure time ([0038], Fig. 3, Fig. 12, calculate exposure) for each process recipe (Fig. 3, [0024], programmed times for the various process recipes used in photolithographic processing operations) of each equipment ([0038],Fig. 3, lithography tools D0, D4, D5, E1 and E3) based on the learned correlation ([0028], [0036], 12, FIG. 3, WPH report 40 with each lithography tool calculate exposure operation time data for various identified lots (LOT_ID) processed through lithography tool WPPHC5#1 using various recipes (RECIPE_ID)); and based on a ratio between at least one process recipe processed by each equipment ([0040], [0044], Unit process times are indicated by U-time and table 70 illustrates bottlenecks 72 indicating that, for each recipe, photolithography tool C2 has the slowest unit processing time for the post exposure bake stations and developer stations and photolithography E4 has the slowest unit time for the develop stations).
Citation Pertinent prior art
5. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shinagawa (US20220092242A1) discloses a method for wafer result prediction. The method includes determining predictor parameters of a semiconductor process using domain knowledge that includes knowledge of the semiconductor process, a processing tool associated with the semiconductor process, a metrology tool, and/or the wafer.
Paul (US 20210116895 A) discloses a receiving, from one or more sensors associated with manufacturing equipment, current trace data associated with producing, by the manufacturing equipment, a plurality of products; performing signal processing to break down the current trace data into a plurality of sets of current component data mapped to corresponding component identifiers.
Adams, III (US9523976B1) discloses a method and system for processing a semiconductor wafer using data associated with previously processed wafers.
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for allthat it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed wereinstead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1 009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. Biocraft Labs., Inc., 874 F.2d804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163USPQ 545, 549 (CCPA 1969).
Conclusion
6. Any inquiry concerning this communication or earlier communications from the examiner should be directed Kidest Worku whose telephone number is 571-272-3737. The examiner can normally be reached on Mon-Fri 9am to 5pm, ET.
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/KIDEST WORKU/ Primary Examiner, Art Unit 2119
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