DETAILED ACTION
Claims 1, 4-5, 7, 10, 13, 16-17, 19 are amended. Claims 2, 11, 18 are canceled. Claims 1, 3-10, 12-17, 19-20 are pending.
Priority: 10/16/2023(FP)
Assignee: Samsung
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendments.
Claim(s) 1, 3-10, 12-17, 19-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
1.Amended Claims 1, 17 are rejected for reciting a limitation that is unclear, ambiguous and indefinite.
Claim 1 recites 'receiving a mapping instruction to map target data onto a process address space for a …..application, the process address space comprising….virtual areas, each virtual area mapped to a region of the application….',
But Para-0145 of the spec recites, ‘When an electronic device executes an application, the electronic device may allocate a process address space to the ….application’.
The mismatch between the claim and the spec introduces an ambiguity whether the ‘application’ in the claim must already exist prior to the step of receiving the mapping instruction, or if the process address space is only created dynamically when the application is executed as described in the spec.
The claim suggests an existing application and an already-established process address space with virtual areas to receive a mapping instruction.
But the spec suggests that the process address space does not fully exist or get allocated until the application is executed.
The mismatch between the claim and the spec makes the precise temporal or structural relationship between the application, the instruction, and the allocation of the process address space unclear.
Because the claim covers receiving instructions before execution, but the spec only teaches allocation during execution, the scope of the claim is rendered unclear, hence indefinite. Accordingly Claim 1 is rejected. Claim 17 has the same issue and is also rejected.
2.Amended Claims 1, 17 are rejected for reciting a limitation that is unclear, vague, ambiguous and indefinite.
Claim 1 recites '….the unused node being a node that has no corresponding virtual area and remains in the tree to preserve a structure of the tree'. The spec does not recite this limitation.
The spec defines an unused node simply as one ‘that do not correspond to the plurality of virtual areas’ (See spec, Para-0006). But the claim adds a new functional limitation ‘remains in the tree to preserve a structure of the tree’ for the unused node, which lacks explicit description in the spec.
The spec never explains how an unused node preserves structure or what structural constraints keep it in the tree. Furthermore ‘preserve a structure’ is vague without a baseline definition of what structure is being preserved or how the node does it.
The spec does not provide structural support or functional details for how an unused node actively preserves tree structure, creating ambiguity as to what structural elements are required or excluded.
The claim alters the definition of the unused node from a simple negative limitation (not corresponding to a virtual area) to an active structural role, rendering an inconsistent scope.
Hence claim 1 is rejected as being indefinite for failing to particularly point out and distinctly claim the subject matter. Claim 17 has the same issue and is also rejected.
3.Amended Claims 1, 10, 17 are rejected for reciting a limitation that is unclear, inconsistent and indefinite.
Amended Claim 1 recites, ‘marking the unused node as a use node to reuse without deleting the unused node ….and without adding a new node to the tree, so that a tree rebalancing due to added addition or deletion of a node is prevented….’.
Paras-0007,0016,0063 of the spec and claims 3,12, explicitly recite, ‘The tree may include a self-balancing binary search tree’. So, claiming a self-balancing BST while explicitly precluding structural additions or deletions that define how a self-balancing BST functions is contradictory.
A self-balancing BST inherently relies on structural rebalancing (rotations/adjustments) triggered by insertions and deletions to maintain its balanced property.
Disclosing a self-balancing BST in the spec, while asserting that tree rebalancing, additions, or deletions are entirely ‘prevented’ creates an inconsistent and technically incorrect limitation.
Therefore, simultaneously disclosing a self-balancing BST and denying the core mechanism that keeps it self-balancing, makes the limitation inconsistent with the definition and prior art-recognized operation of a 'self-balancing BST’. As a result, the limitation is vague, ambiguous, and fails to provide with reasonable certainty the scope of claim 1 and the claimed tree. Hence claim 1 being indefinite, is rejected. Claim 17 has the same issue and is also rejected.
Amended Claim 10 presents the same contradiction as it recites, ‘marking the use node in the tree….as an unused node without deleting the use node from the tree…., so that rebalancing due to addition or deletion of a node is prevented….’. The limitation renders the scope uncertain. Hence claim 10 being indefinite, is rejected.
Note: This issue was previously mentioned. Based on the amendments and arguments, the rejection has been clarified and maintained.
4.Amended Claims 1, 10, 17 are rejected for reciting a limitation that is unclear, vague and indefinite.
Amended Claim 1 recites, ‘executing an operation of the application using the memory based….managed by the tree’. The spec does not recite this limitation.
In Para-0145, the spec recites ‘an electronic device executes an application’. ‘Executing an application’ differs from ‘executing an operation of the application’.
That said, claim 1 recites receiving a mapping instruction to perform a mapping operation. But it is unclear what the new(?) ‘an operation’, in above limitation refers to, rendering the scope of claim 1 indefinite. Hence claim 1 is rejected. Claim 17 has the same issue and is also rejected.
Amended claim 10 has the same issue as it recites ‘executing an operation of the application’. Claim 10 recites receiving an unmapping instruction to perform an unmapping operation. So, it is unclear what the new ‘an operation’ refers to, rendering the scope of claim 10 indefinite. Hence claim 10 is rejected.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendment(s).
Claim(s) 1, 3-10, 12-17, 19-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
1.Amended Claims 1,17 are rejected for reciting a limitation that is unsupported by the spec.
Claim 1 recites, ‘determining,…., whether an unused node exists in the tree by searching the tree for the unused node’. The spec does not teach this limitation.
In Fig. 6, Paras-0005,0008, the spec only describes determining if an unused node exists as an inseparable sub-step within the specific sequence of marking an unused node as a use node (which also requires setting a lock and searching for a space). But the claim broadens the scope by isolating the ‘searching/determining’ step as a standalone limitation, which is not described as an independent variation in the disclosure as filed.
The spec fails to provide descriptive support for performing the search/determination independently or conditionally outside of the mandatory sequence with setting a lock and searching for a target space (marking).
The spec fails to show that the inventor was in possession of the claimed step of ‘determining…..instruction, whether an unused node exists in the tree by searching the tree for the unused node’ as a standalone or decoupled operation. Hence claim 1 fails to comply with the spec, thereby reciting new matter and is rejected. Claim 17 has the same issue and is also rejected.
2.Amended claims 1, 17 are rejected for reciting a limitation that is unsupported by the spec.
Claim 1 recites, ‘marking the unused node as a use node to reuse without deleting the unused node from the tree and without adding a new node to the tree, so that rebalancing…. is prevented and overhead in memory allocation is reduced’.
The claim does not align with the spec. The claim broadly covers achieving a result (preventing tree rebalancing by marking without deleting/adding) through any means, whereas the spec (Fig. 6) discloses a specific, detailed routine involving setting a read lock, searching process address space, and checking node existence before marking.
Claim 1 recites the negative functional limitation ‘so that rebalancing due to addition or deletion of a node is prevented’ without requiring the specific steps of ‘setting a lock’, ‘searching for a space’, and ‘determining whether the unused node exists’.
The spec provides a specific, step-by-step operational sequence for setting a lock and mapping target data, but it fails to disclose how this specific marking sequence achieves the broad prevention of tree rebalancing without node addition or deletion. The spec fails to provide descriptive text, and clear examples of achieving ‘rebalancing prevention’.
As a result, the spec does not convey that the inventor was in possession of the full scope of preventing rebalancing by merely marking an unused node as claimed, separate from the specific lock-and-search routine.
The spec in Para-0008 explicitly defines the 'marking of the unused node' as an integral process that includes 'searching for a space to be mapped with the target data' and 'determining whether the unused node exists in the tree' and only ‘in response to an unused node existing, performing the marking’.
The spec fails to provide descriptive support for marking an unused node as a used node isolated from this specific search and determination process. By omitting the required search and determination steps (See spec: Fig. 6, steps 603, 605), the claim improperly broadens the disclosure to encompass situations where the system attempts to mark a node without verifying that an unused node actually exists in the tree (Fig. 6: step 605-Does unused node exist ?), to prevent rebalancing. Therefore, the spec fails to convey that the inventor was in possession of the ‘marking’ as broadly recited in claim 1. Hence claim 1 recites new matter and is rejected. Claim 17 has the same issue and is also rejected.
3.Amended Claims 1, 17 are rejected for reciting a limitation that lacks written description support.
Claim 1 recites, ‘wherein the marking is performed without acquiring a lock that enables a writing operation to the tree, thereby enabling concurrent access to the process address space’.
The claim directly contradicts the spec.
The claim recites a negative/functional limitation (‘performed without acquiring a lock that enables a writing operation’) that contradicts the spec and lacks disclosure.
The claim recites marking an unused node without acquiring a lock for a write for concurrent access. But the spec (Fig. 6) explicitly teaches that the marking process includes setting a lock enabling a read operation and a multi-step search/determination sequence.
In other words, the spec discloses (setting a read-operation lock, searching, determining, and marking) versus what the claim demands (absence of a writing-operation lock for concurrent access).
The spec fails to convey possession of the broad scope or alternative method claimed, effectively leaving the claimed lack of a writing operation lock for concurrent access unsupported by the spec. Hence claim 1 is rejected. Claim 17 has the same issue and is also rejected.
4.Amended Claims 1, 17 are rejected for reciting a limitation that is unsupported by the spec.
Claim 1 recites, ‘….the unused node being a node that has no corresponding virtual area’.
Para-0006 recites, ‘The tree may manage the process address space using a plurality of use nodes ….and one or more unused nodes that do not correspond to the plurality of virtual areas’.
The claim recites a BST managing address space using ‘unused nodes that do not correspond to the plurality of virtual areas’, but the spec merely provides a functional result (‘do not correspond’) without describing how these unused nodes are structurally or functionally configured, distinguished, arranged or maintained such that they do not correspond to the virtual areas.
The spec fails to provide written description detailing the operational mechanism or structural relationship/mapping of the unused nodes in relation to the process address space. There is no disclosure of a mapping table.
Without an algorithmic correlation in the text, drawings, or code, the inventor has not provided descriptive support. Hence, the spec fails to convey that the inventor was in possession of determining how unused nodes do not correspond to virtual areas, at the time of filing and claim 1 is rejected. Claim 17 has the same issue and is also rejected.
5.Amended claim 10 is rejected for reciting a limitation that is unsupported by the spec.
Claim 10 recites, ‘receiving an unmapping instruction to cancel mapping of data …in a process address space allocated for a deep learning application’.
The spec does not recite this limitation. The spec only speaks broadly to generic applications without detailing the deep learning context. A casual recitation, ‘Fig. 11 ….describing a tree managing a process address space of a deep learning application’ in the spec, does not fulfill the written description requirement to unmap data. The spec does not disclose how the unmapping instruction interacts with the process address space of the deep learning application, to unmap data.
Para-0145 of the spec recites that the ‘data’ for the deep learning application are tensors (multi-dimensional arrays). But as shown below, the spec fails the enablement prong of 112(a).
The spec does not disclose the specific name or details of the ‘unmapping instruction’. Therefore the spec fails to convey that the inventor was in possession of a specific unmapping instruction for the deep learning application, as of the filing date.
Without disclosing the details of the specific unmapping instruction to unmap data from the process address space for a deep learning application, but claiming ‘receiving an unmapping instruction to cancel mapping of data….for a deep learning application’, renders the limitation fatally broad because it covers all unmapping instructions and all possible methods to achieve the result (unmap data), thereby exceeding the disclosure's contribution.
The spec fails to show that the inventor was in possession of the claimed scope at the time of filing. Claim 10 overreaches the scope of the spec thereby introducing new matter. Accordingly claim 10 is rejected.
Note: The rejection is necessitated by the present amendments and arguments.
6.Amended claim 10 is rejected for reciting limitations that are unsupported by the spec.
Amended claim 10 recites, ‘setting a read lock enabling a read operation to the tree, determining,….instruction, whether a use node corresponding to the target virtual area exists in the tree corresponding to a target virtual area in the process address space by searching the tree for the use node’. Nowhere does the spec recite these limitations.
As listed below, amended Claim 10 recites multiple limitations that recite new matter as follows:
(A)...The claim recites ‘setting a read lock enabling a read operation to the tree’. But Fig. 8, Para-0113 of the spec recites, ‘the electronic device may set a lock to enable a read operation to a tree. Claiming a specific ‘read lock’ when the spec only discloses generic locks fails to convey that the inventor possessed a ‘read lock’ specific paragraph.
(B)...The spec at Para-0017, Fig. 8 limits the ‘searching’ step strictly as an integral part of the larger sequence: ‘The marking of the use node as an unused node may include: setting a lock….; searching for the use node….; determining whether a depth of the use node…exceeds a threshold depth; and in response to the depth of the searched use node not exceeding the threshold depth, marking the use node as an unused node’. The spec fails to show that the inventor was in possession of ‘determining,….instruction, whether a use node exists in the tree…. by searching the tree for the use node’ as a standalone or decoupled operation.
(C)...The claim recites the broad functional result (‘marking….without deleting….and preserving a structure’) but the spec only teaches doing so via a specific algorithmic sequence. The claim is generic/broad to any method of marking a use node while preserving tree structure, but the spec fails to provide a written description that omits the lock setting, depth checking, and threshold comparison steps.
(D)...The last limitation recites, ‘wherein the marking is performed without acquiring a lock that enables a writing operation to the tree, thereby enabling concurrent access to the tree’. The spec only describes marking as- requiring a lock for a read, searching the tree, depth determination, and conditional marking, which fails to disclose the broader, negative functional limitation of operating without a write lock. The spec fails to show that the inventor was in possession of the specific claimed scope, specifically, performing the marking without acquiring a writing-enabling lock and enabling concurrent access.
In summary, the spec fails to show that the inventor was in possession of the full scope of the invention as broadly claimed, at the time of filing.
Hence claim 10 is rejected for overreaching the scope of the spec.
7.Amended Claim 10 is rejected for reciting a limitation that is unsupported by the spec.
Claim 10 recites, ‘marking the use node ….as an unused node…., so that rebalancing due to addition or deletion of a node is prevented’.
Nowhere does the spec recite this limitation.
Para-0017 of the spec explicitly recites, ‘The marking of the use node as an unused node may include: setting a lock….; searching for the use node…; determining whether a depth of the use node searched in the tree exceeds a threshold depth; and in response to the depth of the searched use node not exceeding the threshold depth, marking the use node as an unused node’.
And Fig. 8, Para-0115 of the spec teaches a critical determination step, ‘In operation 805, the electronic device may determine whether a depth of the use node exceeds a threshold depth’.
But the claim covers all instances of marking a node as unused without deletion.
The claim is broader than the spec because the claim recites marking the use node as unused without a depth limitation to prevent tree rebalancing, whereas the spec limits the marking step to situations where the depth of the use node does not exceed a threshold depth.
Therefore the spec fails to provide possession for performing the marking step when the threshold depth is exceeded.
By omitting the threshold depth condition, the claim includes all instances (including marking use nodes that exceed the threshold depth) to prevent rebalancing. Accordingly the claim fails to comply with the written description, and is rejected for reciting new matter.
Claim(s) 6, 15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
1.Claims 6, 15 are rejected for reciting a limitation where the spec fails to disclose how to make and use the disclosure without undue experimentation.
Claim 6 recites, ‘wherein the data comprises one or more tensors’.
And amended claim 1 recites, ‘receiving a mapping instruction to map target data onto a process address space for a deep learning application’.
The data, as recited in claim 1, includes tensors. A tensor is a mathematical object, a multi-dimensional array. But the spec does not define ‘a tensor’ and how it is used, in the context of the ‘deep learning application’. The spec fails to show what structural features of a deep learning application interact with the process address space.
The spec fails to show how the ‘mapping instruction’ operates with tensors. Though ‘mapping’ refers to establishing a relationship/binding between two entities such as sets of data, memory locations etc., neither the spec nor the figures disclose how the ‘mapping instruction’ maps multi-dimensional arrays onto the process address space. The mapping instruction provides no mapping definition or mechanism for multi-dimensional array placement within the process address space. In fact, the mapping instruction provides no mapping definition or mechanism for any type of data placement within the process address space.
Though spec Fig. 11, Para-0146 recites, ‘even if 1064 tensors are mapped onto respective virtual areas’, there is no written description of the actual ‘mapping’/binding between the muti-dimensional arrays and virtual areas. Therefore practicing how the multi-dimensional arrays are mapped onto a virtual area of a ‘use node’ in the tree, would require undue experimentation. Though searching the tree is a key feature of the disclosure, neither the claim nor the spec recite how to search the tree for nodes mapped to multi-dimensional arrays.
Amended claim 10 recites, ‘receiving an unmapping instruction to cancel mapping of data for a target virtual area in a process address space allocated for a deep learning application’. Just as the ‘mapping instruction’ is deficient in mapping tensors to virtual areas, the ‘unmapping instruction’ is equally deficient because it does not provide any written description evidence to prove that it can unmap multi-dimensional arrays from virtual areas and help manage the tree. Therefore practicing the same would require undue experimentation.
Though spec, Para-0053 recites, ‘a tensor processing unit (TPU)’, there is no disclosure of TPU integration and of the role the TPU plays in mapping or unmapping tensors onto the process memory space, in the context of the disclosure, thereby practicing undue research and experimentation.
In essence, since the spec does not disclose how the ‘mapping instruction’ maps/binds the multi-dimensional arrays to the virtual areas/nodes or how the ‘unmapping instruction’ unmaps/unbinds the multi-dimensional arrays from the virtual areas, searching the tree to find an unused node or a used node would require excessive trial-and-error to make and use the disclosure. Hence the mapping instruction and unmapping instruction fail to enable the deep learning application to use the tree as recited in claims 1,10,17.
Note: The amendments do not overcome the rejection because they do not add ‘significantly more’ to the exception, to recite an inventive concept and/or technical benefit. The amendments are well-understood, routine college textbook information. Based on the amendments and arguments, the rejection has been clarified and maintained.
Claim Rejections - 35 USC§ 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefore, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Claims 1, 10 are directed to a ‘processor-implemented method’, and claim 17 is directed to ‘an electronic device comprising one or more processors’. Hence they are directed to a statutory category, i.e., a machine (Step 1: Yes).
Under revised Step 2A, Prong 1 of the eligibility analysis, it is necessary to evaluate whether the claim recites a judicial exception by referring to subject matter groupings articulated in 2106.04(a) of the MPEP. In consideration of the analysis, the claims recite an abstract idea. Claims 1, 10, 17 recite the abstract idea of a pre-populated, static tree, arranged in a hierarchical structure, with used and unused nodes. A tree is based on graph theory, a subfield of mathematics.
Independent claim 1 recites the abstract idea of: receiving a mapping instruction to map data onto a process address space allocated for a deep learning application; marking an unused node in the tree that manages the process/virtual address space, mapping the target data onto a virtual area in the process address space. Independent claims 10 and 17 have similar recitations of the abstract idea.
The nodes contain data, including tensor data. Dependent claim 3 recites that the tree is a self-balancing BST/binary search tree. Dependent claims 4-5, 13, 19-20 recite how to mark an unused node into a use node by searching the tree and adding data to it. Claim 8 recites marking a use node to an unused node by searching the tree and deleting its data.
Claims 1-20 recite a pre-populated, static BST comprising used and unused nodes and perform operations on the tree, such as search the tree to locate the used and unused nodes. Since these operations involve well-known rules to identify a parent node or a child node, the operations performed on the BST are mental processes done easily with a pencil and paper. In fact, the static BST encourages an effortless pencil-paper approach to readily locate nodes rather than employ a realistic assessment of the technical requirements to understand how the BST was built (from the beginning). What further validates the abstract idea is that the underlying rules and design of the tree/BST remain the same regardless of whether the tree is used in a deep learning application or a simple sorting algorithm. Even if the claims require a computer, they may still be considered a mental process since the computer is used merely as a tool to perform the mental steps. See MPEP 2106.04(a)(2). Thus claims 1-20 recite an abstract idea.
Under revised Step 2A, Prong 2 of the eligibility analysis, if it is determined that the claims recite a judicial exception, it is then necessary to evaluate whether the claims recite additional elements that integrate the judicial exception into a practical application of that exception. In this case, claims 1-20 recite additional elements such as ‘process address space’ and ‘virtual areas’. For example, claims 2, 11, 18 recite, ‘the tree manages the process address space using a plurality of use nodes corresponding to a plurality of virtual areas in which data is mapped onto the process address space and one or more unused nodes that do not correspond to the plurality of virtual areas’. Here, the tree managing the process/virtual address space with virtual areas does not provide significantly more than the judicial exception because the step is well-understood, routine, and conventional activity previously known to the industry of application data management.
Furthermore, the claims recite the additional elements as virtual areas, without supporting underlying hardware. The claims do not recite any virtual to physical memory mapping or address translation. Though the data includes tensors, no mechanism is specified to map tensors to virtual memory, leaving the mapping incomplete. Hence the additional elements amount to mere software as they do not represent any structural components of the electronic device. They merely comprise the software for performing the BST operations. Based on Recentive Analytics v. Fox (2025), training a deep learning model without specific improvements to the model architecture or hardware utilization, is deemed patent-ineligible. Claims 1-20 are drawn to software per se. See MPEP 2106.01 (I).
Though the spec recites, ‘an electronic device and method with efficient memory management’, claims 2, 11, 18 merely recite software instructions unsupported by hardware limitations. They do not recite any mechanism that shows how virtual memory is mapped to physical memory, tracked and/or managed.
In essence, the additional elements individually and in combination, do not integrate the exception into the deep learning application or any application. Due to the lack of virtual memory to physical memory mapping, the additional elements do integrate the BST into the deep learning application. They do not include specific, non-generic improvements to the tree structure itself that optimizes the deep learning application. This is because they are merely used to apply the abstract idea using a generic processor, as defined in MPEP 2106.04(d).
Claims 1, 10, 17 recite the step of, ‘wherein the unused/used node remains in the tree during the marking without being deleted from the tree and without adding a new node to the tree, thereby a tree rebalancing….is prevented’. Since the recitation is an inherent feature of every tree, including BST, it is considered to be insignificant extra-solution activity. Extra-solution activity are activities that are incidental to the primary method that are merely a nominal or tangential addition to the claim. See MPEP 2106.05(g).
Under Step 2B of the eligibility analysis, if it is determined that the claims recite a judicial exception that is not integrated into a practical application of that exception, it is then necessary to evaluate the additional elements individually and in combination to determine whether they provide an inventive concept. In this case, claim 3 recites, ‘the tree is a self-balancing binary search tree’. The claimed BST is a binary tree, well-known in graph theory and easily found in a college textbook. And the Claim 13 recitation, ‘searching for the use node corresponding to the target virtual area in the tree……..and in response to the depth of the searched use node not exceeding the threshold depth, marking the use node as an unused node’, is a well-known concept in BST self-balancing, previously disclosed in graph theory in a college textbook. The claims do not focus on improvements to the BST itself, such as reciting a specialized tree-balancing algorithm that reduces memory usage in the deep learning application or any application. Hence claims 3, 13 do not provide significantly more than the judicial exception.
The BST, the tree locking, the node searching, marking etc., are software. The claims are directed to an abstract idea of ‘mapping’ data into virtual areas of a BST, without providing a specific algorithm and hardware configuration for achieving the ‘mapping’. Though deep learning is very hardware intensive, the hardware is recited at a high level or acts merely as a generic tool. The software is not meaningfully integrated with the hardware to improve technology. In other words, the ‘integration’ between the software and the hardware is missing. Hence the claims are directed to the abstract idea on a generic computer.
Since the claims do not recite how the tree and the additional elements, considered individually or in combination, improve the functioning of the electronic device or provide a clear technological improvement, the claims do not provide an inventive concept. The claims amount to no more than applying the abstract idea using a generic computer. For court cases, please see at least: Uniloc USA, Inc. v. Med. Info.Tech., Inc., No. 6:16-cv-00463 (E.D. Tex. Mar. 30, 2017), Visual Memory LLC v. NVIDIA Corp., No. 1:15-cv-00789, Op. at 7, 14 (D. Del. May 27, 2016).
Hence independent claims 1, 10 and 17 recite limitations of the abstract idea and are ineligible subject matter. Dependent claims 2-9, 11-16 and 18-20, also being ineligible, do not aid in the eligibility of their respective parent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-10, 12, 15-18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al (20150193354) in view of Clements et al (‘Scalable Address Spaces Using RCU Balanced Trees’, ACM, 2012, Pgs. 199-210), as evidenced by (Gorman, Jan 2023 version, Chapter 4: Process Address Space, https://www.kernel.org/doc/gorman/html/understand/understand007.html), in further view of Edwards et al (20240168830) and Hyland et al (20030009474), hereinafter ‘Kwon,Clements,Edwards,Hyland’.
As per Claim 1, Kwon discloses a processor-implemented method (Kwon, [Fig. 1: Processor 200]; [0005 - A memory management method of an operating system for a nonvolatile main memory system, and provide a memory mapping method that enables an application program to quickly access a file through memory mapping]) comprising:
receiving (Kwon, [0056 – In Fig. 1, NVM controller 100 communicates with the processor 200 through a processor channel to receive a command and an address to receive data]]) a mapping instruction (Kwon, [0097 - A system call such as mmap]) to map target data onto a process address space (Kwon, [Fig. 15]; [0115 - The user area 310 is a space of a memory accessed by the user by using an application and includes user buffer 315 and library buffer 314]; [0151 – In Fig. 11, step S100, a virtual area of a process is allocated due to a command or a system call of a processor, and the processor applies a mapping command for mapping a virtual address of the virtual area to a physical address of a file page]) for ([See 112(b)]) a deep learning application (Kwon, [0005 - Provide a memory mapping method that enables an application program to quickly access a file/virtual area through memory mapping; Since Fig. 1, Para-0068 recites a multi-core processor which can be used for deep learning, mainly for data preprocessing, data loading, and small-scale training, the ‘application’ is considered equivalent to a deep learning application]),
the process address space comprising a plurality of virtual areas (Kwon, [0066 - The page map table is formed in units of pages/virtual areas, and converts a logical address number/LAN into a physical page number/PPN]; [0067 - When data is stored in units of pages, each page is referred to as a file page]),
determining (Kwon, [Fig. 13]), in response to the mapping instruction (Kwon, [0097 - A system call such as mmap]), whether an unused node exists in the tree (Kwon, [Fig. 15]; [0066 - The page map table is formed in units of pages/virtual areas]; [0057 - A memory-based file system/process address space resides in a memory space of the kernel area]) by searching ([See 112(a)]) the tree for the unused node (Kwon, [0166 – In Fig. 13, step S310, a virtual area corresponding to an allocated virtual address of a process is searched by using a binary data structure such as a red-black tree]),
the unused node being a node that has no corresponding virtual area ([See 112(a)]) and remains in the tree to preserve a structure of the tree (Kwon, [0166 - In Fig. 13, when it is determined in step S320 that the virtual area is being used, the method proceeds to step S330. In step S330, the virtual area that is being used is deleted in the red-black tree, thereby implying that the unused node in the tree does not correspond to a virtual area]);
marking the unused node as a use node ([See 112(a)]) without deleting the unused node from the tree and without adding a new node to the tree (Kwon, [0166 – In Fig. 13, step S340, a virtual area is re-allocated. In step S350, the virtual area may be re-inserted into the red-black tree to be managed, thereby marking unused node as a use node]), so that rebalancing due to added addition or deletion of a node is prevented and overhead in memory allocation is reduced (Kwon, [0168 - In Fig. 13, since an overhead of deleting, allocating, and re-arranging a virtual area in the tree is reduced, a response speed of a memory system is increased]);
mapping the target data onto a virtual area corresponding to the use node (Kwon, [0166 – In Fig. 13, step S360, a virtual address of the virtual area is mapped to a physical address of a file page which the process desires to access]]) in the process address space (Kwon, [0071 - When a file or data is stored/written in nonvolatile main memory 300, the file system/process address space organizes the file or the data]),
wherein the tree manages the virtual area as the use node (Kwon, [0006 - mapping a physical address of the file page to a virtual address of a user area of the nonvolatile main memory]; [0065 - The controller includes a mapping manager including a page map table and the FTL, and a local memory to drive the mapping manager. The FTL functions to convert a logical address provided by the processor 200 into a physical address that is used by the flash memory/NVM]),
Clements clarifies the process address space,
the process address space comprising a plurality of virtual areas (Clements, [Pg. 199, Col. 2, Para-2 - An address space consists principally of a set of memory mapping regions, as shown in Fig. 1]; [Gorman, Sec. 4.2 – Managing the Address Space]),
each virtual area being mapped to a region of a memory of the application (Clements, [Pg. 199, Col. 2, Para-2 - Each memory mapping region describes a range of virtual addresses and stores information about the mapping]; [Gorman, Sec. 4.4 – Memory Regions]),
the process address space being managed by a tree (Clements, [Pg. 199, Col. 2, Para-2 – Widely used operating systems use a tree to store the memory regions because applications often have thousands of memory regions due to dynamic linking and a tree enables the OS to find the region containing a particular virtual address quickly]) comprising a plurality of nodes (Clements, [Pg. 201, Fig. 3 - Circles represent tree nodes]),
wherein the marking ([See 112(a)]) is performed without acquiring a lock that enables a writing operation to the tree (Clements, [Pg. 201, Col. 1, Para-5 - Trees with lock-free lookup]), thereby enabling concurrent access to the process address space (Clements, [Pg. 201, Col. 1, Para-5 - a red-black tree that allows read operations to proceed without locks, and write operations on different parts of the tree to proceed in parallel/concurrent using fine-grained locks]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable address space of Clements into the memory mapping method of Kwon, to enable parallelism by an RCU-based binary balanced tree for storing memory mappings (Clements, Pg. 199, Abstract).
Gorman discloses the Linux Process Address Space and mapping data into the red-black tree with mmap and mremap system calls.
Kwon discloses a multi-core processor executing an application. It is well-known that a multi-core processor can be used for deep learning, mainly for data preprocessing, data loading, and small-scale training. Since GPUs are preferred for heavy model training due to their massive parallelization,
Edwards further clarifies,
receiving a mapping instruction (Edwards, [0400 - A WD fetch unit 3591 in accelerator integration slice 3590 fetches next WD 3584 which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module 3546]; [0464 – In Fig. 42, global thread dispatcher is configured to provide an instruction to a graphics core within a graphics processor]) to map target data (Edwards, [0675 - The API is to receive as input a tensor data type]; [0098 – In Fig. 1, mapping is to be used to store data of first tensor to be stored according to mapping. API receives as input information indicating where to store mapping. API is to receive as input a plurality of characteristics of first tensor. e.g., a shape of tensor, location in memory, size, data type, etc.]; [0491 - Tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing]) onto a process address space (Edwards, [Fig. 35: application effective address space 3582+OS virtual address space 3585]; [0397 - An application effective address space 3582 within system memory 3514 stores process elements 3583]; [0095 – In Fig. 1, an API to cause information to be stored in a plurality of storage locations allocated to a first GPU]) for ([See 112(b)]) a deep learning application (Edwards, [0519 - In Fig. 50, application 5000 is an AI/ML application implemented using a deep learning framework such as MXNet, PyTorch, or TensorFlow]; [Figs. 43-54C]),
the process address space (Edwards, [0400 - MMU 3539 includes segment/page walk circuitry for accessing segment/page tables 3586 within OS virtual address space 3585]) comprising a plurality of virtual areas (Edwards, [0432 - Each processing cluster 3894 includes an MMU 3845 that is configured to map virtual addresses/virtual areas into physical addresses. MMU 3845 includes a set of page table entries/PTEs used to map a virtual address to a physical address of a tile and a cache line index]),
executing an operation (Edwards, [0359 - In Fig. 29, processor 2902 includes execution units to execute an instruction; Since an instruction contains a specific operation, the citation is a valid interpretation]) of the application ([See 112(b)]) using the memory based on the plurality of virtual areas managed by the tree (Edwards, [0400 – OS virtual address space 3585]; [0493 – In Fig. 45, SFUs 4512 include a tree traversal unit configured to traverse a hierarchical tree data structure]; [0525 - An abstract system tree/AST comprises hierarchical data. An abstract tree map to a binary tree using the ‘left-child, right-sibling’ method to store any number of children in a binary form]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the deep learning application of Edwards into the memory mapping method of Kwon, Clements for the benefit of including one or more tensor cores in processing cores. The tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing (Edwards, 0491).
Hyland further clarifies,
marking the unused node as a use node without deleting the unused node from the tree ([See 112(a)]) and without adding a new node to the tree (Hyland, [0043 – In Fig. 7, tree 71 has a predetermined structure such that for each level, each node has two child nodes, thereby implying that the tree is balanced from the beginning]; [0045 - If the tree is structured/balanced as shown in Fig. 7 then Fig. 8 is used when searching for an element]; [Fig. 8: step 82, Element found, thereby implying that the unused node which is the search element is found in the tree; Since the spec does not recite the steps to find ‘unused node’, the citation is a valid interpretation]), so that rebalancing due to added addition or deletion of a node is prevented and overhead in memory allocation is reduced (Hyland, [0035 - Fig. 2 represents a balanced BST which is structured in software]; [0037 - It is desirable to achieve a balanced tree in order to minimize the number of operations required to achieve a match between the keys and the address data in the entry, thereby implying that rebalancing is prevented]; [0013 - The BST design is particularly suited for implementation in hardware with minimal memory]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the balanced BST of Hyland into the memory mapping method of Kwon, Clements, Edwards for the benefit of the BST staying balanced with the same depth of tree both to the left and to the right of the root node (Hyland, Para-0039).
As per Claim 3, the rejection of claim 1 is incorporated, and Kwon discloses,
wherein the tree comprises a self-balancing binary search tree (Kwon, [0166 - In Fig. 13, a virtual area corresponding to an allocated virtual address of a process is searched by using a binary data structure such as a red-black tree; It is well-known that a red-black tree is a self-balancing BST]).
As per Claim 5, the rejection of claim 1 is incorporated, and Kwon, Clements, Edwards, Hyland disclose,
searching for an initial node (Hyland, [0032 - Fig. 3: The index node 120 is a root node]; [0040 - In Fig. 4, the data structure is implemented as a tree structure and includes a Level 0 or root level index page 132, a Level 1 index page 134, and a Level 2 data page 136]; [0041 - A traversal/search begins at the Level 0/L0 or root level index page 132; Since the claim does not define ‘initial node’, it is valid to interpret it as the root node]) using the tree (Hyland, [0044 – In Fig. 6, data structure 144 is based on a tree structure such as binary search tree]);
searching for the unused node from the initial node (Hyland, [0059 - Fig. 10 shows the search for new unoccupied nodes when inserting a new element]; [0061 - Fig. 11 commences with stage 111, where the ‘current’ node, that is to say the node in respect of which operations are being performed, is set to the root/initial node; Here, the tree already exists. There are no dynamic additions or deletions of nodes]) using a list indicating an address order of the plurality of virtual areas comprised in the process address space (Hyland, [0013 – lookup memory available/process address space]; [0041 - Fig. 6 shows an array 60 of hardware memory locations, each defined by a multiple binary word. The array 60/list of memory locations is organized as a binary tree 61 from a root node 62. The tree 61 has nodes corresponding to the addresses in array 60 and except for the leaf nodes at the lowest level, each node has two child nodes of which the addresses can be computed from their parent node, thereby implying a list indicating an address order of virtual areas/nodes]; [0043 - In Fig. 7, tree 71 has a predetermined structure such that for each level/depth, each node has two child nodes of which the right node has an address greater than the address of the left node and each is computable from the address of the parent node]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the search of Hyland into the memory mapping method of Kwon, Clements, Edwards for the benefit of the using the binary search tree as it offers a convenient and deterministic minimal search latency because every memory address is associated with a single MAC address and the search algorithm has a fixed worse case value fixed by the size of the look-up memory available (Hyland, 0013).
As per Claim 6, the rejection of claim 1 is incorporated, and Kwon, Clements, Edwards, Hyland disclose,
wherein the data comprises one or more tensors (Edwards, [0100 - In Fig. 1, API 108 receives as input a layout of one or more tensors to be used to perform one or more image-to-column transformations]; [0070 - API 108 includes functions to generate more than one type of tensor descriptor, e.g., a first function to generate a tensor descriptor to be used with a tiled tensor mapping, and a second function to generate a tensor descriptor to be used with an image-to-column tensor mapping]; [0079 – In Fig. 2, inputs to tensor map API 240 include a location to store a generated tensor map data structure, a tensor data type, a tensor rank, a global address, global tensor dimensions, global strides, box dimensions, element strides, an interleave data structure, a swizzle data structure, an L2 promotion data structure, an out of bounds fill data structure, and/or other suitable inputs]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tensors of Edwards into the memory mapping method of Kwon, Clements, Hyland for the benefit of including one or more tensor cores in processing cores. The tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing (Edwards, 0491).
As per Claim 7, the rejection of claim 1 is incorporated, and Kwon discloses,
wherein the plurality of virtual areas (Kwon, [Claim 10 - Mapping the newly allocated file page to a virtual area]) are managed by one or more groups (Kwon, [0172 - In Fig. 14, step S410, when an area to be mapped to operate a process exceeds an overall file offset, the number of file pages that are to be first allocated is calculated. In step S420, the file pages/virtual areas are allocated. And in step S430, the newly allocated file pages are newly appended to a file/group by being connected through a data structure of a file system/process address space]) in response to a grouping instruction (Kwon, [Fig. 14: MAP APPEND]) to group the plurality of virtual areas into the one or more groups (Kwon, [0172 – In Fig. 14, step S440, the newly allocated file pages are recognized as the file, and the existing mapping process of mapping a physical address and a virtual address of each allocated file page is performed]),
the plurality of virtual areas comprised in one of the one or more groups (Kwon, [0175 - In Fig. 15, referring to the first picture, a file page request/arbitrary instruction may be transmitted four times in total to the library buffer 510 when a size of a file page is 1 KB]) are concurrently processed with respect to an arbitrary instruction (Kwon, [0175 - Library buffer 510 does not access a kernel area of the nonvolatile main memory during a system call whenever the file page request command is received, but may perform only one system call for the file page request command four times, for example, a 4 KB-file page, thereby implying concurrent processing]).
As per Claim 8, the rejection of claim 1 is incorporated, and Kwon discloses,
receiving an unmapping instruction (Kwon, [Fig. 13: MAP_REPLACE; In Linux mmap can also be used with MAP_FIXED to replace/unmap the mapping]) to cancel mapping of data for a target virtual area in the process address space (Kwon, [0167 - When a special flag such as MAP_REPLACE is detected during the checking of the flag]);
in response to reception of the unmapping instruction (Kwon, [Fig. 13: MAP_REPLACE; In Linux mmap can also be used with MAP_FIXED to replace the mapping]), marking another use node in the tree as another unused node (Kwon, [Fig. 13: step S390, No, thereby implying marking another use node as an unused node]);
unmapping data for the target virtual area (Kwon, [Fig. 13: step S330, Delete virtual area. In step S340, a virtual area is re-allocated, implying old data is unmapped and the newly allocated virtual area is clean. In step S350, the virtual area is re-inserted into the red-black tree to be managed, thereby implying that the virtual area corresponds to the unused node in the process address space]),
wherein the tree manages the other unused node to reuse in future (Kwon, [0166 - In Fig. 13, step S360, a virtual address of the virtual area may be mapped to a physical address of a file page which the process desires to access, thereby implying that the unused node is ready to reuse for future use]).
As per Claim 9, the rejection of claim 1 is incorporated, and Kwon discloses,
when executed by one or more processors (Kwon, [0068 – In Fig. 1, processor 200 may be a single core processor, or a multi-core processor. For example, the processor 200 may be a dual core processor, a quad-core processor, or a hexa-core processor]),
As per Claim 10, Kwon discloses a processor-implemented method (Kwon, [Fig. 1: Processor 200]; [0005 - A memory management method of an operating system for a nonvolatile main memory system, and provide a memory mapping method that enables an application program to quickly access a file through memory mapping]) comprising:
receiving (Kwon, [0056 – In Fig. 1, NVM controller 100 communicates with the processor 200 through a processor channel to receive a command]) an unmapping instruction (Kwon, [Fig. 13: MAP_REPLACE; In Linux mmap can also be used with MAP_FIXED to replace/unmap the mapping]) to cancel mapping of data for a target virtual area of a plurality of virtual areas in a process address space (Kwon, [Fig. 15]; [0115 - The user area 310 is a space of a memory accessed by the user by using an application and includes user buffer 315 and library buffer 314; Here the virtual area associated with user buffer 315 can be unmapped]; [0167 - When a special flag such as MAP_REPLACE is detected during the checking of the flag]) allocated for a deep learning application (Kwon, [0005 - Provide a memory mapping method that enables an application program to quickly access a file/virtual area through memory mapping; Since Fig. 1, Para-0068 recites a multi-core processor which can be used for deep learning, mainly for data preprocessing, data loading, and small-scale training, the ‘application’ is equivalent to a deep learning application]),
the process address space comprising a plurality of virtual areas (Kwon, [0066 - The page map table is formed in units of pages/virtual areas, and converts a logical address number/LAN into a physical page number/PPN]; [0067 - When data is stored in units of pages, each page may be referred to as a file page])
determining, in response to the unmapping instruction (Kwon, [Fig. 13: MAP_REPLACE; In Linux mmap can also be used with MAP_FIXED to replace the mapping]), whether a use node corresponding to the target virtual area (Kwon, [Fig. 15]; [0057 - A memory-based file system/process address space resides in a memory space of the kernel area]) exists in the tree by searching the tree for the use node (Kwon, [0167 – In Fig. 13, step S370, a virtual area corresponding to the allocated virtual address of the process is searched in the red-black tree. After steps S370, S380, which determine that the virtual area characteristics is valid, in step S390, it is determined whether the virtual area may be re-used? No]);
marking the use node in the tree corresponding to the target virtual area as an unused node without deleting the use node from the tree and preserving a structure of the tree (Kwon, [Fig. 13: step S390, No, thereby implying marking the use node as an unused node]), so that rebalancing ([See 112(a)]) due to addition or deletion of a node is prevented and overhead in memory allocation is reduced (Kwon, [0168 - In Fig. 13, since an overhead of deleting, allocating, and re-arranging a virtual area in the tree is reduced, a response speed of a memory system is increased]),
unmapping data from the target virtual area corresponding to the unused node in the process address space and the unused node remaining in the tree for future reuse (Kwon, [Fig. 13: step S330, Delete/unmap virtual area]; [0166 - In Fig. 3, step S330, the virtual area that is being used may be deleted in the red-black tree]),
wherein the tree manages the unused node to reuse in future (Kwon, [0168 – In Fig. 13, an overhead of deleting, allocating, and re-arranging a virtual area in the tree is reduced, thereby implying that the unused node is ready to reuse for future use]),
Clements clarifies the process address space,
setting a read lock enabling a read operation to the tree (Clements, [Pg. 200, Col. 2, Sec. 2, Para-2 - fine-grained lock; The fine-grained lock can be a read lock when traversing the BST]; [Gorman, Sec. 4.3: Process Space Descriptor - mmap_sem - This is a long lived lock which protects the VMA list for readers and writers]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the scalable address space of Clements into the memory mapping method of Kwon, to enable parallelism by an RCU-based binary balanced tree for storing memory mappings (Clements, Pg. 199, Abstract).
Gorman discloses the Linux Process Address Space and mapping data into the red-black tree with mremap system call and mmap_sem as the read lock.
Kwon discloses a multi-core processor executing an application. It is well-known that a multi-core processor can be used for deep learning. Since GPUs are preferred for heavy model training due to their massive parallelization,
Edwards further clarifies,
receiving an umapping instruction (Edwards, [0594 - cudaFree(d_A); CUDA calls to free memory for vector A are migrated to corresponding DPC++ calls]) to cancel mapping of data for a target virtual area (Edwards, [0260 - The CUDA Runtime API function cudaFree() releases or frees the memory space on the GPU device that was previously allocated by functions like cudaMalloc()]) in a process address space allocated (Edwards, [Fig. 35: application effective address space 3582+OS virtual address space 3585]; [0397 - An application effective address space 3582 within system memory 3514 stores process elements 3583]; [0095 – In Fig. 1, an API to cause information to be stored in a plurality of storage locations allocated to a first GPU]) for a deep learning application (Edwards, [0519 - In Fig. 50, application 5000 is an AI/ML application implemented using a deep learning framework such as MXNet, PyTorch, or TensorFlow]; [Figs. 43-54C]),
the process address space (Edwards, [0400 - MMU 3539 includes segment/page walk circuitry for accessing segment/page tables 3586 within OS virtual address space 3585]) comprising a plurality of virtual areas (Edwards, [0432 - Each processing cluster 3894 includes an MMU 3845 that is configured to map virtual addresses/virtual areas into physical addresses. MMU 3845 includes a set of page table entries/PTEs used to map a virtual address to a physical address of a tile and a cache line index]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the deep learning application of Edwards into the memory mapping method of Kwon, Clements for the benefit of including one or more tensor cores in processing cores. The tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing (Edwards, 0491).
Hyland clarifies,
marking the use node in the tree as an unused node without deleting the use node from the tree and preserving a structure of the tree (Hyland, [0043 – In Fig. 7, tree 71 has a predetermined structure such that for each level, each node has two child nodes, thereby implying that the tree is balanced from the beginning]; [0045 - If the tree is structured/balanced as shown in Fig. 7 then Fig. 8 is used when searching for an element]; [Fig. 8: step 82, Element found, thereby implying that the use node which is the search element is found in the tree]), so that rebalancing due to addition or deletion of a node is prevented and overhead in memory allocation is reduced (Hyland, [0035 - Fig. 2 represents a balanced BST which is structured in software]; [0037 - It is desirable to achieve a balanced tree in order to minimize the number of operations required to achieve a match between the keys and the address data in the entry, thereby implying that rebalancing is prevented]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the balanced BST of Hyland into the memory mapping method of Kwon, Clements, Edwards for the benefit of the BST staying balanced with the same depth of tree both to the left and to the right of the root node (Hyland, Para-0039).
The remaining limitations are similar to claims 1, 8 and therefore the same mappings are incorporated.
As per Claim 12, it is similar to claim 3 and therefore the same mappings are incorporated.
As per Claim 15, it is similar to claim 6 and therefore the same mappings are incorporated.
As per Claim 16, it is similar to claim 7 and therefore the same mappings are incorporated.
As per Claim 17, Kwon discloses an electronic device (Kwon, [0054 – As per Fig. 1, system 10 includes processor 200, memory system 11, and secondary storage apparatus 400. System 10 may be included in a terminal such as a desktop or laptop. Also, the system 10 may be a mobile system]) comprising:
one or more processors (Kwon, [0056 – In Fig. 1, NVM controller 100 communicates with processor 200];
a memory comprising one or more non-transitory storage media (Kwon, [0055 – In Fig. 1, memory system 11 includes a nonvolatile memory controller 100 and at least one nonvolatile main memory 300. The nonvolatile main memory 300 may be a semiconductor flash main memory such as a NAND memory chip or a NOR memory chip]) that store instructions that, when executed by the one or more processors (Kwon, [0056 – In Fig. 1, the nonvolatile memory controller 100 communicates with the processor 200 through a processor channel to receive a command and an address and to transmit/receive data]), configures the electronic device to:
The remaining limitations are similar to claim 1 and therefore the same mappings are incorporated.
Claims 4, 13-14, 19-20 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kwon et al (20150193354) in view of Clements et al (‘Scalable Address Spaces Using RCU Balanced Trees’, ACM, 2012, Pgs. 199-210), as evidenced by (Gorman, Jan 2023 version, Chapter 4: Process Address Space), in further view of Edwards et al (20240168830), Hyland et al (20030009474) and Majnemer et al (20140074841).
As per Claim 4, the rejection of claim 1 is incorporated, and Kwon, Clements, Edwards, Hyland disclose marking of the unused node to the use node.
Majnemer further discloses,
setting a lock enabling a read operation to the tree (Majnemer, [0028 - Before reading data, an operation upon a B-tree can acquire a read lock]; [0022 - At a basic level, a B-tree operates like a binary-search tree/BST]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the read lock of Majnemer into the memory mapping method of Kwon, Clements, Edwards, Hyland for the benefit managing a complex hierarchical file system such as the B-tree data structure, wherein for implementing the file system operations such as acquiring an exclusive lock are performed (Majnemer, 0004-0005).
As per Claim 13, the rejection of claim 10 is incorporated, and Kwon, Clements, Edwards, Hyland disclose searching the BST.
Majnamer discloses,
setting a lock enabling a read operation to the tree (Majnemer, [0028 - Before reading data, an operation upon a B-tree can acquire a read lock]; [0022 - At a basic level, a B-tree operates like a binary-search tree/BST]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the read lock of Majnemer into the memory mapping method of Kwon, Clements, Edwards, Hyland for the benefit managing a complex hierarchical file system such as the B-tree data structure, wherein for implementing the file system operations such as acquiring an exclusive lock are performed (Majnemer, 0004-0005).
Hyland further discloses,
determining whether a depth of the use node (Hyland, [Fig. 11: after step 111, at step 112-currentElement==0? No, step 113-currentNode==lastNodeAtLevel? No, step 114-currentLevel==0? Yes, thereby determining depth of searched use node]; [0004 - If a BST has L levels the root node is the only node to be a member of level L, the uppermost level. A full binary tree with L levels has (2^L)−1 nodes; Note: The depth of a node is the number of edges present in the path from the root node of a tree to that node]) searched (Hyland, [0059 - The search commences at the root node 101, then proceeds along the next level (L−1) for nodes 102 and 103, then proceeds along the next level (L−2) to nodes 104 to 105 and so on to the next level of which the first node is 106 and the last node of the level is 107]) in the tree exceeds a threshold depth (Hyland, [0009 - For a given number of nodes there is an associated minimum tree depth/threshold that yields maximally efficient searches for any given element of that tree; Note: the depth of a node in a binary tree is also its level. Both terms describe the number of edges on the path from the root node to the given node]);
in response to the depth of the searched use node not exceeding the threshold depth (Hyland, [Fig. 11: step 114-currentLevel==0? Yes, step 115-noFreeSpace]), marking the use node as an unused node (Hyland, [0064 – In Fig. 11, if the current level/depth is zero as determined by step 114, there is no free space, as indicated by step 115. The algorithm has reached node 109 as shown in Fig. 10, thereby marking the use node as an unused node]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the balanced BST of Hyland into the memory mapping method of Kwon, Clements, Edwards, Majnemer for the benefit of using the balanced BST because every new element is inserted at the highest available node in the hierarchy of the tree. Thus for a full tree of L levels or depth there is a worst case of L possible comparisons before the search element can be located (Hyland, 0012).
As per Claim 14, the rejection of claim 13 is incorporated, and Kwon, Edwards, Clements, Hyland, Majnemer further disclose,
as the threshold depth (Hyland, [0009 - For a given number of nodes there is an associated minimum tree depth/threshold that yields maximally efficient searches for any given element of that tree; Since the claim does not define ‘threshold depth’, the citation is a valid interpretation]) increases, a number of unused nodes comprised in the tree increases (Hyland, [0039 - Unbalance occurs owing to the fact that the entries have to be compiled in an uncontrolled order. This is shown in Fig. 3. The root node is established first and contains the element 90. Thus it is seen that the number of nodes and the depth of the tree is greater on the left-hand side of Fig. 3 than the right-hand side, thereby implying that as the threshold depth increases, the number of unused nodes increases]),
and as the threshold depth decreases, a number of unused nodes comprised in the tree decreases (Hyland, [0040 – In Fig. 5, a shuffling operation is performed, wherein node 41 becomes the root node and node 40 a child of the root node. The new element ‘2’ is put into node 43 and the tree is balanced, thereby implying that a decreased threshold depth decreases the number of unused nodes]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the balanced BST of Hyland into the memory mapping method of Kwon, Clements, Edwards, Majnemer for the benefit of using the balanced BST because every new element is inserted at the highest available node in the hierarchy of the tree. Thus for a full tree of L levels or depth there is a worst case of L possible comparisons before the search element can be located (Hyland, 0012).
As per Claim 19, it is similar to claim 4 and therefore the same mappings are incorporated.
As per Claim 20, the rejection of claim 19 is incorporated, and Kwon, Clements, Edwards, Hyland, Majnemer disclose,
searching for an initial node (Hyland, [0032 - Fig. 3: The index node 120 is a root node]; [0040 - In Fig. 4, the data structure is implemented as a tree structure and includes a Level 0 or root level index page 132, a Level 1 index page 134, and a Level 2 data page 136]; [0041 - A traversal/search begins at the Level 0/L0 or root level index page 132; Since the claim does not define ‘initial node’, it is valid to interpret it as the root node]) using the tree (Hyland, [0044 – In Fig. 6, data structure 144 is based on a tree structure such as binary search tree]);
searching for the unused node from the initial node (Hyland, [0059 - Fig. 10 shows the search for new unoccupied nodes when inserting a new element]; [0061 - Fig. 11 commences with stage 111, where the ‘current’ node, that is to say the node in respect of which operations are being performed, is set to the root/initial node; Here, the tree already exists. There are no dynamic additions or deletions of nodes]) using a list indicating an address order of the plurality of virtual areas comprised in the process address space (Hyland, [0013 – lookup memory available/process address space]; [0041 - Fig. 6 shows an array 60 of hardware memory locations, each defined by a multiple binary word. The array 60/list of memory locations is organized as a binary tree 61 from a root node 62. The tree 61 has nodes corresponding to the addresses in array 60 and except for the leaf nodes at the lowest level, each node has two child nodes of which the addresses can be computed from their parent node, thereby implying a list indicating an address order of virtual areas/nodes]; [0043 - In Fig. 7, tree 71 has a predetermined structure such that for each level/depth, each node has two child nodes of which the right node has an address greater than the address of the left node and each is computable from the address of the parent node]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the search of Hyland into the memory mapping method of Kwon, Clements, Edwards, Majnemer for the benefit of the using the binary search tree as it offers a convenient and deterministic minimal search latency because every memory address is associated with a single MAC address and the search algorithm has a fixed worse case value fixed by the size of the look-up memory available (Hyland, 0013).
Response to Arguments
The Applicant's arguments filed on June 24, 2026 have been fully considered, but they are not persuasive.
Applicant argues,‘The use/unused state is recorded and read is supported by the structure managing each virtual area (e.g., a Linux vm_area_struct) "may include various flags indicating properties of the virtual area as members" [0141]….’ (Rem, Pg. 8)
Response: The Linux vm_area_struct is a standard OS data structure, well known in the art. And the spec summarizes what is already known (e.g. process address space, VMA, mm_struct, mm_map, red-black tree, flags etc.). See Linux Kernel Documentation. A PHOSITA cannot just ‘know’ the inventor's unique implementation details from a passing reference to standard kernel constructs in the spec.
Merely naming standard kernel structures (vm_area_struct, mm_struct, red-black tree etc.) alongside flags (VM_GROUP etc.) amounts to a ‘research plan’ or functional result rather than an operable teaching. Reciting standard background technology demonstrates possession of existing open-source code, not possession of a novel invention. Referencing standard flags or data structures off-the-shelf without linking them to a specific structural or functional improvement fails the test of conveying that the applicant actually invented the ‘improvement’.
The spec fails to detail the specific algorithm(s), parameters, and logic used to achieve the memory mapping and tree balancing.
Applicant further argues:‘Taken together, the specification discloses with ….determination of whether an unused node exists is accomplished by searching the tree,….by traversing the tree from an initial node along the connection list’. (Rem, Pg. 8)
Response: This argument is incorrect.
There is no disclosure of how the ‘connection list’ is built.
Para-0064 of the spec recites a one-line statement such as, ‘the connection list may represent an address order of the plurality of virtual areas included in the process address space’. But the spec does not disclose how to generate ‘an address order of the plurality of virtual areas included in the process address space’. The spec provides no starting criteria, sorting rules, updating logic or algorithmic details for the list. Simply reciting a vague, one-line statement to build a ‘connection list’ that indicates an address order of virtual areas, does not convey structural possession. It does not fulfill the written description requirement.
Applicant further argues: ‘,….a lack of support for mapping/unmapping tensors and would require undue experimentation……..tensors are ….a data type known to a person with ordinary skill in the deep learning art. ([0146] describing mapping of 1064 tensors in a Swin-Transformer application and [0053] referencing a tensor processing unit (TPU))’. (Rem, Pg. 9)
Response: This argument is incorrect.
The spec being a high-level, general document, relies on one to two-line statements to recite features but offers no details. Sprinkling a few AI buzzwords is insufficient to support a broad, functionally defined genus of AI. The spec must define the boundaries through specific algorithms, training methods, and distinct architectural interactions.
The spec must demonstrate ‘possession’ of the invention, rather than rely on the knowledge of the PHOSITA to fill in the gaps.
The spec does not disclose how a non-trivial data structure such as tensors/multi-dimensional arrays are mapped/unmapped into the process address space comprising virtual areas of a deep learning application.
The generic limitation ‘receiving a mapping instruction to map data onto a process address space for a deep learning application’, where data represents tensors, is stated at a purely functional, result-oriented level without disclosing the necessary structural, algorithmic, or technical implementation details (such as tensor formatting, address space coordination, memory management etc.). The same is true of the limitation, ‘receiving a unmapping instruction to map data….’.
The spec merely restates the claim's desired outcome and broad terminology without providing structural or algorithmic context (e.g., how the mapping/unmapping instruction parameters are generated, how tensor dimensions align with the process space, or how the deep learning framework interacts with the mapping etc.). Therefore the disclosure is not enabling for the full scope of the claim.
The spec does not explicitly disclose the name of the unmapping instruction. Claiming a generic ‘unmapping instruction’ while leaving all implementation details blank, amounts to an unearned monopoly over any instruction and method that achieves tensor mapping via memory operations. Please see the 112(a).
Regarding the ‘Swin Transform application’, the spec does not even define it. Naming a modern machine learning architecture like a Swin-Transform without details does not prove the inventor possessed the specific mapping method. Therefore how the 1,064 tensors map onto a Swin-Transform application forces the PHOSITA to guess, engage in experimentation or do excessive research.
Though spec Fig. 11, Para-0146 recites, ‘even if 1064 tensors are mapped onto respective virtual areas’, there is no written description of the actual mapping/binding between the muti-dimensional arrays and virtual areas. Though searching the BST is a key feature of the disclosure, neither the claims nor the spec recite how to search the tree for nodes mapped/unmapped to multi-dimensional arrays. Therefore the spec does not enable a mapping/unmapping instruction to map/unmap tensors onto a process address space for a deep learning application.
Casually mentioning a TPU as a black-box component without explaining how the TPU is integrated, or interfaced with the rest of the system, leaves undue experimentation for a person of ordinary skill in the art. The spec fails to disclose the corresponding specific structure or algorithm tied to the TPU. Merely mentioning AI hardware buzzwords like ‘TPU’ does not transform a functional result (‘perform an operation according to a neural network’) into a concrete, technologically detailed solution.
Simply pointing a generic, off-the-shelf machine learning model or TPU as a new field of use is an abstract idea, not an improvement to computer functionality or technology.
Applicant further argues:‘Accordingly, the present claims recite features that reflect an improvement….a computer, or an improvement….technical field, and therefore the claimed features are integrated into a practical application, and therefore the claims are not "directed to" an abstract idea, and….claims recite patent-eligible subject matter’. (Rem, Pg. 13)
Response: This argument is incorrect.
The claims focus on a BST, and searching the BST in a process address space and its virtual areas. The BST is well-known in graph theory and searching the BDT is found in a college textbook. And managing the process address space via virtual areas is also well understood.
Though the claims recite ‘deep learning application’, the spec does not recite a concrete underlying hardware implementation. Based on Recentive Analytics v. Fox (2025), training a deep learning model without specific improvements to the model architecture or hardware utilization, is deemed patent-ineligible.
The claims recite a ‘deep learning application’ at a high level of generality without explaining how it integrates into a specific technical solution.
The BST, the tree locking, the node searching, marking etc., are software. The claims are directed to an abstract idea of ‘mapping’ data into virtual areas of a BST, without providing a specific, unconventional, a detailed algorithm or hardware configuration for achieving the ‘mapping’. Though deep learning is very hardware intensive, the hardware is recited at a high level or acts merely as a generic tool. The software is not meaningfully integrated with the hardware to improve technology. In other words, the ‘integration’ between the software and the hardware is missing. Hence the claims are directed to the abstract idea on a generic computer.
Applicant further argues:‘….claim 1 sets forth: A processor-implemented method comprising: receiving a mapping instruction to map target data onto a process address space for a deep learning application,….’ (Rem, Pg. 13)
Response: The claims do not align with the spec. There are several issues.
Please see the 112(a)’s and 112(b)’s.
Applicant further argues:‘In Kwon, there is no discussion of an unused node that has no corresponding virtual area and marking the unused node as a use node’. (Rem, Pg. 15)
Response: This argument is incorrect.
In Para-0006, the spec recites, ‘The tree may manage the process address space using a plurality of use nodes….and one or more unused nodes that do not correspond to the plurality of virtual areas’.
The spec provides a mere functional result (‘do not correspond’) without detailing how the unused nodes are configured, structured, or maintained in the BST such that they do not correspond to the virtual areas. There is no disclosure of a mapping table that tracks the dynamic relationship between the used and unused nodes and the virtual areas.
The spec fails to detail the operational mechanism or structural relationship of the used nodes and unused nodes in relation to the process address space. Please see the 112(a).
That being said, Kwon, Fig. 13, Para-0133 recites, ‘When it is determined in operation S320 that the virtual area is being used, the method proceeds to operation S330. In operation S330, the virtual area that is being used may be deleted in the red-black tree (implying unused node not corresponding to a virtual area). Next, in operation S340, a virtual area is re-allocated. In operation S350, the virtual area may be re-inserted into the red-black tree to be managed (implying marking unused node to used). In operation S360, a virtual address of the virtual area may be mapped to a physical address of a file page which the process desires to access’.
The spec relies on 1-2 lines to disclose the above requirement. No details are provided.
As shown in Fig. 6, the spec does not disclose the details of the search for the unused node. The spec does not explicitly disclose how an unused node that has no corresponding virtual area is determined so that the marking of the unused node as a use node is accomplished. Hence it is valid to interpret that the combination of Kwon,Edwards,Hyland disclose the above requirement. Please see O/A.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/ Primary Examiner, Art Unit 2132
Prosecution Insights