DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to Applicant’s communication filed on 01/02/2026 Claims 1-20 have been examined.
Response to Arguments
Applicant’s arguments with respect to claim 1,11,17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 - 10 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claims 1,4,5,7,8, the claim recites “the associated memory circuit”. It unclear what the associated memory circuit is referring to because claim 1 recites “ a memory interface circuit”,” first memory access circuit” and second memory access circuit. It is unclear if the associated memory circuit refers to the memory interface circuit or memory access circuit. Therefore, the examiner is unable to determine the metes and bounds of the claim language. For the purpose of examination, the examiner will interpret the associated memory circuit to refer to the first or the second memory access circuit.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,11,12,13,17,19,20 are rejected under 35 U.S.C. 102 (a1) as being anticipated by Griffy et al. Publication No. US 2022/0413886 A1 ( Griffy hereinafter)
Regarding claim 1,
Griffy teaches a memory interface circuit (Fig.1), comprising:
a secure interface configured to couple to a secure processor ( ¶0005 - FIG. 1B illustrates a block diagram of a computer system including a plurality of sockets having an encryption circuit according to embodiments of the disclosure – ¶ 0056 - . encryption circuit is separate from a processor core, for example, as an offload circuit controlled by a command sent from processor core, e.g., encryption circuit 114 separate from any cores and encryption circuit 134 separate from any cores)
a first memory access circuit associated with a first memory circuit and a second memory access circuit associated with a second memory circuit , wherein the first memory access circuit and the second memory access circuit each comprise (¶ 0051 - FIG. 1B illustrates a block diagram of a computer system 100 including a plurality of sockets 102, 122 having an encryption circuit (114, 134, respectively) according to embodiments of the disclosure. Computer system 100A and/or computer system 100B of FIG. 1A may be an instance of computer system 100 in FIG. 1B – ¶ 0052 - Although two sockets are shown, a single socket or any plurality of sockets may be utilized. In FIG. 1, socket_0 102 includes a core_0 104 and socket 122 includes a core_0 124. A core may be any hardware processor core, e.g., as an instance of core 1690 in FIG. 16B. Although multiple cores are shown, each socket may have a single or any plurality of cores ( e.g., where N is any positive integer greater than 1 ). Each socket may have an identification value, e.g., "socket ID" )
a multi-bus interface configured to couple to a plurality of processing circuits via system interfaces; a memory interface configured to couple to the associated memory circuit ( ¶ 0057 - Memory controller circuit 116 of socket 102 may receive an address for a memory access request, e.g., and for a store request also receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 120, e.g., via one or more memory buses 118)
an encrypt/decrypt circuit (¶ 0005 - FIG. 1B illustrates a block diagram of a computer system including a plurality of sockets having an encryption circuit according to embodiments of the disclosure – ¶ 0047 - an encryption circuit
includes decryption circuitry in certain embodiments. Embodiments herein use encryption circuitry/modes disclosed herein (e.g., and RDMA circuitry) to free up the hardware processor cores ( e.g., CPUs) to perform other tasks and is also faster overall than hardware processor cores).
wherein the first memory access circuit and the second memory access circuit are each configured to: encrypt data stored in the associated memory circuit in response to a memory write transactions from the plurality of processing circuits ( ¶0049 - each of the computer systems includes a memory controller circuit 116 to control memory access (e.g., reads and/or writes), for example, with socket 102A including memory controller circuit 116A (e.g., for memory accesses to memory 120A and/or any other memory of computer system 100A) and socket 102B including memory controller circuit 116B (e.g., for memory accesses to memory 120B and/or any other memory of computer system 100B) – ¶ 0054 - Memory access (e.g., store or load) request may be generated by a core, e.g., a memory access request may be generated by execution circuit 108 of core 104 (e.g., caused by the execution of an instruction) and/or a memory access
request may be generated by execution circuit 128 of core 124 (e.g., caused by the execution of an instruction) – ¶0056 - Encryption circuit 114 of socket 102 may receive a memory access request from one or more of its cores ( e.g., from address generation unit 110 of execution circuit 108) and/or encryption circuit 134 of socket 122 may receive a memory access ( e.g., store) request from one or more of its cores ( e.g., from address generation unit 130 of execution circuit 128). Encryption circuit may, e.g., for an input of a destination address and text to be encrypted (e.g., plaintext) (e.g., and a key), perform an encryption to generate a ciphertext (e.g., encrypted data)) ;
decrypt encrypted data read from the associated memory circuit in response to memory read transactions from the plurality of processing circuits (¶ 0056 – An encryption circuit may perform a decryption operation, e.g., for a memory load request. – ¶ 0048 -total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext – ¶ 0043 - Then, on the new host, the hardware processor core ( e.g., CPU) is again used for decryption – ¶ 0054 - Memory access (e.g., store or load) request may be generated by a core, e.g., a memory access request may be generated by execution circuit 108 of core 104 (e.g., caused by the execution of an instruction) and/or a memory access request may be generated by execution circuit 128 of core 124 (e.g., caused by the execution of an instruction – ¶ 0047 -Although the term encryption is used throughout, it should be understood that decryption is also achievable according to the embodiments herein, e.g., an encryption circuit includes decryption circuitry in certain embodiments ).
re-encrypt first data in a first encrypted data block stored in the associated memory circuit, the re-encrypt comprising: setting secure key register values based on data received via the secure interface from the secure processor, wherein the secure key register values comprise a first key and a second key of the respective memory access circuit ( ¶ 0079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments- ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose – Table 2, ¶ 0064 - . MKTME encryption circuit maintains an internal key table not accessible by software to store the information (e.g., key and encryption mode) associated with each Key ID (e.g., a corresponding Key ID for a corresponding encrypted memory block/page) (for example, where a key ID is incorporated into the physical address, e.g., in the p age tables, and also in every other storage location such as the caches and TLB – See Also ¶ 0081).
reading the first encrypted data block comprising a first number of cache lines from the associated memory circuit (¶ 0048-total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext. ) ;
decrypting, in the encrypt/decrypt circuit with first key, the first encrypted data to recover the first data (¶ 0056 -An encryption circuit may perform a decryption operation, e.g., for a memory load request. – ¶ 0048 – total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext – ¶ 0103 -Exemplary architectures, systems, etc. that the above may be used in are detailed below. Exemplary instruction formats that may cause a configuration, a decryption, an encryption, a read (e.g., and a decryption), and/or a write (e.g., and an encryption) are );
encrypting, in the encrypt/decrypt circuit with a second key the first data to generate a second encrypted data block comprising the first number of cache lines (¶ 00079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments.- ¶ 0056 - Encryption circuit may, e.g., for an input of a destination address and text to be encrypted (e.g., plaintext) (e.g., and a key), perform an encryption to generate a ciphertext (e.g., encrypted data). The ciphertext may then be stored in storage, e.g., in memory 120 and/or memory 140. An encryption circuit may perform a decryption operation, e.g., for a memory load request. ); and
writing the second encrypted data block to the associated memory circuit (¶ 0102 - The operations 1200 further include, at block 1208, storing the encrypted code and data of the virtual machine within a migration buffer of the memory of the first computer system by a direct memory access engine circuit of the first computer system - ¶ 0057 -Memory controller circuit 136 of socket 122 may receive an address for a memory access request, e.g., and for a store request also
receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 140, e.g., via one or more memory buses 138 – See Also ¶ 0081) .
Regarding claim 11,
Griffy teaches a processor-based system comprising:
at least one processing circuit; a plurality of memory circuits; and a plurality of memory interface circuits, each memory interface circuit of the plurality of memory interface circuits, comprising; an encrypt/decrypt circuit; a re-encryption circuit comprising: a first interface configured to couple to the at least one processing circuit; and a second interface configured to couple to an associated memory circuit of the plurality of memory circuit; wherein the memory interface circuit is configured to( ¶ 0005 - FIG. 1B illustrates a block diagram of a computer system including a plurality of sockets having an encryption circuit according to embodiments of the disclosure – ¶ 0056 - . encryption circuit is separate from a processor core, for example, as an offload circuit controlled by a command sent from processor core, e.g., encryption circuit 114 separate from any cores and encryption circuit 134 separate from any cores -¶ 0051 - FIG. 1B illustrates a block diagram of a computer system 100 including a plurality of sockets 102, 122 having an encryption circuit (114, 134, respectively) according to embodiments of the disclosure. Computer system 100A and/or computer system 100B of FIG. 1A may be an instance of computer system 100 in FIG. 1B – ¶ 0052 - Although two sockets are shown, a single socket or any plurality of sockets may be utilized. In FIG. 1, socket_0 102 includes a core_0 104 and socket 122 includes a core_0 124. A core may be any hardware processor core, e.g., as an instance of core 1690 in FIG. 16B. Although multiple cores are shown, each socket may have a single or any plurality of cores ( e.g., where N is any positive integer greater than 1 ). Each socket may have an identification value, e.g., "socket ID" -¶ 0057 - Memory controller circuit 116 of socket 102 may receive an address for a memory access request, e.g., and for a store request also receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 120, e.g., via one or more memory buses 118)
encrypt data stored in the associated memory circuit in response to a memory write transaction from the at least one processing circuit ( ¶0049 - each of the computer systems includes a memory controller circuit 116 to control memory access (e.g., reads and/or writes), for example, with socket 102A including memory controller circuit 116A (e.g., for memory accesses to memory 120A and/or any other memory of computer system 100A) and socket 102B including memory controller circuit 116B (e.g., for memory accesses to memory 120B and/or any other memory of computer system 100B) – ¶ 0054 - Memory access (e.g., store or load) request may be generated by a core, e.g., a memory access request may be generated by execution circuit 108 of core 104 (e.g., caused by the execution of an instruction) and/or a memory access request may be generated by execution circuit 128 of core 124 (e.g., caused by the execution of an instruction) – ¶0056 - Encryption circuit 114 of socket 102 may receive a memory access request from one or more of its cores ( e.g., from address generation unit 110 of execution circuit 108) and/or encryption circuit 134 of socket 122 may receive a memory access ( e.g., store) request from one or more of its cores ( e.g., from address generation unit 130 of execution circuit 128). Encryption circuit may, e.g., for an input of a destination address and text to be encrypted (e.g., plaintext) (e.g., and a key), perform an encryption to generate a ciphertext (e.g., encrypted data));
decrypt encrypted data read from the associated memory circuit in response to a memory read transaction from the at least one processing circuit(¶ 0056 – An encryption circuit may perform a decryption operation, e.g., for a memory load request. – ¶ 0048 -total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext – ¶ 0043 - Then, on the new host, the hardware processor core ( e.g., CPU) is again used for decryption – ¶ 0054 - Memory access (e.g., store or load) request may be generated by a core, e.g., a memory access request may be generated by execution circuit 108 of core 104 (e.g., caused by the execution of an instruction) and/or a memory access request may be generated by execution circuit 128 of core 124 (e.g., caused by the execution of an instruction – ¶ 0047 -Although the term encryption is used throughout, it should be understood that decryption is also achievable according to the embodiments herein, e.g., an encryption circuit
includes decryption circuitry in certain embodiments );
and re-encrypt first data in a first encrypted data block stored in the associated memory circuit, the re-encrypt ( ¶ 0079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments- ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose – Table 2, ¶ 0064 - . MKTME encryption circuit maintains an internal key table not accessible by software to store the information (e.g., key and encryption mode) associated with each Key ID (e.g., a corresponding Key ID for a corresponding encrypted memory block/page) (for example, where a key ID is incorporated into the physical address, e.g., in the p age tables, and also in every other storage location such as the caches and TLB – See Also ¶ 0081)comprising:
reading the first encrypted data block comprising a first number of cache lines from the associated memory circuit(¶ 0048-total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext. ) ;
decrypting, in the encrypt/decrypt circuit, the first encrypted data block based on a first key to recover the first data(¶ 0056 -An encryption circuit may perform a decryption operation, e.g., for a memory load request. – ¶ 0048 – total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext – ¶ 0103 -Exemplary architectures, systems, etc. that the above may be used in are detailed below. Exemplary instruction formats that may cause a configuration, a decryption, an encryption, a read (e.g., and a decryption), and/or a write (e.g., and an encryption) are );
encrypting, in the encrypt/decrypt circuit, the first data based on a second key to generate a second encrypted data block comprising the first number of cache lines(¶ 00079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments.- ¶ 0056 - Encryption circuit may, e.g., for an input of a destination address and text to be encrypted (e.g., plaintext) (e.g., and a key), perform an encryption to generate a ciphertext (e.g., encrypted data). The ciphertext may then be stored in storage, e.g., in memory 120 and/or memory 140. An encryption circuit may perform a decryption operation, e.g., for a memory load request. ); and
writing the second encrypted data block to the memory circuit (¶ 0102 - The operations 1200 further include, at block 1208, storing the encrypted code and data of the virtual machine within a migration buffer of the memory of the first computer system by a direct memory access engine circuit of the first computer system - ¶ 0057 -Memory controller circuit 136 of socket 122 may receive an address for a memory access request, e.g., and for a store request also receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 140, e.g., via one or more memory buses 138 – See Also ¶ 0081) .
Regarding claim 12,
Griffy further teaches
each memory interface circuit further comprising: a secure processor; and a secure interface coupled to the secure processor and the memory interface circuit ( ¶ 0005 - FIG. 1B illustrates a block diagram of a computer system including a plurality of sockets having an encryption circuit according to embodiments of the disclosure – ¶ 0056 - . encryption circuit is separate from a processor core, for example, as an offload circuit controlled by a command sent from processor core, e.g., encryption circuit 114 separate from any cores and encryption circuit 134 separate from any cores)
wherein: the first encrypted data block comprises one of a plurality of encrypted data blocks in a configured range of memory addresses in the memory circuit (¶ 0039 -software manages the use of keys and can use each of the available keys for encrypting any section (e.g., page) of the memory. Thus, certain embodiments of MKTME allow page granular encryption of memory – ¶ 0091 -the VM's memory 602, 604 (e.g., page) (e.g., encrypted with the transfer key and stored into migration buffer 606) is then copied (e.g., as shown by arrow (2)) from the migration buffer 306 to the new host with RDMA. In contrast to FIG. 3, the example shown in FIG. 6 does not utilize a migration buffer in host 2 (e.g., in memory 120B), e.g., and instead copies the encrypted data into the desired place to start the VM on the new host. ) ;
and the memory interface circuit is further configured to start re-encrypting each block of the plurality of encrypted data blocks in response to a first configuration instruction received from the secure processor on the secure interface (¶ 0082 - . the encryption of (e.g., each block of) memory uses its physical address as the offset. To ensure that the same ciphertext can be decrypted on both HOST l and HOST2, memory must be transferred to the same physical address – ¶ 0063 - the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction 0 (e.g., when executed by a core) is used to execute functions – Table 2 – ¶ 151 – the PConfig instruction is used to set the parameters that the encryption circuit uses to begin processing the memory ranges).
Regarding claim 13,
Griffy further teaches
wherein the secure processor is configured to program a configuration register to indicate the configured range of memory addresses (¶ 0063- the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction – ¶ 0039 - software manages the use of keys and can use each of the available keys for encrypting any section (e.g., page) of the memory. Thus, certain embodiments of MKTME allow page granular encryption of memory. – ¶ 0083 - software sets up the migration buffer on HOST1 and HOST2 to use position independent encryption – ¶ 0053 - Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as
corresponding control/capabilities register(s) 126 of socket. control/capabilities
registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager
storage 142) that indicate the functionality that a corresponding encryption circuit is capable of – See Also ¶ 0081 & ¶ 0088).
Regarding claim 17,
Griffy teaches a method of a plurality of memory interface circuits to re-encrypt first data in a first encrypted data block in an associated memory circuit, the method comprising:
reading the first encrypted data block comprising a first number of cache lines from the associated memory circuit(¶ 0048-total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext. ) ;
decrypting the first encrypted data block based on a first key associated with the respective memory interface circuit obtained from a first secure key register of the respective memory interface circuit to recover the first data¶ 0048-total memory encryption (TME) encrypts memory coming out of a socket, for example, where the memory is then decrypted when it is retrieved, so that in the cache and registers, all data is in plaintext – ¶ 0079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key – ¶ 0064 - MKTME encryption circuit maintains an internal key table not accessible by software to store the information (e.g., key and encryption mode) associated with each KeyID – ¶ 0062 -encryption circuit 200 in decryption mode
(for example, in response to a request to decrypt, e.g., a decrypt data from storage request), receives as inputs a tweak value (e.g., from tweak circuit 204), encryption key 206, and ciphertext 212, and then generates the plaintext 208 therefrom. – See Also ¶ 0057) ;
encrypting the first data based on a second key associated with the respective memory interface circuit obtained from a second secure key register of the respective memory interface circuit to generate a second encrypted data block comprising the first number of cache lines(¶0079 - -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments –¶ 0064 - MKTME encryption circuit maintains an internal key table not accessible by software to store the information (e.g., key and encryption mode) associated with each KeyID- See Als ¶ 0056 – ¶ 0057 -Encryption circuit may, e.g., for an input of a destination address and text to be encrypted (e.g., plaintext) (e.g., and a key), perform an encryption to generate a ciphertext (e.g., encrypted data).. Memory controller circuit 116 of socket 102 may receive an address for a memory access request, e.g., and for a store request also receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 120, e.g., via one or more memory buses 118); and
writing the second encrypted data block to the associated memory circuit(¶ 0081 -set the Key ID for the migration buffer in first host 400A to use the "transfer" key, the host 400A performs a DMA (e.g., by memory controller circuit 416A)
to send the VM' s memory to the migration buffer in first host 400A, - See Also ¶ 0043) .
Regarding claim 19,
Griffy further teaches
re-encrypting a plurality of encrypted data blocks comprising the first encrypted data block ¶ 0048-Embodiments herein perform DMAs and RDMAs on memory that is encrypted with MK-TME to greatly improve the performance of live migrations while still remaining secure – ¶ 0039 certain embodiments of MK TME allow page granular encryption of memory. ¶ 0043 - the hardware processor core ( e.g., CPU) is involved in the encryption and/or decryption of VM data (e.g., and VM code) in certain embodiment, for example, where the hardware processor core (e.g., CPU) on the sending host (from where the VM is migrated from) encrypts the VM data ( e.g., and VM code) and the hardware processor core ( e.g., CPU) on the receiving host decrypts the VM data (e.g., and VM code) before storing it in memory and allowing execution to continue. – ¶0079Mapping
these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments. – See ¶0093 ).
Regarding claim 20,
Griffy further teaches
starting to re-encrypt the plurality of encrypted data blocks in the associated memory circuit in response to a start indication stored in the plurality of configuration registers associated with the respective memory interface circuit (¶0079 -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments – ¶ 0081 -the first host 400A (e.g., a hardware
processor (e.g., CPU 402A) of the host 400A) is to send an indication to the second host 400B that a live migration is to be performed. ¶ 0053 -control/capabilities
registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager
storage 142) that indicate the functionality that a corresponding encryption circuit is capable of. – ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose. In certain embodiments, PCONFIG instruction is a package scoped instruction, e.g., needs to be executed once per physical package to configure the desired platform feature (e.g., MKTME feature)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2,4,6,8,16,18 are rejected under 35 U.S.C. 103 as being unpatentable over Griffy in view of Berntsen et al. Publication No. US 2016/0299720 A1 ( Berntsen hereinafter)
Regarding claim 2,
Griffy further teaches
Wherein the first memory access circuit and the second memory access circuit each further comprise a plurality of configuration registers; and a re-encryption circuit configured to: receive configuration instructions directed to the plurality of configuration registers (¶0053 -Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as corresponding control/capabilities register(s) 126 of socket -control/capabilities
registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager storage 142) that indicate the functionality that a corresponding encryption circuit is capable of – ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose. In certain embodiments - ¶ 0068, Table 3 -Table 3 below indicates example PCONFIG targets (e.g., MKTME encryption circuit – ¶ 0079 Mapping
these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments).
However, Griffy does not explicitly teach
for each configuration instruction of the configuration instructions received: determine whether a source of the configuration instruction is authorized to access the plurality of configuration registers; and in response to determining the source of the configuration instruction is authorized, access the plurality of configuration registers according to the configuration instruction.
Berntsen teaches
for each configuration instruction of the configuration instructions received: determine whether a source of the configuration instruction is authorized to access the plurality of configuration registers; and in response to determining the source of the configuration instruction is authorized, access the plurality of configuration registers according to the configuration instruction (¶ 0092-¶0094 - relevant data stored in the memory protection configuration area of flash 13 is copied to memory protection configuration registers accessible to the memory protection logic 9. These registers are writeable only from a hardware state machine that executes only during power on of the microcontroller 1,. For every data access request, the memory protection logic 9 determines whether the source of the access request was from the firmware module 23 or elsewhere by checking the value of the "firmware region" register. It can be configured to detect if the source of the request is the debugger interface 18, or a direct-memory access (DMA) unit, by determining the identity of the active memory bus master. It also accesses the memory protection configuration. registers to determine whether to allow or deny the access request based on the state of the "firmware region" register and the identity of the bus master – See Also ¶ 0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Berntsen. The motivation for doing so is to allow the system to provide additional security by restricting access to registers in case user omits to set new configuration after an erase (Berntsen - ¶ 0066).
Regarding claim 4,
Griffy further teaches
Where in the first memory access circuit and the second memory access circuit are each further comprise read the first encrypted data block from the memory circuit before writing the second encrypted data block to the memory circuit (Abstract - encrypt code and data of the virtual machine from the memory with an encryption key by the encryption circuit of the hardware processor, store the encrypted code and data of the virtual machine within a migration buffer of the memory of the first computer system by the direct memory access engine circuit, and cause the network interface controller circuit to send the encrypted code and data of the virtual machine from the migration buffer to the second computer system via the network - ¶0079 - -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key re-encrypts with a transfer key to send over the network – ¶ 0053 -Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as corresponding control/capabilities register(s) 126 of socket 122.) .
Regarding claim 6,
Griffy further teaches
Wherein: the first encrypted data block comprises one of a plurality of encrypted data blocks; and the first memory access circuit and the second memory access circuit each further configured to is further configured to re-encrypt the plurality of encrypted data blocks(¶ 0079 - -Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key re-encrypts with a transfer key to send over the network – ¶ 0053 -Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as corresponding control/capabilities register(s) 126 of socket 122- Abstract - a first computer system includes an encryption circuit in a hardware processor of the first computer system to encrypt data-encrypt code and data of the virtual machine from the memory with an encryption key by the encryption circuit of the hardware processor, store the encrypted code and data of the virtual machine within a migration buffer of the memory of the first computer system
by the direct memory access engine circuit – See Als0 -¶ 0085).
Regarding claim 8,
Griffy further teaches
wherein each plurality of configuration registers is further configured to store a start indication indicating to start re-encrypting the plurality of encrypted data blocks in the associated memory circuit (¶ 0081- the first host 400A (e.g., a hardware processor (e.g., CPU 402A) of the host 400A) is to send an indication to the second host 400B that a live migration is to be performed. set the Key ID for the migration buffer in first host 400A to use the "transfer" key, the host 400A performs a DMA (e.g., by memory controller circuit 416A) to send the VM' s memory to the migration buffer in first host 400A, and this DMA will decrypt the VM's memory from the previously used key and re-encrypt the data into the migration buffer with the transfer key (or any combination of the above). In certain embodiments, the second subset of operations includes (e.g., as shown as arrow (2) in FIG. 3), setting that the data transfer between the first host 400A and the second host 400B will not utilize further encryption ( e.g., an encryption circuit of NIC circuit/RDMA engine of the first host 400A will not utilize encryption – ¶ 0063 - the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) -See ¶ 0068 &¶ 0079)
Regarding claim 16,
Griffy further teaches
Wherein each the memory interface circuit further comprises a plurality of configuration registers and each memory interface circuit is further configured to: receive a configuration instruction on the secure interface to access the plurality of configuration registers (¶0053 -Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as corresponding control/capabilities register(s) 126 of socket -control/capabilities
registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager storage 142) that indicate the functionality that a corresponding encryption circuit is capable of – ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose. In certain embodiments - ¶ 0068, Table 3 -Table 3 below indicates example PCONFIG targets (e.g., MKTME encryption circuit – ¶ 0079 Mapping
these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments) ;
However, Griffy does not explicitly teach
determine whether a source of the configuration instruction has authorization to access the plurality of configuration registers; and in response to determining the source of the configuration instruction has authorization, access the plurality of configuration registers according to the configuration instruction.
Berntsen teaches
receive a configuration instruction on the secure interface to access the plurality of configuration registers; determine whether a source of the configuration instruction has authorization to access the plurality of configuration registers; and in response to determining the source of the configuration instruction has authorization, access the plurality of configuration registers according to the configuration instruction (¶ 0092-0094 - relevant data stored in the memory protection configuration area of flash 13 is copied to memory protection configuration registers accessible to the memory protection logic 9. These registers are writeable only from a hardware state machine that executes only during power on of the microcontroller 1,. For every data access request, the memory protection logic 9 determines whether the source of the access request was from the firmware module 23 or elsewhere by checking the value of the "firmware region" register. It can be configured to detect if the source of the request is the debugger interface 18, or a direct-memory access (DMA) unit, by determining the identity of the active memory bus master. It also accesses the memory protection configuration. registers to determine whether to allow or deny the access request based on the state of the "firmware region" register and the identity of the bus master – See Also ¶ 0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Berntsen. The motivation for doing so is to allow the system to provide additional security by restricting access to registers in case user omits to set new configuration after an erase (Berntsen - ¶ 0066)
Regarding claim 18,
Griffy further teaches
receiving, in a re-encryption circuit, configuration instructions directed to a plurality of configuration registers associated with the respective memory interface circuit ((¶0053 -Computer system 100 includes control/capabilities register(s). In one embodiment, each of control/capabilities register(s) 106 of socket 102 includes a same data as corresponding control/capabilities register(s) 126 of socket -control/capabilities registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager storage 142) that indicate the functionality that a corresponding encryption circuit is capable of – ¶ 0063 -the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction (e.g., when executed by a core) is used to execute functions for configuring platform features, e.g., where register (e.g., EAX) indicates the (e.g., leaf) function to be invoked and register(s) (e.g., RBX/RCX/RDX) indicate the (e.g., leaf) specific purpose. In certain embodiments - ¶ 0068, Table 3 -Table 3 below indicates example PCONFIG targets (e.g., MKTME encryption circuit – ¶ 0079 Mapping these pages this way effectively uses the existing MK-TME engine to decrypt the VM's data from its current key, re-encrypts with a transfer key to send over the network, then re-encrypt with a new live key on the new host in certain embodiments).
However, Griffy does not explicitly teach
for each configuration instruction of the configuration instructions received: determining whether a source of the configuration instruction is authorized to access the plurality of configuration registers associated with the respective memory interface circuit; and in response to determining the source of the configuration instruction is authorized, accessing the plurality of configuration registers according to the configuration instruction.
Berntsen teaches
for each configuration instruction of the configuration instructions received: determining whether a source of the configuration instruction is authorized to access the plurality of configuration registers associated with the respective memory interface circuit; and in response to determining the source of the configuration instruction is authorized, accessing the plurality of configuration registers according to the configuration instruction (¶ 0092-¶0094 - relevant data stored in the memory protection configuration area of flash 13 is copied to memory protection configuration registers accessible to the memory protection logic 9. These registers are writeable only from a hardware state machine that executes only during power on of the microcontroller 1,. For every data access request, the memory protection logic 9 determines whether the source of the access request was from the firmware module 23 or elsewhere by checking the value of the "firmware region" register. It can be configured to detect if the source of the request is the debugger interface 18, or a direct-memory access (DMA) unit, by determining the identity of the active memory bus master. It also accesses the memory protection configuration. registers to determine whether to allow or deny the access request based on the state of the "firmware region" register and the identity of the bus master – See Also ¶ 0044).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Berntsen. The motivation for doing so is to allow the system to provide additional security by restricting access to registers in case user omits to set new configuration after an erase (Berntsen - ¶ 0066).
Claims 3,5,7,9,10 are rejected under 35 U.S.C. 103 as being unpatentable over Griffy in view of Berntsen further in view of Chhabra et al. Publication No.US 2019/0229924 A1 ( Chhabra hereinafter).
Regarding claim 3,
Griffy does not explicitly teach
each plurality of configuration registers configured to store a first number indicating the first encrypted data block comprises the first number of cache lines
However, Chhabra teaches
each plurality of configuration registers configured to store a first number indicating the first encrypted data block comprises the first number of cache lines (Fig.3, ¶ 0068 - As previously discussed, temporal uniqueness may be based on a chain of counters each associated with a hierarchy of data lines. In at least one embodiment, the lowest level counter may then be associated with a location (e.g., address) in memory module 104 to which an encrypted cache line will be written, wherein the counters are incremented on each write to the memory location. The counters may be used to formulate a VER for the data line for providing replay protection -See Also ¶ 0069).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Regarding claim 5,
Griffy further teaches
wherein: the first number of cache lines are stored in sequential memory addresses in the associated memory circuit; and the first memory access circuit and second memory access circuit is further configured to increment the first memory address (¶ 0085 - the data transferred over can be encrypted using a random string (e.g., "salt") value. The salt value can be pre-agreed between HOST 1 and HOST2 and can be mixed into the data (e.g., logically XORed with data) before encryption and incremented on every (e.g., 16B) block boundary. On the receiving end, the HOST2 can use the same salt to retrieve plaintext – ¶ 0053 - control/capabilities registers store the control values and/or capability indicating values of an encryption circuit or other component. For example, where capabilities registers store value(s) (e.g., provided by execution of hardware initialization manager storage 142) that indicate the functionality that a corresponding encryption circuit is capable of).
However, Griffy does not explicitly teach
each plurality of configuration registers further configured to store a first memory address of a current cache line of the first number of cache lines in the first encrypted data block to be read, the first memory access circuit and second memory access circuit is further configured to increment the first memory address each time one of the first number of cache lines of the first encrypted data block is read
Chhabra teaches
each plurality of configuration registers further configured to store a first memory address of a current cache line of the first number of cache lines in the first encrypted data block to be read, wherein: the first number of cache lines are stored in sequential memory addresses in the memory circuit; and the first memory access circuit and second memory access circuit is further configured to increment the first memory address each time one of the first number of cache lines of the first encrypted data block is read (¶ 0122 - When a data line is read from memory, the MEE verifies its MAC as well. This ensures protection against modification attacks on the data line while it was resident in memory, providing integrity protection to the MEE region. The version nodes hold the version of a data line which is incremented each time a data line is written back to memory. A metadata node in the counter tree (LO, Ll , L2) consists of counter values and an embedded MAC, computed over the counters stored in the node. As an input to the embedded MAC – ¶ 0148 – first version line of a cache line associated with a cache request is read from memory and the first cache line associated with the version line is read from memory. At operation 2315 the old major/minor counter values are recorded, the major counter is incremented by 1 and the minor counter is reset to zero – ¶ 0107 - Each LO counter 1440 is linked to a version block 1450, which contains a sequence of version nodes (represented by "V") 1460. Each version node 1460 is associated with an encrypted data line 1480 in the protected region)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Regarding claim 7,
Griffy does not explicitly teach
wherein: the associated plurality of encrypted data blocks are stored in a range of memory addresses in the associated memory circuit; and each plurality of configuration registers is configured to store a maximum memory address in the associated range of memory addresses
However, Chhabra teaches
wherein: the associated plurality of encrypted data blocks are stored in a range of memory addresses in the associated memory circuit; and each plurality of configuration registers is configured to store a maximum memory address in the associated range of memory addresses (¶ 0104 - The union of these regions may be referred to as the "MEE region" forming a range of physical addresses that is fixed to some size at boot time (e.g., 128 MB), in a trustworthy way. In some cases, the entirety of the MEE region may be referred to as the protected or secured memory region. Read/write requests to the protected region may be routed by the memory controller 210 to the MEE 212, which encrypts (or decrypts) the data before sending (fetching) it to (from) the DRAM) ¶ 0082 – ¶ 0083 -With the adaptive counter mapping, mappings between counters and corresponding lower-level data lines or memory locations in memory module 104 are no longer static. Therefore, logic may be used to configure selectors 602 to point to the correct lower-level data lines or memory locations.- Counter index 702 is the index that would be used to locate the counter without the adaptive scheme, and may be easily calculated ( e.g., using the address in memory module 104 of the particular encrypted data line – ¶ 0068 - the lowest level counter may then be associated with a location (e.g., address) in memory module 104 to which an encrypted cache line will be written, wherein the counters are incremented on each write to the memory location. The counters may be used to formulate a VER for the data line for providing replay protection – See Also Fig.4, ¶ 0073).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Regarding claim 9,
Griffy further teaches
Wherein the first memory access circuit and the second memory access circuit each further comprises a first secure key register and a second secure key register(¶ 0064 - MKTME encryption circuit maintains an internal key table not accessible by software to store the information (e.g., key and encryption mode) associated with each KeyID (e.g., a corresponding KeyID for a corresponding encrypted memory block/page) (for example, where a key ID is incorporated into the physical address, e.g., in the page tables, and also in every other storage location such as the caches and TLB) – ¶ 0065 - the PCONFIG is used to program KeyID attributes for MKTME -see Also ¶ 0079).
However, Griffy does not explicitly teach
wherein: the first secure key register is configured to store the associated first key; the second secure key register is configured to store the associated second key; and in response to a first indication that re-encrypting the plurality of encrypted data blocks is complete, the associated re-encryption circuit is further configured to update the associated first key register to store an updated first key
Chhabra teaches
wherein: the first secure key register is configured to store the associated first key; the second secure key register is configured to store the associated second key; and in response to a first indication that re-encrypting the plurality of encrypted data blocks is complete, the associated re-encryption circuit is further configured to update the associated first key register to store an updated first key (Fig.23, ¶ 0147 - FIG. 23 illustrates operations in a re-encryption flow for key rotation – ¶ 0148 - at operation 2310 a first version line of a cache line associated with a cache request is read from memory and the first cache line associated with the version line is read from memory. At operation 2315 the old major/minor counter values are recorded, the major counter is incremented by 1 and the minor counter is reset to zero. At operation 2320 the cache line is decrypted with the old major counter and minor counter and is re-encrypted with the new major counter and minor counter and written back to memory – ¶ 0146 - At the time of a key refresh for a line in memory, the line is re-encrypted with the new key. the minor counters are reset at re-encryption time. The major/minor counter organization used with KR-tree works naturally with key rotation. At the time of re-keying, the data lines are read from memory in a special mode where the encryption engine in addition to re-encryption with the new key resets the minor counter, increments the major counter and uses the new combination as the counter to encrypt the line – ¶ 0095 - generating a new key (block 1105). In an embodiment, this old key may be stored in a storage of the TMP module itself. The new key may be generated, the new key also may be stored in a storage of the TMP module).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Regarding claim 10,
Griffy further teaches
Wherein the first memory access circuit and the second memory access circuit each further configured to re-encrypt the plurality of encrypted data blocks based on the updated first key and update the second key register to store an updated second key (¶ 0081 - this DMA will decrypt the VM's memory from the previously used key and re-encrypt the data into the migration buffer with the transfer key (or any combination of the above second host 400B will store the transferred data into its migration buffer encrypted as well because no decryption operation is performed in this step ( e.g., an encryption circuit of NIC circuit/RD MA engine of the second host 400B will not utilize decryption). In certain embodiments, the third subset of operations includes (e.g., as shown as arrow (3) in FIG. 3), the second host 400B ( e.g., a hardware processor (e.g., CPU 402B) of the host 400B) sets the encryption key (e.g., Key ID in MKTME circuit) to use the transfer key for the migration buffer in host 400B -See ¶ 0053 &¶ 0063).
However, Griffy does not explicitly teach
in response to a second indication that re-encrypting the plurality of encrypted data blocks is complete, re-encrypt the associated plurality of encrypted data blocks based on the updated first key and update the associated second key register to store an updated second key
Chhabra further teaches
in response to a second indication that re-encrypting the plurality of encrypted data blocks is complete, re-encrypt the associated plurality of encrypted data blocks based on the updated first key and update the associated second key register to store an updated second key(Fig.23, ¶ 0147 - FIG. 23 illustrates operations in a re-encryption flow for key rotation – ¶ 0148 - at operation 2310 a first version line of a cache line associated with a cache request is read from memory and the first cache line associated with the version line is read from memory. At operation 2315 the old major/minor counter values are recorded, the major counter is incremented by 1 and the minor counter is reset to zero. At operation 2320 the cache line is decrypted with the old major counter and minor counter and is re-encrypted with the new major counter and minor counter and written back to memory – ¶ 0146 - At the time of a key refresh for a line in memory, the line is re-encrypted with the new key. the minor counters are reset at re-encryption time. The major/minor counter organization used with KR-tree works naturally with key rotation. At the time of re-keying, the data lines are read from memory in a special mode where the encryption engine in addition to re-encryption with the new key resets the minor counter, increments the major counter and uses the new combination as the counter to encrypt the line – ¶ 0095 - generating a new key (block 1105). In an embodiment, this old key may be stored in a storage of the TMP module itself. The new key may be generated, the new key also may be stored in a storage of the TMP module).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Claims 14,15 are rejected under 35 U.S.C. 103 as being unpatentable over Griffy in view Chhabra et al. Publication No.US 2019/0229924 A1 ( Chhabra hereinafter).
Regarding claim 14,
Griffy further teaches
wherein the secure processor is configured to: transmit a second configuration instruction to start re-encrypting each block of the plurality of encrypted data blocks (¶ 0063 - the mode(s) are enumerated and activated using a TME MSRs and/or used by software through extensions to a platform configuration (PCONFIG) instruction. In certain embodiments, a PCONFIG instruction)
However, Griffy does not explicitly teach
transmit a second configuration instruction to start re-encrypting each block of the plurality of encrypted data blocks within a configurable time window; and configure the time window to be long enough to re-encrypt every block of the plurality of encrypted blocks in the configured range of memory addresses
Chhabra teaches
wherein the secure processor is configured to: transmit a second configuration instruction to start re-encrypting each block of the plurality of encrypted data blocks within a configurable time window; and configure the time window to be long enough to re-encrypt every block of the plurality of encrypted blocks in the configured range of memory addresses (¶ 0094 -
, the arbitration-based technique allows low-priority memory accesses to be impacted first, while letting high-priority traffic proceed. Note that the rollback time window can be configured differently for applications having varying security and other features, trading off performance overheads for a shorter rollback window – ¶ 0092 To provide rollback protection, MAC values may periodically be re-keyed so that a compromised MAC value recorded at an earlier time cannot later be replayed (at least outside of a re-keying time window) without raising an integrity violation.- ¶ 0096 - this re-MAC timer may be set on the order of approximately a given number of minutes ( which may be on the order of many billions of processor clock cycles). If it is determined that this timer has expired or the TMP module is idle (and thus at an ideal time to perform re-keying), control passes to block 1130. At block 1130 a MAC stored in the current MAC address may be loaded, along with its associated data. Using this information, the MAC may be re-keyed and the resulting new MAC may be stored at the current MAC address – ¶ 0146 - At the time of a key refresh for a line in memory, the line is re-encrypted with the new key. In order to allow the small counters to again be capable of covering the vulnerability window (minimizing the probability of rollover inside a vulnerability window), the minor counters are reset at re-encryption time. At the time of re-keying, the data lines are read from memory in a special mode where the encryption engine in addition to re-encryption with the new key resets the minor counter, increments the major counter and uses the new combination as the counter to encrypt the line).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Regarding claim 15,
Griffy further teaches
wherein: each memory interface circuit is further configured to: receive memory access transactions from the at least one processing circuit and access the associated memory circuit in response to the memory access transactions (¶ 0057 - Memory controller circuit 116 of socket 102 may receive an address for a memory access request, e.g., and for a store request also receiving the payload data (e.g., ciphertext) to be stored at the address, and then perform the corresponding access into memory 120, e.g., via one or more memory buses 118)
However, Griffy does not explicitly teach
associated secure processor is configured to: determine an idle time of the associated memory interface circuit between receiving consecutive memory access transactions; and adjust the time window based on the idle time
Chhabra teaches
receive memory access transactions from the at least one processing circuit; and access the associated memory circuit in response to the memory access transactions (¶ 0104 - Internal memory (or cache) of an example processor may be relatively small and may be accessed much faster than the system memory. During normal operation, memory transactions may be continuously issued by the processor's core(s) (e.g., 206A, 206B, 206C), and transactions that miss the cache may be handled by the memory controller (e.g.,210). The MEE 212, in some implementations, may operate as an extension of the memory controller 210, managing at least some aspects of the cache-system memory (e.g., DRAM) traffic that points to the protected region 204 of memory. The MEE 212 may autonomously initiate additional transactions to verify ( or update) the integrity tree, such as based on a construction of counters and MAC tags (also referred to as embedded MACs). The self-initiated transactions access the seized region on the DRAM, and also some on-die array that serves as the root of the tree).
the associated secure processor is configured to: determine an idle time of the associated memory interface circuit between receiving consecutive memory access transactions; and adjust the time window based on the idle time (¶ 0096 - control next passes to diamond 1120 to determine whether the TMP module is idle or a re-MAC timer has expired. In an embodiment, this re-MAC timer may be set at a configurable value to provide an appropriate level of rollback protection. Understand that the lower the value of this timer, the greater the protection that is afforded, while at the same time, the greater the impact on performance due to re-keying operations. this re-MAC timer may be set on the order of approximately a given number of minutes ( which may be on the order of many billions of processor clock cycles). If it is determined that this timer has expired or the TMP module is idle (and thus at an ideal time to perform re-keying), control passes to block 1130. At block 1130 a MAC stored in the current MAC address may be loaded, along with its associated data -See Also ¶ 0099,¶ 0093-¶ 0094)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Griffy to include the teachings of Chhabra. The motivation for doing so is to allow the system to implement key rotating trees with split counters for efficient hardware replay protection (Chhabra - ¶0030).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YOUNES NAJI whose telephone number is (571)272-2659. The examiner can normally be reached Monday - Friday 8:30 AM -5:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Oscar A Louie can be reached on (571) 270-1684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YOUNES NAJI/Primary Examiner, Art Unit 2445
Prosecution Insights