Prosecution Insights
Last updated: May 29, 2026
Application No. 18/755,129

DATA LINK RECEIVER CALIBRATION

Non-Final OA §101§102§103
Filed
Jun 26, 2024
Examiner
PRIFTI, AUREL
Art Unit
2175
Tech Center
2100 — Computer Architecture & Software
Assignee
Microsoft Technology Licensing, LLC
OA Round
1 (Non-Final)
83%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
516 granted / 622 resolved
+28.0% vs TC avg
Strong +22% interview lift
Without
With
+22.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
20 currently pending
Career history
644
Total Applications
across all art units

Statute-Specific Performance

§101
2.7%
-37.3% vs TC avg
§103
80.8%
+40.8% vs TC avg
§102
9.8%
-30.2% vs TC avg
§112
2.7%
-37.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 622 resolved cases

Office Action

§101 §102 §103
DETAILED ACTION Claims 1-20 are presented for examination. The present application is being examined under the AIA (America Invents Act) First Inventor to File. This Office Action is Non-Final. Claims 1, 9 and 20 are independent claims. Claims 2-8, 10-19 are dependent claims. This action is responsive to the following communication: corresponding claims filed on 06-26-2024. Domestic Priority Applicant’s claim for the benefit of a prior-filed application under 365(c) is acknowledged. Information Disclosure Statement The information disclosure statement (IDS) submitted on 07-01-2025, 07-11-2025,10-13-2025, 01-09-2026, 02-18-2026 and 03-12-2026 are in compliance with the provisions of 37 CFR 1.97 Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claim 20 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. Claim 20 recites a product claim directed to a “computer-readable media…". Because of that, under the broadest reasonable standard, a claim drawn to a computer readable media covers non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer-readable media. On one hand, ¶ [0321] of the Specification recites various CRMs, e.g., “magnetic disks, magnetic tapes or cassettes, CD-ROMs, DVDs”-- -, and that these mediums to store information in a non-transitory way. On the other hand, claim 15 is directed to a “computer readable media”, which is different from the mediums for which the exclusionary provision is directed to. Therefore, since a signal is not one of the four statutory categories “process, machine, manufacture or composition of matter”. Energy is not one of the four categories of invention and therefore this/these claim(s) is/are not statutory .Thus, the claims are non-statutory. See MPEP 2106.01. To overcome a rejection under 35 U.S.C. 101 to a claim drawn to a computer readable media that cover both non-transitory and transitory embodiments may be amended to cover only statutory embodiments by adding the limitation "non-transitory" before “computer readable media". Such an amendment is not considered new matter. See the "Subject Matter Eligibility of Computer Readable Media" memo dated January 26, 2010 (OG Cite: 1351 OG 212; OG Date: 23 Feb 2010). Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 9-10, 12, 14 are rejected under 35 U.S.C. 102(a)(1)/(a)/(2) as being anticipated by U.S. Patent 11,239,992 (hereinafter, “Wang”). As per claim 9, Wang discloses an apparatus comprising: a phase detector (slicer) coupled to receive signals from a clock lane and a data lane of a transmission bus and configured to output, based on a phase offset between the received signals, a comparison signal (phase adjustment clock ) in a calibration mode; (Fig. 1 illustrates a transmitter 102 that is configured to send serial data and serial clock to a receiver 108 that is coupled together over a high-speed serial data interface. Fig. 1 further illustrates a slicer 118, where the serial clock experiences a phase adjustment by the phase interpolator. The phase adjustment clock signal to the slicer is the claimed comparison signal. ) a phase shifter (phase calibrator) coupled to receive a control signal (deserialized data) derived from the comparison signal (Col 5 lines 50-54 state “deserialized data is a product of phase adjusted clock) and apply a phase shift in the clock lane based on the control signal; (phase calibrating the phase shifted clock signal so that the phase interpolator 116 may provide a phase adjusted (or phase calibrated) clock signal to the slicer 118 so that the slicer 118 may correctly sample data”) wherein the control signal and the applied phase shift drive the phase offset toward a target value. (Col 5 lines 50-54 state “deserialized data is a product of phase adjusted clock) and apply a phase shift in the clock lane based on the control signal; (phase calibrating the phase shifted clock signal so that the phase interpolator 116 may provide a phase adjusted (or phase calibrated) clock signal to the slicer 118 so that the slicer 118 may correctly sample data”) As per claim 10, Wang discloses an apparatus wherein the received signals are matching signals. (phase interpolator to shift the phase of the serial clock signal may include shifting the serial clock signal such that an edge of the serial clock signal is aligned with middle of data eye of the serial data signal; Col 1 lines 64-67) As per claim 12, Wang discloses an apparatus wherein the phase shifter comprises a phase interpolator. (phase interpolator 116; Fig 1) As per claim 14, Wang discloses an apparatus further comprising a controller coupled to receive the comparison signal and generate the control signal based on the comparison signal. (deserializer 120 which deserializes the serial data signal and provides the deserialized data; Fig. 1) Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 6, 20 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent 11,239,992 (hereinafter, “Wang”) and further view of U.S. Publication No. 2008/0232179 (hereinafter, “Kwak”). As per claims 1, 20, Wang discloses a method comprising: at a transmitter configured to drive a data lane and a clock lane whose cycles correspond to respective bits on the data lane: (Fig, 1 illustrates a clock transmitter 104 and a data transmitter 106, where the data lane is sampled using bits as further illustrated by Fig’s 2-3) driving matching signals on the data lane and the clock lane; (Fig. 1 illustrates a clock receiver 110 and data receiver 112 such that clock signal is aligned with middle of data by undergoing a phase adjustment; Col 1 lines 64-67) at a receiver configured to [sample] data received on the data lane at edges received on the clock lane: (data sampling techniques where the data is sampled at both the rising edge and the falling edge; Col 7 lines 44-45) receiving the matching signals; and (phase adjusted signal and serial data signal; Fig 1 measuring a phase offset between respective signals derived from the matching signals; (shift the phase of the serial clock signal may include shifting the serial clock signal such that an edge of the serial clock signal is aligned with middle of data eye of the serial data signal; Col 1 lines 64-67) controlling an adjustable phase shift in the clock lane until, at a first value of the phase shift, the measured phase offset matches a target phase offset; and setting the adjustable phase shift based on the first value. (Col 5 lines 50-54 state “deserialized data is a product of phase adjusted clock) and apply a phase shift in the clock lane based on the control signal; (he embodiments of the present disclosure provide techniques for phase calibrating the phase shifted clock signal so that the phase interpolator 116 may provide a phase adjusted (or phase calibrated) clock signal to the slicer 118 so that the slicer 118 may correctly sample data”) Wang does not distinctly disclose a circuit that is configured to latch data. However, Kwak discloses that. In particular, Kwak discloses the following: at a transmitter configured to drive a data lane and a clock lane whose cycles correspond to respective bits on the data lane: (memory controller to transmit extclk and command/address data, where data is supplied bit words; ¶ [0034]) at a receiver configured to latch data received on the data lane: ( upon receiving the CLKUP and the CLKDN signals respectively, the read latency control circuit 202 matches the timing of the READ signal to the internal clock signals of the synchronization circuit 201; ¶ [0019] ) It would have been obvious before the effective filing date of the claimed invention to modify the teachings of Wang and Kwak because both references are in the same field of endeavor. Kwak’s teaching of a latch would enhance Wang's system by allowing the system to store values that is more efficient, thus enhancing power consumption. As per claim 2, Wang as modified discloses a method comprising subsequent to the setting, transmitting content data from the transmitter to the receiver over the data lane. (Wang: Fig, 1 illustrates a clock transmitter 104 and a data transmitter 106 for transmitting to the receiver) As per claim 6, Wang as modified discloses a method wherein the controlling the adjustable phase shift comprises: comparing a first signal representing the measured phase offset with a second signal representing the target phase offset; and applying one or more control signals to a phase shifter to drive the measured phase shift toward the target phase offset. (phase calibrating the phase shifted clock signal so that the phase interpolator 116 may provide a phase adjusted (or phase calibrated) clock signal to the slicer 118 so that the slicer 118 may correctly sample data”) Allowable Subject Matter Over 35 USC § 102/103 Claims 3-5, 7-8, 11, 13, 15-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion With respect to any newly added or amended claims, applicant should show support in the original disclosure for the new or amended claims. See MPEP §714.02 and § 2163.06. For example, when responding to this office action, applicants are advised to provide the examiner with the line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AUREL PRIFTI whose telephone number is (571)270-1743. The examiner can normally be reached on M-F 8 a.m.- 6 p.m.. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached on 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /AUREL PRIFTI/Primary Examiner, Art Unit 2175 Aurel Prifti Primary Examiner Art Unit 2175 Tel. (571) 270-1743 Fax (571) 270-2743 aurel.prifti@uspto.gov
Read full office action

Prosecution Timeline

Jun 26, 2024
Application Filed
Apr 01, 2026
Non-Final Rejection mailed — §101, §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
83%
Grant Probability
99%
With Interview (+22.3%)
2y 7m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 622 resolved cases by this examiner. Grant probability derived from career allowance rate.

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