DETAILED ACTION
The RCE filed September 08, 2026 has been entered. Claims 1-20 are pending. Claim 20 was cancelled. Claims 1, 12 and 19 are independent.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 11-15 and 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Doluca et al. (US 2025/0364040).
Regarding independent claims 1 and 19, Doluca et al. disclose a read multiplexer circuit for a multiport register file, comprising:
an input stage (see e.g., FIG. 7: input of 110) coupled to configured to receive a storage node output from an array of storage nodes, each storage node coupled to drive a respective storage node output of a respective bitcell (DI of ROWS by WR_ADDR);
a read stage (output of 110) coupled to an output of the input stage to receive the storage node output therefrom, the read stage comprising control logic dividing the array of storage nodes into one or more sets and first circuitry that provides a first read word line (e.g., one of RD_ADDR; and para. 0078: read address RD_ADDR to select one of the N rows for reading) to a first storage node of a first set for reading data from the first storage node, and a second read word line (e.g., one of RD_ADDR) to a second storage node of the first set for reading data from the second storage node; and
a first latch stage (126) comprising second circuitry that provides a third read word line (see 120, OTHER BANKS, i.e., another word line in other banks) to the first storage node (output of 98 selected by one of RD_ADDR) and the second storage node (output of 98 selected by another RD_ADDR) of the first set to latch the data read from one of the first storage node and the second storage node (see e.g., FIG. 7 and accompanying disclosure).
Regarding claim 11, which depends from claim 1, Doluca et al. disclose an inverter is coupled to an output of a bitcell to drive storage node output of the bitcell (see FIG. 7).
Regarding independent claim 12, Doluca et al. disclose a circuit for a multiport register file comprising:
an array of multiple storage nodes, each having a bitcell (see FIG. 7: DI, ROWS along with memory FIGS. 1-6 memory cell array);
an input stage (FIG. 7: input of 110) configured to receive storage node output from the array of multiple storage nodes (DI, ROWS); and
a two-stage read multiplexer circuit (FIG. 7: output of 110) coupled to an output of the input stage and configured to receive the storage node output of each storage node in the array of multiple storage nodes from the input stage, comprising:
a read stage for selecting data from the storage node output (FIG. 7: 110 through 120, along with FIG. 8: READ CYCLE, RD_ADDR, RE) and ;
a first latch stage for storing the selected data; and control logic for coordinating read operations from multiple ports (FIG. 7: 120 through DO, along with FIG. 8: READ_CYCLE, DOUT VALID).
Regarding claim 13, which depends from claim 12, Doluca et al. disclose a driver is coupled to the output of each storage node and coupled to an input of the two-stage read multiplexer circuit (FIG. 7).
Regarding claim 14, which depends from claim 13, Doluca et al. disclose the driver is provided by an inverter coupled to the output of a bitcell to drive storage node output of the bitcell (FIG. 7).
Regarding claim 15, which depends from claim 13, Doluca et al. disclose control logic dividing the array of storage nodes into sets and first circuitry that provides a first read word line to a first storage node of a first set for reading data from the first storage node and a second read word line to a second storage node of the first set for reading data from the second storage node (FIG. 7).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 10 and 16-17 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Doluca et al. (US 2025/0364040).
Regarding claims 2-3 and 16, Doluca et al. teach the limitations of claims 1 and 15, respectively.
Doluca et al. do not explicitly disclose the first read word line is shared with a first storage node of a second set and the second read word line is shared with a second storage node of the second set for reading data from the first and second storage nodes of the second set respectively; and the first read word line is shared with multiple sets of storage nodes and the second read word line is shared with multiple sets of storage nodes.
However, read word line shared with several storage node (claimed a first storge node and a second storage node) in a multi-bank memory device is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Tanpure et al. (US 2012/0159076), e.g., FIGS. 8-10 and accompanying disclosure.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize memory word lines driving multiple memory banks because these conventional technology are well established in the art of the memory devices.
Regarding claim 10, Doluca et al. teach the limitations of claim 1.
Doluca’s latch circuit does not fully describe multiple sets and wherein each set is coupled to an individual latch circuit.
However, an individual latch circuit for each bit is a well-known technology for a type of memory for its purpose.
For support, of the above asserted facts, see for example, Nguyen et al. (US 2020/0357462), FIG. 1A: dout0 and dout1 paths.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize an individual latch circuit because these conventional technology are well established in the art of the memory devices.
Regarding claim 17, Doluca et al. teach the limitations of claim 16.
Doluca et al. further teach the first latch stage is coupled to control logic that coordinates read operations provided by a read port line coupled from the read stage to the control logic to determine an output state of stored data (see FIG. 7, and accompanying disclosure).
Claims 4-9 and 18 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Doluca et al. (US 2025/0364040) in view of Nguyen et al. (US 2020/0357462).
Regarding claim 4, Doluca et al. teach the limitations of claim 1.
Doluca et al. are silent with respect to the first circuitry that provides a first read word line to the first storage node comprises a first transistor and a second transistor coupled in series between a source voltage and a reference voltage.
Nguyen et al. teach the deficiencies in e.g., FIG. 1A: 108, and accompanying disclosure.
Doluca and Nguyen are analogous art because they both are directed to memory multiplexer circuits and one of ordinary skill in the art would have had a reasonable expectation of success to modify Doluca with the specified features of Nguyen because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Nguyen et al. to the teaching of Doluca et al. such that a memory, as taught by Doluca et al., utilizes series transistors, as taught by Nguyen et al., for the purpose of comprising NOR functions, thereby enhancing signal integration.
Regarding claim 5, Doluca et al. and Nguyen et al., as combined, teach the limitations of claim 4.
Doluca and Nguyen do not explicitly disclose the first transistor is activated by the first read word line and the second transistor is activated by a logical inversion of the first read word line.
However, the word line activation with logical gates (such as inverter, NAND or NOR) is a well-known technology for a type of memory control logic for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize logical control gates in a memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claim 6, Doluca et al. and Nguyen et al., as combined, teach the limitations of claim 5.
Nguyen et al. further teach a third transistor is coupled between the second transistor and the source voltage and a fourth transistor is coupled between the second transistor and the reference voltage (FIG. 1A, further read multiplexer comprising transistor is a well-known technology).
Regarding claims 7-8, Doluca et al. and Nguyen et al., as combined, teach the limitations of claim 6.
Nguyen et al. do not explicitly disclose the first latch stage comprising second circuitry such that the first read word line is coupled between the first transistor and the second transistor; and the first latch stage is coupled to control logic that coordinates read operations provided by a read port line coupled from the first read stage to the control logic to determine an output state of stored data.
However, data latch circuit relates read word line in a memory device is a well-known technology for a type of memory control logic for its purpose.
It would have been obvious to one of ordinary skill in the art before the effective filing date to utilize logical control gates controlling data latch in a memory operation because these conventional technology are well established in the art of the memory devices.
Regarding claims 9 and 18, Doluca et al. teach the limitations of claim 1 and 15, respectively.
Doluca et al. are silent with respect to the limitations of claims 9 and 18.
Nguyen et al. teach a second latch stage comprising third circuitry that provides a fourth read word line to a first and second storage node of a different set to the first set to latch the read from one of the first and second storage nodes of that different set according to an address specifying a location of the storage node in the read multiplexer circuit (see FIG. 1A: 130 latch, latch for dout0 and latch for dout1, and para. 0023, r0_addr and r1_addr).
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Nguyen et al. to the teaching of Doluca et al. such that a memory, as taught by Doluca et al., utilizes series transistors, as taught by Nguyen et al., for the purpose of storing output data effectively.
Comments on Amendment
Applicant’s RCE filed 09/08/2026, with respect to the rejection(s) of claims 1-19 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection.
Conclusion
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/SUNG IL CHO/Primary Examiner, Art Unit 2825
