Prosecution Insights
Last updated: October 02, 2026
Application No. 18/755,189

SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP

Non-Final OA §103
Filed
Jun 26, 2024
Priority
Dec 21, 2021 — continuation of 17/558,012
Examiner
NGUYEN, SOPHIA T
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Intel Corporation
OA Round
1 (Non-Final)
45%
Grant Probability
Moderate
1-2
OA Rounds
6m
Est. Remaining
59%
With Interview

Examiner Intelligence

Grants 45% of resolved cases
45%
Career Allowance Rate
236 granted / 528 resolved
-23.3% vs TC avg
Moderate +14% lift
Without
With
+14.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
71 currently pending
Career history
617
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
14.6%
-25.4% vs TC avg
§112
26.5%
-13.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 528 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of species 1d, Fig. 7C in the reply filed on 08/03/2026 is acknowledged. Regarding claims 11-15, as stated in election/restriction requirement, claims 11-15 directs to species 1f which is not shown in Fig. 7C nor in any other drawings. Accordingly, claims 11-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10, 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hafez et al. (US Pub. 2190287972) in view of Webb et al. (US Pub. 20160233298). Regarding claim 1, Hafez et al. discloses in Fig. 8A an integrated circuit structure, comprising: a first plurality of fins [right fin 804] on a substrate [802][paragraph [0055], “Each of the individual fins 804 depicted… may represent a plurality of fins at a given location”]; a second plurality of fins [middle fin 804] on the substrate [802], the second plurality of fins [middle fin 804] laterally spaced apart from the first plurality of fins [right fin 804][paragraph [0055], “Each of the individual fins 804 depicted… may represent a plurality of fins at a given location”]; a first gate endcap wall [821A] laterally spaced apart from a side of the first plurality of fins [right fin 804] opposite the second plurality of fins [middle fin 804]; a first gate stack [808 right] over an upper portion of the first plurality of fins [right fin 804] and in contact with the first gate endcap wall [821A]; a second gate endcap wall [820 left] laterally spaced apart from a side of the second plurality of fins [middle fin 804] opposite the first plurality of fins [right fin 804]; a second gate stack [808 middle] over an upper portion of the second plurality of fins [middle fin 804] and in contact with the second gate endcap wall [820 left]; a third gate endcap wall [820 right] between the first plurality of fins [right fin 804] and the second plurality of fins [middle fin 804], the third gate endcap wall [820 right] in contact with the first gate stack [808 right] and the second gate stack [808 middle]; a trench isolation structure [806] laterally adjacent to a lower portion of the first plurality of fins [right fin 804], a lower portion of the second plurality of fins [middle fin 804], a lower portion of the first gate endcap wall [821A], a lower portion of the second gate endcap wall [820 left], and a lower portion of the third gate endcap wall [820 right]; a first cap layer [899 right] on the first gate endcap wall [821A]; a second cap layer [899 left] on the second gate endcap wall [820 left]; and a local conductive interconnect [854] laterally between and in contact with the first cap layer [899 right] and the second cap layer [899 left], the local conductive interconnect [854] on the first gate stack [808 right] and the second gate stack [808 middle], and the local conductive interconnect [854] vertically over the third gate endcap wall [820 right]. PNG media_image1.png 447 634 media_image1.png Greyscale Hafez fails to explicitly disclose the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. However, it would be obvious that a plurality of fins comprises 2 or more fins. Hafez et al. discloses in Fig. 7D, paragraph [0047] that the first plurality of fins [702] comprises a first pair of fins; the second plurality of fins [704] comprises a second pair of fins. However, it would be obvious that a plurality of fins comprises 2 or more fins. Hafez et al. discloses in Fig. 7D, paragraph [0047] that the first plurality of fins [702] comprises a first pair of fins; the second plurality of fins [704] comprises a second pair of fins. Webb et al. discloses in Fig. 7B the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. PNG media_image2.png 474 445 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 7D of Hafez et al. and Webb et al. into the device of Fig. 8A of Hafez et al. to include the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. The ordinary artisan would have been motivated to modify Hafez et al. in the above manner for the purpose of providing suitable configuration of the first plurality of fins and the second plurality of fins. Regarding claims 2 and 17, Hafez et al. discloses in Fig. 8A wherein the local conductive interconnect [854] is in contact with a top of the third gate endcap wall [820 right]. PNG media_image3.png 439 634 media_image3.png Greyscale Regarding claims 3 and 18, Hafez et al. discloses in paragraph [0072] wherein the local conductive interconnect [854] comprises tungsten. Regarding claims 4 and 19, Hafez et al. discloses in Fig. 8A, paragraph [0056], [0068]-[0069] wherein the first gate stack comprises a first high-k dielectric layer [852 right] that is in contact with a sidewall of the first gate endcap wall [821A], and wherein the second gate stack comprises a second high-k dielectric layer [852 middle] that is in contact with a sidewall of the second gate endcap wall [820 left]. Regarding claims 5 and 20, Hafez et al. discloses in Fig. 8A, paragraph [0056], [0067] wherein the first gate stack has a same composition as the second gate stack. Regarding claim 6, Hafez et al. discloses in Fig. 7A, Fig. 7D, Fig. 8A an integrated circuit a first gate endcap wall [821A]; a first plurality of fins [right fin 804] spaced apart from the first gate endcap wall [821A][paragraph [0055], “Each of the individual fins 804 depicted… may represent a plurality of fins at a given location”]; a second gate endcap wall [820 right] spaced apart from the first plurality of fins [right fin 804]; a second plurality of fins [middle fin 804] spaced apart from the second gate endcap wall [820 right][paragraph [0055], “Each of the individual fins 804 depicted… may represent a plurality of fins at a given location”]; a third gate endcap wall [820 left] spaced apart from the second plurality of fins [middle fin 804]; a first gate stack [808 right] over an upper portion of the first plurality of fins [right fin 804], and the first gate stack [808 right] in contact with the first gate endcap wall [821A]; a second gate stack [808 middle] over an upper portion of the second plurality of fins [middle fin 804], and the second gate stack [808 middle] in contact with the second gate endcap wall [820 left]; a trench isolation structure [806] surrounding a lower portion of the first plurality of fins [right fin 804], a lower portion of the second plurality of fins [middle fin 804]; a first cap layer [899 right] on the first gate endcap wall [821A]; a second cap layer [899 left] on the third gate endcap wall [820 left]; and a local conductive interconnect [854] between and in contact with the first cap layer [899 right] and the second cap layer [899 left], the local conductive interconnect [854] on the first gate stack [808 right] and the second gate stack [808 middle], and the local conductive interconnect [854] vertically over the second gate endcap wall [820 right]. PNG media_image4.png 447 634 media_image4.png Greyscale Hafez et al. fails to explicitly disclose in Fig. 8A the first plurality of fins comprises a first fin spaced apart from the first gate endcap wall; a second fin spaced apart from the first fin; the second gate endcap wall spaced apart from the second fin the second plurality of fins comprises a third fin spaced apart from the second gate endcap wall; a fourth fin spaced apart from the third fin; the third gate endcap wall spaced apart from the fourth fin; the first gate stack over an upper portion of the first fin and over an upper portion of the second fin, the first gate stack between the upper portion of the first fin and the upper portion of the second fin; the second gate stack over an upper portion of the third fin and over an upper portion of the fourth fin, the second gate stack between the upper portion of the third fin and the upper portion of the fourth fin, the trench isolation structure surrounding a lower portion of the first fin, a lower portion of the second fin, a lower portion of the third fin, and a lower portion of the fourth fin. However, it would be obvious that a plurality of fins comprises 2 or more fins. Hafez et al. discloses in Fig. 7D, paragraph [0047] that the first plurality of fins [704] comprises a first fin and a second fin spaced apart from the first fin; the second plurality of fins [702] comprises a third fin and a fourth fin spaced apart from the third fin. Webb et al. discloses in Fig. 7B the first plurality of fins comprises a first fin spaced apart from the first gate endcap wall, and a second fin spaced apart from the first fin; the second gate endcap wall spaced apart from the second fin the second plurality of fins comprises a third fin spaced apart from the second gate endcap wall, and a fourth fin spaced apart from the third fin; the first gate stack over an upper portion of the first fin and over an upper portion of the second fin, the first gate stack between the upper portion of the first fin and the upper portion of the second fin; the second gate stack over an upper portion of the third fin and over an upper portion of the fourth fin, the second gate stack between the upper portion of the third fin and the upper portion of the fourth fin; and the trench isolation structure surrounding a lower portion of the first fin, a lower portion of the second fin, a lower portion of the third fin, and a lower portion of the fourth fin. PNG media_image5.png 467 445 media_image5.png Greyscale Hafez et al. discloses the third gate endcap wall [820 left] spaced apart from the second plurality of fins [middle fin 804]. Thus, the combination of Hafez et al. and Webb et al. result to the third gate endcap wall spaced apart from the fourth fin. It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Webb et al. into the method of Hafez et al. to include the first plurality of fins comprises a first fin spaced apart from the first gate endcap wall, and a second fin spaced apart from the first fin; the second gate endcap wall spaced apart from the second fin; the second plurality of fins comprises: a third fin spaced apart from the second gate endcap wall, and a fourth fin spaced apart from the third fin; the third gate endcap wall spaced apart from the fourth fin; the first gate stack over an upper portion of the first fin and over an upper portion of the second fin, the first gate stack between the upper portion of the first fin and the upper portion of the second fin; the second gate stack over an upper portion of the third fin and over an upper portion of the fourth fin, the second gate stack between the upper portion of the third fin and the upper portion of the fourth fin; and the trench isolation structure surrounding a lower portion of the first fin, a lower portion of the second fin, a lower portion of the third fin, and a lower portion of the fourth fin. The ordinary artisan would have been motivated to modify Hafez et al. in the above manner for the purpose of providing suitable configuration of a device including gate stacks formed on the first plurality of fins and the second plurality of fins. Regarding claim 7, Hafez et al. discloses in Fig. 8A wherein the local conductive interconnect [854] is in contact with a top of the second gate endcap wall [820 right]. PNG media_image6.png 447 634 media_image6.png Greyscale Regarding claim 8, Hafez et al. discloses in paragraph [0072] wherein the local conductive interconnect [854] comprises tungsten. Regarding claim 9, Hafez et al. discloses in Fig. 8A, paragraph [0056], [0068]-[0069] wherein the first gate stack comprises a first high-k dielectric layer [852 right] that is in contact with a sidewall of the first gate endcap wall [821A], and wherein the second gate stack comprises a second high-k dielectric layer [852 middle] that is in contact with a sidewall of the third gate endcap wall [820 left]. Regarding claim 10, Hafez et al. discloses in Fig. 8A, paragraph [0056], [0067] wherein the first gate stack has a same composition as the second gate stack. Regarding claim 16, Hafez et al. discloses in Fig. 7A, Fig. 7D, Fig. 8A method of fabricating an integrated circuit structure, the method comprising: forming a first plurality of fins [right fin 804] on a substrate [802][paragraph [0055], “Each of the individual fins 804 depicted… may represent a plurality of fins at a given location”]; forming a second plurality of fins [middle fin 804] on the substrate [802], the second plurality of fins [middle fin 804] laterally spaced apart from the first plurality of fins [right fin 804]; forming a first gate endcap wall [821A] laterally spaced apart from a side of the first plurality of fins [right fin 804] opposite the second plurality of fins [middle fin 804]; forming a first gate stack [808 right] over an upper portion of the first plurality of fins [right fin 804] and in contact with the first gate endcap wall [821A]; forming a second gate endcap wall [820 left] laterally spaced apart from a side of the second plurality of fins [middle fin 804] opposite the first plurality of fins [right fin 804]; forming a second gate stack [808 middle] over an upper portion of the second plurality of fins [middle fin 804] and in contact with the second gate endcap wall [820 left]; forming a third gate endcap wall [820 right] between the first plurality of fins [right fin 804] and the second plurality of fins [middle fin 804], the third gate endcap wall [820 right] in contact with the first gate stack [808 right] and the second gate stack [808 middle]; forming a trench isolation structure [806] laterally adjacent to a lower portion of the first plurality of fins [right fin 804], a lower portion of the second plurality of fins [middle fin 804], a lower portion of the first gate endcap wall [821A], a lower portion of the second gate endcap wall [820 left], and a lower portion of the third gate endcap wall [820 right]; forming a first cap layer [899 right] on the first gate endcap wall [821A]; forming a second cap layer [899 left] on the second gate endcap wall [820 left]; and forming a local conductive interconnect [854] laterally between and in contact with the first cap layer [899 right] and the second cap layer [899 left], the local conductive interconnect [854] on the first gate stack [808 right] and the second gate stack [808 middle], and the local conductive interconnect [854] vertically over the third gate endcap wall [820 right]. PNG media_image7.png 447 634 media_image7.png Greyscale Hafez fails to explicitly disclose the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. However, it would be obvious that a plurality of fins comprises 2 or more fins. Hafez et al. discloses in Fig. 7D, paragraph [0047] that the first plurality of fins [702] comprises a first pair of fins; the second plurality of fins [704] comprises a second pair of fins. Webb et al. discloses in Fig. 7B the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. PNG media_image2.png 474 445 media_image2.png Greyscale It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to incorporate the teachings of Fig. 7D of Hefez et al. and Webb et al. into the device of Fig. 8A of Hafez et al. to include the first plurality of fins comprises a first pair of fins; the second plurality of fins comprises a second pair of fins. The ordinary artisan would have been motivated to modify Hafez et al. in the above manner for the purpose of providing suitable configuration of the first plurality of fins and the second plurality of fins. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SOPHIA T NGUYEN whose telephone number is (571)272-1686. The examiner can normally be reached 9:00am -5:00 pm, Monday-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, BRITT D HANLEY can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SOPHIA T NGUYEN/ Primary Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

Jun 26, 2024
Application Filed
Aug 25, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
45%
Grant Probability
59%
With Interview (+14.4%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 528 resolved cases by this examiner. Grant probability derived from career allowance rate.

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