Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the Amendment filed on 07/20/2026.
Claim Objections
Claims 1, 2, 9, 10, and 15 are objected to because of the following informalities: Regarding claim 1, in line 3, “the first current source” appears that it should read as “the current source”, because of antecedent basis. Regarding claim 2, in line 5, “the second transistor” appears that it should read as “the transistor”, because of antecedent basis.
Regarding claim 9, in line 6, “the second terminal of the capacitor” appears that it should read as “the transistor current terminal”, because of antecedent basis.
Regarding claim 10, in line 4, “the control terminals” appears that it should read as “the control terminal”;
in line 4, “the terminal of the second terminal” appears that it should read as “the second terminal”.
Regarding claim 15, in line 8, “the control terminal of the second transistor; and” appears that it should read as “the control terminal of the second transistor;”;
in line 14-15, “the terminal of the driver circuitry” appears that it should read as “the control terminal of the first transistor”, because of antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-12, and 15-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bau et al. (“CMOS Active Gate Driver for Closed-Loop dv/dt Control of GaN Transistors,” IEEE Transactions on Power Electronics, Vol. 35, No. 12, December 2020, pp. 13322-13332, hereinafter “Bau”). Regarding claim 1, Bau discloses (see Fig. 1) an apparatus comprising: driver circuitry having a terminal (the CMOS gate driver shown within the ASIC boundary, comprising the main stage driver and the dv/dt control loop, and having a terminal at the node at which the resistors RG and ROFF and the drain of M4 are coupled to the gate of the power transistor and through which the gate current iG flows), the driver circuitry including a current source and a current sink coupled to the terminal (the PMOS transistor M5, coupled to the terminal through the resistor RG, and the NMOS transistor M4, coupled to the terminal at its drain; see p. 13324, “The current buffer, also called the main stage driver, is composed of a P-type metal oxide semi-conductor (PMOS) transistor M5 and a N-type metal oxide semi-conductor (NMOS) transistor M6 used to source and sink the high gate currents, respectively.”), the first current source configurable to provide a first current to the terminal (M5 provides the current iRG to the terminal through the resistor RG), and the current sink configurable to sink a second current from the terminal (M4 sinks the feedback current iFB from the terminal; see p. 13324, “which is subtracted from the current iRG provided by the driver”), the current sink having a control terminal (the gate of M4); current mirror circuitry having an input and an output (M3, an NMOS transistor having its drain and gate tied together; the input is the drain of M3 and the output is the gate of M3), the output of the current mirror circuitry coupled to the control terminal of the current sink (the gate of M3 is coupled to the gate of M4); and a capacitor coupled between a transistor current terminal and the input of the current mirror circuitry (the sensing capacitor CS is coupled between the drain of the GaN power transistor, at which the voltage vDS appears, and the drain of M3 through the PMOS transistors M1 and M2) and configurable to set the second current via the current mirror circuitry responsive to voltage transition at the transistor current terminal (see p. 13323, “This feedback current iFB is proportional to the derivative of the power transistor voltage vDS, current gain G and the value of the capacitor CS acting as a dv/dt sensor”).
Regarding claim 2, Bau discloses (see Fig. 1) further comprising a transistor having the transistor current terminal and a control terminal (the GaN power transistor, having the drain at which the voltage vDS appears and having a gate), the control terminal of the second transistor coupled to the terminal of the driver circuitry (the gate of the GaN power transistor is coupled to the terminal of the driver circuitry through which the gate current iG flows).
Regarding claim 3, Bau discloses (see Fig. 1) wherein the current source is a first current source (M5), and the apparatus further comprises: a first transistor configurable as a second current source having a current terminal coupled to the input of the current mirror circuitry and a control terminal coupled to the capacitor (the PMOS transistor M2, having a width W2 equal to Gp times W1 and forming the output leg of a current mirror with M1 such that M2 conducts a current set by that current mirror; the drain of M2 is coupled to the drain of M3 and the gate of M2 is coupled to the capacitor CS at the node vinM); and a second transistor configurable as diode circuitry and coupled between a voltage supply terminal and the control terminal of the first transistor (the PMOS transistor M1, having its gate and drain tied together, coupled between the supply rail vDRV at its source and the gate of M2 at its drain).
Regarding claim 4, Bau discloses (see Fig. 1) wherein the current mirror circuitry includes a diode-connected third transistor (M3, an NMOS transistor having its drain and gate tied together).
Regarding claim 5, Bau discloses (see Fig. 1) wherein the current sink includes a fourth transistor having a control terminal coupled to a control terminal of the third transistor (M4, an NMOS transistor having a width W4 equal to Gn times W3, the gate of M4 being coupled to the gate of M3).
Regarding claim 6, Bau discloses (see Fig. 1) wherein the transistor is a gallium nitride (GaN) transistor (see p. 13324, “The capacitors CGD, CGS, and CDS are intrinsic to the GaN power transistor.”).
Regarding claim 8, Bau discloses (see Fig. 1) an apparatus comprising: a supply terminal (the supply rail vDRV); driver circuitry having a terminal (the CMOS gate driver shown within the ASIC boundary, having a terminal at the node at which the resistors RG and ROFF and the drain of M4 are coupled to the gate of the power transistor), the driver circuitry having a current source (the PMOS transistor M5 of the main stage driver, which provides the current iRG); diode circuitry having a first terminal and a second terminal (the PMOS transistor M1, having its gate and drain tied together; the first terminal is the source of M1 and the second terminal is the drain and gate of M1 at the node vinM); a capacitor coupled between a transistor current terminal and the second terminal of the diode circuitry (the sensing capacitor CS is coupled between the drain of the GaN power transistor and the node vinM); current mirror circuitry having a first terminal, a second terminal, and a third terminal (the PMOS transistor M2; the first terminal is the source of M2, the second terminal is the gate of M2, and the third terminal is the drain of M2), the first terminal of the current mirror circuitry coupled to the supply terminal and the first terminal of the diode circuitry (the source of M2 is coupled to the supply rail vDRV and to the source of M1), the second terminal of the current mirror circuitry coupled to the second terminal of the diode circuitry and the capacitor (the gate of M2 is coupled to the drain and gate of M1 and to the capacitor CS at the node vinM); and current scaling circuitry having a first terminal and a second terminal (the NMOS transistors M3 and M4; the first terminal is the drain of M4 and the second terminal is the drain and gate of M3), the first terminal of the current scaling circuitry is coupled to the terminal of the driver circuitry (the drain of M4 is coupled to the terminal at which the gate current iG flows to the gate of the power transistor), the second terminal of the current scaling circuitry is coupled to the third terminal of the current mirror circuitry (the drain and gate of M3 are coupled to the drain of M2), the current scaling circuitry configurable to sink a first current from the terminal of the driver circuitry (M4 sinks the feedback current iFB from the terminal), the first current being a scaled version of a second current provided by the capacitor (see p. 13323, “This feedback current iFB is proportional to the derivative of the power transistor voltage vDS, current gain G and the value of the capacitor CS acting as a dv/dt sensor”, and see p. 13324, “Due to the feedback current amplification through current mirrors, the sense capacitor CS can be downsized and further integrated on-chip.”; the current flowing through the capacitor CS is amplified by the gain Gp of the current mirror formed by M1 and M2 and by the gain Gn of the current mirror formed by M3 and M4, so that the current sunk by M4 is the product of the current through CS and the total gain G).
Regarding claim 9, Bau discloses (see Fig. 1) further comprising: a transistor having a first terminal and a control terminal (the GaN power transistor; the first terminal is the drain and the control terminal is the gate), the first terminal of the transistor coupled to the second terminal of the capacitor (the drain of the GaN power transistor is coupled to the drain-side terminal of the capacitor CS), the control terminal of the transistor coupled to the terminal of the driver circuitry and the first terminal of the current scaling circuitry (the gate of the GaN power transistor is coupled to the terminal of the driver circuitry and to the drain of M4).
Regarding claim 10, Bau discloses (see Fig. 1) wherein the diode circuitry is a transistor having a first terminal, a second terminal, and a control terminal (M1 is a PMOS transistor having a source, a drain, and a gate; the drain and gate of M1 are tied together), the first terminal of the transistor is coupled to the supply terminal and the first terminal of the current mirror circuitry (the source of M1 is coupled to the supply rail vDRV and to the source of M2), the second terminal and the control terminals of the transistor are coupled to the terminal of the second terminal of the current mirror circuitry (the drain and gate of M1 are tied together and coupled to the gate of M2).
Regarding claim 11, Bau discloses (see Fig. 1) wherein the current mirror circuitry is a transistor having a first terminal, a second terminal, and a control terminal (M2 is a PMOS transistor having a source, a drain, and a gate), the first terminal of the transistor is coupled to the supply terminal and the first terminal of the diode circuitry (the source of M2 is coupled to the supply rail vDRV and to the source of M1), the second terminal of the transistor is coupled to the second terminal of the current scaling circuitry (the drain of M2 is coupled to the drain and gate of M3), the control terminal of the transistor is coupled to the second terminal of the diode circuitry (the gate of M2 is coupled to the drain and gate of M1).
Regarding claim 12, Bau discloses (see Fig. 1) wherein the current mirror circuitry is first current mirror circuitry (M2), and the current scaling circuitry includes: a first transistor having a first terminal and a control terminal (M3; the first terminal is the drain of M3 and the control terminal is the gate of M3); and a second transistor having a first terminal and a control terminal (M4; the first terminal is the drain of M4 and the control terminal is the gate of M4), the first terminal of the second transistor is coupled to the terminal of the driver circuitry (the drain of M4 is coupled to the terminal at which the gate current iG flows), and the control terminal of the second transistor is coupled to the third terminal of the first current mirror circuitry, the first terminal of the first transistor, and the control terminal of the first transistor (the gate of M4 is coupled to the drain of M2, to the drain of M3, and to the gate of M3).
Regarding claim 15, Bau discloses (see Fig. 1) an apparatus comprising: a first transistor having a first terminal and a control terminal (the GaN power transistor; the first terminal is the drain and the control terminal is the gate); a capacitor having a first terminal and a second terminal (the sensing capacitor CS, having a drain-side terminal and a terminal at the node vinM), the first terminal of the capacitor coupled to the first terminal of the first transistor (the drain-side terminal of CS is coupled to the drain of the GaN power transistor); a second transistor having a first terminal and a control terminal (the PMOS transistor M1; the first terminal is the drain of M1 and the control terminal is the gate of M1, the drain and gate being tied together); current mirror circuitry having a first terminal and a second terminal (the PMOS transistor M2; the first terminal is the gate of M2 and the second terminal is the drain of M2), the first terminal of the current mirror circuitry is coupled to the second terminal of the capacitor, the first terminal of the second transistor, and the control terminal of the second transistor (the gate of M2 is coupled to the node vinM at which CS terminates, to the drain of M1, and to the gate of M1); and a current source coupled to the control terminal of the first transistor and configurable to provide a first current to the control terminal of the first transistor (the PMOS transistor M5 of the main stage driver, coupled to the gate of the GaN power transistor through the resistor RG and providing the current iRG); and current scaling circuitry having a first terminal and a second terminal (the NMOS transistors M3 and M4; the first terminal is the drain and gate of M3 and the second terminal is the drain of M4), the first terminal of the current scaling circuitry is coupled to the second terminal of the current mirror circuitry (the drain and gate of M3 are coupled to the drain of M2), the second terminal of the current scaling circuitry is coupled to the control terminal of the first transistor (the drain of M4 is coupled to the gate of the GaN power transistor), the current scaling circuitry configurable to sink a second current from the terminal of the driver circuitry (M4 sinks the feedback current iFB from the terminal at which the gate current iG flows), the second current being a scaled version of a third current provided by the capacitor (the current flowing through CS is amplified by the gain Gp of the mirror formed by M1 and M2 and by the gain Gn of the mirror formed by M3 and M4).
Regarding claim 16, Bau discloses (see Fig. 1) wherein the second transistor further has a second terminal (the source of M1), and the current mirror circuitry is a third transistor having a first terminal, a second terminal, and a control terminal (M2; the first terminal is the source of M2, the second terminal is the drain of M2, and the control terminal is the gate of M2), the first terminal of the third transistor is coupled to the second terminal of the second transistor (the source of M2 is coupled to the source of M1 at the supply rail vDRV), the second terminal of the third transistor is coupled to the first terminal of the current scaling circuitry (the drain of M2 is coupled to the drain and gate of M3), and the control terminal of the third transistor is coupled to the second terminal of the capacitor, the first terminal of the second transistor, and the control terminal of the second transistor (the gate of M2 is coupled to the node vinM at which CS terminates, to the drain of M1, and to the gate of M1).
Regarding claim 17, Bau discloses (see Fig. 1) wherein the current mirror circuitry is a first current mirror circuitry (M2), and the current scaling circuitry includes: a second current mirror circuitry having a first terminal and a second terminal (M3; the first terminal is the source of M3 and the second terminal is the drain and gate of M3); and a third transistor having a first terminal, a second terminal, and a control terminal (M4; the first terminal is the drain of M4, the second terminal is the source of M4, and the control terminal is the gate of M4), the first terminal of the third transistor is coupled to the control terminal of the first transistor (the drain of M4 is coupled to the gate of the GaN power transistor), the second terminal of the third transistor is coupled to the first terminal of the second current mirror circuitry (the source of M4 is coupled to the source of M3), and the control terminal of the third transistor is coupled to the second terminal of the first current mirror circuitry and the second terminal of the second current mirror circuitry (the gate of M4 is coupled to the drain of M2 and to the drain and gate of M3).
Regarding claim 18, Bau discloses (see Fig. 1) wherein the second current mirror circuitry is a fourth transistor having a first terminal, a second terminal, and a control terminal (M3; the first terminal is the drain of M3, the second terminal is the source of M3, and the control terminal is the gate of M3), the first terminal and the control terminal of the fourth transistor is coupled to the second terminal of the first current mirror circuitry, the second terminal of the second current mirror circuitry, and the control terminal of the third transistor (the drain and gate of M3 are tied together and coupled to the drain of M2 and to the gate of M4), and the second terminal of the fourth transistor is coupled to the second terminal of the third transistor (the source of M3 is coupled to the source of M4).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Bau in view of Seth et al. (US Patent Application Publication US 2008/0246512 A1, hereinafter “Seth”).
Regarding claim 7, Bau discloses (see Fig. 1) the sensing capacitor CS coupled between the drain of the GaN power transistor and the node vinM. Bau does not disclose wherein the capacitor has a larger capacitance than a gate-drain capacitance of the transistor.
However, Seth teaches (see Fig. 3) wherein the capacitor has a larger capacitance than a gate-drain capacitance of the transistor (the feedback capacitor Cp, coupled between the gate and the drain of the driver transistor MP2, and the feedback capacitor Cn, coupled between the gate and the drain of the driver transistor MN2, the drains of MP2 and MN2 being coupled to the output node Vout through the series switches MP3 and MN3; see [0026] of Seth, “the large feedback capacitors Cp and Cn”, and see [0044] of Seth, “The feedback capacitor needs to be much higher than the CGD capacitor value, so that the slew is controlled by the linear capacitance.”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Bau wherein the capacitor has a larger capacitance than a gate-drain capacitance of the transistor, as taught by Seth, because it can help ensure that the switching slew rate is controlled by the linear capacitance of the added capacitor rather than by the gate-drain capacitance of the transistor. Bau further discloses (see p. 13324) that “the feedback circuit acts like an active equivalent gate-drain capacitor placed in parallel with CGD equal to G × CS”, so that the capacitance of the capacitor is a result-effective variable that determines the extent to which the voltage slew rate is reduced, and it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claims 13, 14, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 13, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the current scaling circuitry further has a third terminal, and the apparatus further comprising a transistor having a first terminal and a second terminal, the first terminal of the transistor is coupled to the supply terminal, the first terminal of the diode circuitry, and the first terminal of the current mirror circuitry, the second terminal of the transistor is coupled to the third terminal of the current scaling circuitry.”.
Claim 14 is objected due to its dependency on claim 13.
Regarding Claim 19, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the second transistor further has a second terminal, the current mirror circuitry further has a third terminal, the current scaling circuitry further has a third terminal, and the apparatus further comprising a third transistor having a first terminal and a second terminal, the first terminal of the third transistor is coupled to the second terminal of the second transistor and the third terminal of the current mirror circuitry, the second terminal of the third transistor is coupled to the third terminal of the current scaling circuitry.”.
Claim 20 is objected due to its dependency on claim 19.
Response to Arguments
Applicant’s arguments filed on 07/20/2026 have been considered but are moot because the new ground of rejection necessitated by the amendment does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 2023/0223850 A1 discloses switching slew rate control for gate drivers using a feedback capacitor coupled to the drain terminal of a gallium nitride switching transistor.
US 2014/0125389 A1 discloses an edge rate control gate drive circuit in which a capacitive feedback element is coupled between the drain of an output transistor and the input of a PMOS current mirror.
US 10,938,381 B1 discloses a slew-rate controlled driver having a current-sensing transistor whose gate is capacitively coupled to the drain of an output transistor.
US 9,000,811 B2 discloses a driver circuit in which current mirrors scale a discharge current applied to the gate of a drive transistor in response to a sensed drain-to-source voltage.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838
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