DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: amendment & remarks filed on May 26, 2026.
This application has been examined. Claims 1-20 are pending.
Claim Interpretation - 35 U.S.C. § 112(f)
Claims 15-20 recite “means for obtaining,” “means for setting,” “means for estimating,” “means for mapping,” and “means for providing.” Because “means for” is not modified by structure-connoting language, these limitations invoke 35 U.S.C. § 112(f). The Specification discloses corresponding structure at ¶[0069] and FIG. 6: an obtaining component 605, a setting component 610, an estimating component 615, a mapping component 620, and a providing component 625, each of which “may be implemented at least in part in hardware or firmware” or “at least in part by a processor and software” (Spec ¶[0069]). Claims 15-20 are construed under § 112(f) using this structure (and equivalents thereof) in the prior-art mapping below. No rejection under 35 U.S.C. § 112(b) is applied, as the Specification discloses adequate corresponding structure for each recited function.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9, 15-16 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Lee et al. (“Lee”) (US Pub No. 2012/0016510).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Lee reference; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
Claim Construction - “different parts of the SoC”
Before mapping the claims to the art, the term “different parts of the SoC” (claims 1, 8, 15) is construed under its broadest reasonable interpretation, informed by the Specification. The Specification consistently uses “part” to mean an individually manufactured unit/instance of the SoC design that varies from other units due to semiconductor manufacturing process variation - not an internal functional subdivision such as “CPU” versus “GPU” versus “modem.” See Spec ¶[0018] (“the same SoC vote … are employed for all parts across the process distribution”; “higher-leakage parts … boot up with relatively higher power consumption”); ¶[0042] (same); ¶[0047] (“the SoC … may read … an Open Loop Voltage (OL) and … Quiescent Current (IDDQ) fuse … for one or more parts”); ¶[0048] (equation “PowerCPU,Part(mW)”, i.e., power computed per manufactured part); ¶[0054] (“the SoC may be partitioned into regions based on certain metrics … [t]he parts (and the corresponding CPU votes) may be grouped by regions”). Under this construction, “different parts of the SoC” reads on different individual manufactured instances of the claimed SoC design, each independently characterized and calibrated at its own boot-up using its own process/leakage data - in contrast to a conventional, uniform vote applied identically to every manufactured unit (Spec ¶[0018]). This construction is applied throughout the mapping below and directly addresses Applicant's principal traversal argument that the Lee passages cited in the prior action describe only “a single semiconductor device.” Under this construction, Lee's semiconductor device 20 is itself “a part,” and the claim's use of “different parts” reflects that Lee's method, like claim 1, is performed at boot by whichever manufactured device 20 (part) is executing it, using that device's own individually fused process/leakage data - as opposed to a fixed, device-independent value.
In regard to claim 1, Lee et al. disclose a method performed at a system-on-a-chip (SoC), comprising: obtaining parameters associated with estimated boot-up power consumption for different parts of the SoC (as shown in Fig. 4, which is reproduced below for ease of reference and convenience, Lee discloses a method performed by a semiconductor device described as a VLSI system or System on Chip (SoC). See Lee ¶ [0006] ("reducing power consumption of the VLSI system or SoC"), ¶ [0009] (semiconductor device 20 is a SoC), FIG. 4 (semiconductor device 20 comprising CPU 23, system bus 22, peripheral devices 29). Lee discloses obtaining parameters associated with estimated boot-up power consumption for different parts of the SoC (construed above):
Lee's data storage device 21 (fuses) stores, for the particular semiconductor device 20 under test (i.e., a “part” within the meaning above), data indicating the performance of that device - specifically its operational speed and leakage current (Lee ¶[0017], “[t]he performance of the semiconductor device includes the operational speed … or the leakage current …. The data … includes … information about the current of at least one of transistors embodied in the semiconductor device.”). The automatic test equipment (ATE) programs this device-specific data into the fuses during manufacture (Lee ¶¶[0031]-[0032] (ATE 2 tests semiconductor device 20 and programs the resulting performance data, including leakage current, into data storage device 21), [0035]-[0038]; FIG. 3), e.g., values ‘001,’ ‘010,’ or ‘011’ corresponding to leakage-current ranges of <1 mA, 1-2 mA, and 2-3 mA respectively for that specific device (Lee ¶[0038]).
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Lee does not expressly state that leakage current is a component of, or otherwise “drives,” power consumption - Lee's own background describes chip power consumption as “mostly dynamic power consumption” of the form Pd∝C_LVDD²fp (Lee ¶¶[0007]-[0008]), and ¶[0010] ties leakage current to operational speed, not power. It is nonetheless well understood in the art, and consistent with Applicant's own Specification - which computes a part's power directly from its fused leakage-current/IDDQ data, see Spec ¶¶[0047]-[0048] (“PowerCPU,Part(mW)” computed from fused IDDQ/OL data) - that leakage (static) current is a recognized contributor to a semiconductor device's total power consumption in addition to dynamic power, and that a higher-leakage part consumes more power at a given voltage/frequency than a lower-leakage part.
On this basis, a POSITA would have recognized Lee's per-device, fuse-programmed leakage-current data as being associated with that device's power consumption. Processor 23 reads and decodes this device-specific fuse data upon power application - i.e., at boot - before or as part of bringing the device into normal operation (Lee ¶[0048], “[t]he processor 23 … reads and decodes the data stored in the data storage device 21 … after the power is applied to the system 10 or the semiconductor device 20”; FIG. 4, data storage device 21 [Wingdings font/0xE0] processor 23). Because this data is unique to, and read from, the particular device being booted, and because leakage current is a recognized contributor to a device's power consumption (see above), this obtained, decoded fuse data constitutes a parameter associated with the estimated boot-up power consumption of that part of the SoC. Lee further discloses setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure, based on the corresponding parameters: immediately after decoding, the clock control block 25 adjusts the frequency of clock signal CLK, and the voltage generator 33 (via voltage control block 30) generates at least one level-controlled supply voltage VDD, both based on the decoded, device-specific performance data (Lee ¶¶[0050]-[0054] (“[t]he clock control block 25 may receive the decoded data output from the processor 23 … and control or adjust the frequency of the clock signal CLK”; “[t]he voltage generator 33 … generates at least one level-controlled supply voltage (VDD1, …, VDDm) … based on data relating to the performance … stored in the data storage device 21”); ¶¶[0059]-[0062] and FIG. 5, steps S20-S30 (processor decodes data (S20); clock control block controls clock frequency and voltage control block controls supply voltage and body-bias voltage, all based on the decoded data (S30)); FIG. 4 (clock control block 25, voltage control block 30, voltage generator 33)). This V/CLK setting occurs immediately following the power-on fuse read, i.e., during the boot-up procedure.
It would have been obvious to a person of ordinary skill in the art, at the time of filing, to characterize Lee's device-specific, power-on-read leakage/process data as a “parameter associated with estimated boot-up power consumption,” and Lee's immediately-following clock/voltage adjustment as “setting … during a boot-up procedure … based on the corresponding parameters,” because Lee's own disclosure already performs the substantive parameter-based voltage/frequency-setting operation, on a per-device basis, at power-on, using data (leakage current) that a POSITA would have recognized as a known contributor to power consumption, for the reasons given above. Characterizing this data using the claim's terminology does not require modifying Lee's structure or introducing a new technical teaching - it is the application of a known technique (fuse-based, per-device leakage characterization used to set boot-time voltage/frequency) that Lee already performs, articulated in the claim's terms; a POSITA would have had a reasonable expectation of success because Lee's own processor 23, clock control block 25, and voltage generator 33 already carry out each recited step. See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 416-17 (2007); MPEP § 2143(A), (G). This is provided as an articulated obviousness rationale in place of the conclusory “inherently associated” language used in the June 17, 2026 action, which Applicant correctly identified as insufficient under In re Kahn, 441 F.3d 977, 988 (Fed. Cir. 2006), and MPEP § 2142.
In regard to claims 2, 9, 16, Lee discloses wherein the parameters comprise at least one of open loop voltage or leakage current for the different parts (in Lee, expressly teaches that “[t]he performance of the semiconductor device includes the operational speed of the semiconductor device or the leakage current of the semiconductor device. The data, which is stored in the data storage device, includes … information about the current of at least one of transistors embodied in the semiconductor device” (Lee ¶[0017]); and that the ATE programs values (e.g., ‘001,’ ‘010,’ ‘011’) into the fuses corresponding to leakage-current ranges (<1 mA, 1-2 mA, 2-3 mA) (Lee ¶[0038]; FIG. 3; ¶[0032], ATE 2 programs leakage-current performance data into data storage device 21). Because claim 2 (and claims 9 and 16) recite the parameters in the alternative (“at least one of … or …”), Lee's disclosure of leakage current alone is sufficient).
In regard to claim 8, Lee discloses an apparatus for wireless communication at a system-on-a-chip (SoC), comprising: at least one memory comprising computer-executable instructions; and one or more processors configured to execute the computer-executable instructions and cause the apparatus to [obtain/set as in claim 1]. Lee's system 100/semiconductor device 20 (FIG. 1, FIG. 4) includes processor 23, which reads and decodes data from data storage device 21 and drives clock control block 25 and voltage generator 33, as detailed above for claim 1. The remaining limitations of claim 8 are rejected for the same reasons given for claim 1, which claim 8 recites in apparatus form.
In regard to claim 15, recites the same operative limitations as claim 1 in means-plus-function form (“means for obtaining …” and “means for setting …”), construed per the Claim Interpretation section above as corresponding to obtaining component 605 and setting component 610 (Spec ¶[0069], FIG. 6) and equivalents. Lee's processor 23, in reading and decoding the fuse data of data storage device 21 (Lee ¶[0048]), is structurally and functionally equivalent to the disclosed “means for obtaining”; Lee's clock control block 25 and voltage generator 33, in setting CLK and VDD based on the decoded data (Lee ¶¶[0050]-[0054]), are structurally and functionally equivalent to the disclosed “means for setting.” Claim 15 is therefore rejected for the same reasons given for claim 1.
5. Claims 3, 10, 17 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Lee in view of Ponnathota et al. (“Ponnathota”) (US Pub No. 2013/0311792).
The examiner relies on the entire teachings of Lee and Ponnathota references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 3, 10, and 17, which depend from claims 2, 9, and 16 and further recite estimating the boot-up power consumptions for the different parts based on the open loop voltages and the leakage currents obtained for the different parts (i.e., conjunctively requiring both an open-loop-voltage-type parameter and a leakage-current parameter to be obtained and used together - contrast the disjunctive recitation in claim 2) (Lee discloses estimating/classifying a part's performance from its fuse-programmed leakage-current data via a look-up table consulted by processor 23 (“[t]he processor 23 may include a lookup table LUT …. [T]he processor 23 may decode data displaying performance, such as clock frequency, maximum operable frequency, operational speed, or leakage current … referring to the LUT,” Lee ¶[0049]). Lee does not teach: estimating boot-up power consumption for a part using an open-loop-voltage parameter in combination with a leakage-current parameter for that same part. Lee's disclosed classification scheme relies on leakage-current/process-corner (fast/normal/slow) fuse data alone).
Lee does not teach: estimating boot-up power consumption for a part using an open-loop-voltage parameter in combination with a leakage-current parameter for that same part. Lee's disclosed classification scheme relies on leakage-current/process-corner (fast/normal/slow) fuse data alone; Lee does not separately obtain or use an open-loop voltage.
In the same field of endeavor (SoC power-supply voltage/frequency control accounting for manufacturing process variation), Ponnathota teaches estimating boot-up power consumption for a part using an open-loop-voltage parameter in combination with a leakage-current parameter for that same part and obtain or use an open-loop voltage ((as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Ponnathota teaches a controller 110 that controls a voltage regulator 114 supplying an SoC processor 105, based on target voltage values read from a look-up table (LUT) 140 (Ponnathota ¶¶[0072]-[0073]). Ponnathota expressly defines this LUT-based mode of control as “open loop control”: “[w]hen the controller 110 controls the voltage regulator 114 based only on target voltage values obtained from the LUT 140 without feedback information, this is referred to as open loop control,” as distinguished from feedback-based “closed loop control” - and Ponnathota further discloses using both together, i.e., a closed-loop, hybrid adaptive voltage scaling (AVS) scheme in which “open loop control can be used to drive the operating voltage to the target voltage value, and closed loop control can be used to optimize the operating voltage,” with “the target voltage values obtained from the LUT 140” being, e.g., “the worst case voltage for a particular frequency, temperature, and/or process” (Ponnathota ¶[0074]). This LUT-obtained, open-loop target voltage is indexed by process, in addition to frequency and temperature: Ponnathota's LUT 140 “store[s] operating parameters for different indexes corresponding to various combinations of frequencies, processes, and temperatures” (Ponnathota ¶[0118]; Table 1 (“Example of LUT memory structure”), entries Freq[9:0], Proc[1:0], Temp[1:0] mapped to a Voltage[7:0] field), and a dedicated configuration register, AVS_LUT_INDEX, “stores the {frequency, process, temperature}” index used to read the corresponding open-loop target-voltage entry from the LUT (Ponnathota ¶[0086]; Table 1 (“Examples of configuration registers”), AVS_LUT_INDEX register, address 0x14) - matching, essentially verbatim, the “[o]pen-loop voltage control of SoC power supply using [a] LUT indexed by {frequency, process, temperature}” description of this reference already of record in this application's file history. This LUT-based, process-indexed open-loop target voltage is the claimed open-loop-voltage-type parameter, obtained and used together with a leakage-current-type parameter of the kind Lee already discloses (see claim 2 mapping, above) to estimate the boot-up power consumption of a given part, as required by claim 3's conjunctive limitation).
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A person of ordinary skill in the art would have been motivated to combine Lee's leakage-current-based classification with Ponnathota's open-loop-voltage, process-indexed classification because both are known, art-recognized process-variation indicators used for the identical purpose of selecting a part-specific safe operating point, and combining two known per-part process indicators to refine a power estimate is the combination of known elements according to known methods to yield the predictable result of a more accurate, per-part power/voltage estimate. See KSR, 550 U.S. at 416; MPEP § 2143(A). A POSITA would have had a reasonable expectation of success because both references operate on the same class of hardware - fuse- or register-programmed, per-part characterization data consulted by boot-time hardware/firmware to set voltage - such that combining their respective process-variation inputs required no more than ordinary skill and predictable engineering.
5. Claims 4-5, 11-12, 18-19 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Lee in view of Ponnathota and further in view of Cheriyan et al. (“Cheriyan”) (US No. 9,933,827).
The examiner relies on the entire teachings of Lee and Ponnathota, and Cheriyan references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 4, 11,18, wherein setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure comprises:
mapping the estimated boot-up power consumptions to values (in Lee, teaches mapping decoded fuse data (leakage/process class) to voltage and frequency settings. Lee's processor 23 with LUT maps the performance bins to V/f operating points. See Lee ¶ [0035]-[0038], [0047]-[0052] and that the decoded/mapped value is provided to clock control block 25 and voltage generator 33, which set CLK and VDD accordingly (Lee ¶¶[0033]-[0038], [0050]-[0054]; FIG. 4). Lee and Ponnathota together, for the reasons given above for claim 3, teach the underlying open-loop-voltage-and-leakage-current-based estimating step from which the claim 4 mapping is performed.
Lee does not teach: a discrete “resource manager component”, separate from the initial per-part performance decode, that receives already-mapped power-consumption-derived values from (potentially) multiple parts/clients and independently sets voltage/frequency for those parts based on the received values. Lee's clock control block 25/voltage generator 33 operate directly on the decoded fuse data of a single device via a fixed data path, rather than via a distinct resource-manager component receiving mapped values. In the same field of endeavor, Cheriyan teaches providing the values to a resource manager component that sets the operating voltages and operating frequencies for the different parts during the boot-up procedure (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Cheriyan discloses a hybrid power management system 110 for an SoC device 100 comprising a Core Power Reduction (CPR) module 120 (hardware) and a CPR driver 132 (software) executing on a Resource and Power Management (RPM) processor 130 (Cheriyan, FIG. 1; col. 3-4, Detailed Description). Each of a plurality of subsystems 160-1 to 160-n sharing a power rail 140 “may periodically indicate a desired performance level to the CPR module 120 using a communication bus generally illustrated as a signal line 162,” after which “[t]he CPR module 120 aggregates these ‘votes’ to determine a final performance level and then provides that as an input to the RPM processor 130,” which “may then choose a power profile from the set of power profiles L1 to Ln 136 stored in the memory 134 … and set the power supply 170 to use a baseline voltage for that performance level” (Cheriyan, col. 6:63-7:6). The power profiles L1-Ln are themselves stored “in a memory 134 of the RPM processor 130” (col. 6:48-52), and the RPM processor 130 sets the power supply 170 to the selected voltage via control channel 142 (FIG. 1; col. 6:68-7:6). This RPM processor 130 - receiving aggregated, vote-derived performance-level values from the CPR module 120 and independently setting the operating voltage supplied to the subsystems/parts accordingly - is the claimed “resource manager component that sets the operating voltages and operating frequencies … based on … values” of claim 4. Cheriyan's own text describes this vote/profile-selection operation as occurring during an ongoing “active use state,” following a one-time “initialization phase” (col. 5:9-19), rather than expressly during device boot-up; the combination below relies on Lee, not Cheriyan, for the boot-up timing of this operation).
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A POSITA would have been motivated to combine Lee with Ponnathota for the reasons given above for claims 3, 10, and 17, and to further modify that combination by interposing Cheriyan's RPM/CPR vote-and-profile-selection architecture at Lee's already-disclosed boot-up decode point, because Cheriyan's architecture is a known, more scalable technique for managing voltage across multiple, potentially concurrently-operating SoC subsystems or parts (rather than a single fixed decode path), and applying a known centralized resource-management technique to the Lee/Ponnathota-based per-part power estimate, at the boot-up point Lee already discloses, would have yielded the predictable result of centralized, corner-based voltage/frequency management for the different parts at boot-up. See KSR, 550 U.S. at 416; MPEP § 2143(A). A POSITA would have had a reasonable expectation of success because all three references operate within the same SoC power-domain-control paradigm - device-specific performance/process data consulted by dedicated hardware/firmware to set voltage and frequency - such that supplementing the Lee/Ponnathota mapping with Cheriyan's RPM/vote mechanism, at the boot-up time Lee already establishes, is a predictable application of a known technique to a known device to improve it in the same way.
In regard to claims 5, 12, 19, wherein the values correspond to regions, each region defined by a range of boot-up power consumption (Lee discloses at least three power/process regions - fast process, normal process, and slow process - each corresponding to a leakage-current range and each assigned a different voltage/frequency combination (Lee ¶¶[0024]-[0025]), and Lee expressly ties leakage current to power-consumption differences (Lee ¶[0010]); Lee's regions are accordingly regions defined by ranges of (leakage-current-indicative) power consumption). Lee does not teach (or does not clearly teach): regions expressed as a corner/value abstraction consumed by a resource-manager component, as opposed to Lee's fixed three-way fast/normal/slow classification consumed directly by clock control block 25/voltage generator 33. Cheriyan teaches regions expressed as a corner/value abstraction consumed by a resource-manager component (Cheriyan discloses that “each design corner may include an operation voltage level, referred to as a ‘safe’ voltage level, at which components such as transistor devices in each of the sub-system 160-1 to 160-n are guaranteed to operate at an associated performance level” (Cheriyan, col. 5:38-45), and that the RPM processor 130 “allows clients to vote or request an operating condition specified by the SoC design, referred to herein as a ‘corner,’” after which the RPM “obtains the ‘safe’ voltages corresponding to the new corner requirement,” the safe voltage being “typically the lowest possible voltage at which all variants of an SoC device … may function at a specified corner” (col. 9:17-31). Cheriyan further discloses that a discrete number of such corners/profiles - power profiles L1 to Ln 136, “where n is a number of performance levels supported by the SoC device 100” (col. 6:48-52) - are stored and selected from as a set. Each corner/profile of Cheriyan's L1-Ln set, indexed to a defined performance level and an associated safe-voltage value, is a region defined by a range of (voltage/performance-level-indicative) per-part operating characteristics mapped to a value, analogous to the claimed “region … defined by a range of boot-up power consumption”).
A POSITA would have been motivated to combine Lee's multi-region (fast/normal/slow) leakage classification, as already combined with Ponnathota (claims 3, 10, 17) and Cheriyan (claims 4, 11, 18), with Cheriyan's corner-indexed, safe-voltage region framework for the same reasons given for claims 4, 11, and 18, above - the combination is the predictable application of Cheriyan's known corner/region abstraction, applied at Lee's already-disclosed boot-up decode point, to the Lee/Ponnathota-based, power-consumption-indicative region classification, with a reasonable expectation of success because all three references operate on the same type of per-part process/performance data.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
6. Claims 6-7, 13-14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The Examiner's statement of reasons can be found in the previous Office Action.
Response to the Arguments
The Non-Final Office Action mailed 06/17/2026 identified the secondary reference applied to claims 3-5, 10-12, and 17-19 inconsistently - citing it as “US No. 9,993,827,” referring to it as “Abhishek,” and twice attributing teachings to “Garg,” a reference not of record. Applicant correctly flagged this in the September 1, 2026. Remarks and requested identification with particularity under 37 C.F.R. § 1.104(c)(2). This has been run down and the full reference text obtained and reviewed: the reference of record, consistent with the PTO-892 and with Applicant's own citation, is Cheriyan et al., US 9,933,827 B2 (“Method and Apparatus for Hybrid Chip-Level Voltage Scaling,” issued Apr. 3, 2018, assigned to Qualcomm Incorporated; inventors Ajay Cheriyan, Rajesh Joshi, and Madan Krishnappa; from Appl. No. 13/771,064, filed Feb. 19, 2013). The names “Abhishek” and “Garg” and the number 9,993,827 do not correspond to any reference of record here and should not be carried forward. All citations above use the correct reference, Cheriyan (US 9,933,827 B2), with column:line citations drawn directly from the reference as filed. Important scope correction: having now reviewed the full Cheriyan text, the terms “open loop voltage,” “boot,” “boot-up,” and “power-on” do NOT appear anywhere in Cheriyan. Cheriyan's disclosure is directed to dynamic corner/voltage management during an ongoing “active use state” (initialized once via an “initialization phase,” col. 5:9-19), not to characterizing or setting voltage/frequency specifically during device boot-up, and it does not disclose an open-loop-voltage parameter at all. Cheriyan therefore cannot properly support the “open loop voltage” limitation of claims 3, 10, and 17 (see the revised mapping for those claims, below, which substitutes Ponnathota et al., US 2013/0311792 A1, disclosing open-loop voltage control of an SoC power supply using a look-up table indexed by frequency, process, and temperature; see Ponnathota ¶¶[0074], [0086], [0118], cited in full above). Cheriyan remains well-suited, to supply the “resource manager component” / “vote” / “region-value” structure for claims 4-5, 11-12, and 18-19 - which, because those claims depend from claims 3, 10, and 17, are rejected as Lee in view of Ponnathota, further in view of Cheriyan, rather than Lee in view of Cheriyan alone, so that the open-loop-voltage-based limitation carried down from claim 3 remains accounted for.
Applicant's arguments have been fully considered. As discussed in the claim-by-claim analysis above, the rejections of claims 1-5, 8-12, and 15-19 are maintained, with the claim construction and articulated rationale clarified in response to Applicant's arguments.
Conclusion
8. Claims 1-5, 8-12, 15-19 are rejected. Claims 6-7, 13-14, 20 are objected.
9. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Titiano and Qasem, US 8,327,158, disclose a hardware voting mechanism arbitrating a shared supply voltage among multiple processor cores' voltage requests, and AVS “used at boot time to adapt … voltage to device process characteristics (strong/weak).” Also pertinent as background on multi-client voltage-vote arbitration relevant to claims 4-5, 11-12, 18-19.
Mallik et al., US 7,913,071, disclose “Process-Driven Voltage Scaling”: derives an individual, per-chip voltage profile from offline process-variation profiling, expressly noting the profiling “may be performed as part of system startup and/or power-on.”
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
