DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This application has been examined. Claims 1-20 are pending.
The Group and/or Art Unit location of your application in the PTO has changed. To aid in correlating any papers for this application, all further correspondence regarding this application should be directed to Group Art Unit 2175.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8, 15 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by Bergsagel et al. (US Pub No. 2025/0028835).
In regard to claims 1, 8, 15, Bergsagel et al. disclose an apparatus, a method performed at a system-on-a-chip (SoC), comprising: at least one memory comprising computer-executable instructions (¶ 62-63, 80); and one or more processors configure to execute the computer-executable instructions (claim 9) and cause the apparatus to: obtaining parameters associated with estimated boot-up power consumption for different parts of the SoC (as shown in Fig. 5, which is reproduced below for ease of reference and convenience, Bergsagel discloses the step of provide (or receive) an operational conditions hint data (a hint data) of the SoC. In some examples, operational conditions hint data is user-generated, or is generated by an automated process. Operational conditions hint data includes, for example, clock and power control information of the SoC, such as bypass mode frequency and nominal mode frequency information for PLLs, power supply information, and functional block clock frequency and power supply requirements. Accordingly, in some examples, operational conditions hint data includes clock frequency and power supply requirements for peripherals, resources, and interfaces. See ¶ 60-64);
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and setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure, based on the corresponding parameters (in Bersgasel, operational data includes data structures that represent which circuits to enable (in some examples, in what order), including which clock circuits and power supply circuits to enable, and how to configure clock circuits and power supply circuits to be enabled, when a firmware (or other executed code) processes a request to enable specified peripherals, such as peripherals specified in the devgroup. In some examples, an order in which to enable circuits corresponds to clock and power supply hierarchies described by the component description. Information related to enabling and configuring clock circuits is referred to herein as clock information, and information related to enabling and configuring power supply circuits is referred to herein as power supply information. See ¶ 64-69).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 9-10, 16-17 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Bergsagel et al. in view of Anderson et al. (US Pub No. 2015/0169382).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Bergsagsel and Anderson references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 2, 9, 16, Bergsagel et al. disclose the claimed subjected matter as discussed above rejection except the teaching of wherein the parameters comprise at least one of open loop voltage or leakage current for the different parts. In the same field of endeavor, Anderson et al. teach that the built-in self test to collect the current leakage data from the selected processor cores and then save the self test data in the non-volatile memory accessible by the processor and may enable this information to be used at boot time (as shown in Fig. 1, which is reproduced below for ease of reference and convenience, Anderson discloses the built in self test may provide a workload for the selected processor cores to execute so that the processor may collect thermal output and current leakage data from the selected processor cores that are relevant for calculating priorities for the processor cores. The self test data may be stored in nonvolatile memory accessible by the processor, such as the nonvolatile memory used to store collected operational data in block 507. Storing the self test data in non-volatile memory may enable this information to be used at boot time to set initial processor core priorities and mappings. The processor may also retrieve the operating time data for the selected processor cores as part of collecting the built in self test data. The processor may calculate priorities for each of the selected processor cores based on the collected operation data and operating history. See ¶ 62-65).
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It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Bergsagel et al. to include the collection of current leakage of the selected processor core, as taught by Anderson et al., in order to optimize runtime of multi-core system designs for increased operating life and maximized performance.
In regard to claims 3, 10, 17, Anderson et al. disclose further: estimating the boot-up power consumptions for the different parts based on the open loop voltages and the leakage currents obtained for the different parts (in Anderson, the processor may calculate priorities for each of the selected processor cores based on the collected operation data and operating history. The collected operation data may include the boot-up power consumption for the selected processor cores. See ¶ 64-68). It would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to a person having ordinary skill in the art to modify the teaching of Bergsagel et al. to include the collection of current leakage of the selected processor core, as taught by Anderson et al., in order to optimize runtime of multi-core system designs for increased operating life and maximized performance.
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
Claims 4-7, 11-14, 18-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 4, 11, 18 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure comprises: mapping the estimated boot-up power consumptions to values; and providing the values to a resource manager component that sets the operating voltages and operating frequencies for the different parts during the boot-up procedure.
Conclusion
Claims 1-3, 8-10, 15-17 are rejected. Claims 4-7, 11-14, 18-20 are objected.
The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Toosizadeh et al. (US Pub No. 2017/0068309) disclose a method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.
Zhang et al. (US No. 11,847,471) disclose a method includes receiving configuration data associated with a PLD. The PLD includes an array of configuration memory cells including logic block memory cells and input/output (I/O) block memory cells associated with the PLD's logic fabric and I/O fabric, respectively. The method further includes programming a subset of the I/O block memory cells with the configuration data, and providing a wakeup signal to activate functionality associated with a portion of the I/O fabric. The method further includes programming remaining configuration memory cells of the array with the configuration data, where the remaining configuration memory cells include at least a subset of the logic block memory cells.
Rajwan et al. (US Pub No. 2023/0077747) disclose a control circuitry controls the voltage regulators to supply a setting of the voltages. The circuitry adaptively activates and deactivates power stages by ensuring that a number of active power stages is set to a predefined partial number only while the setting matches one of safe settings.
Sharma et al. (US Pub No. 2021/0064383) disclose the method involves determining a criticality value for each subsystem based on the subsystem image size, selecting a loading characteristic where subsystem images are read from memory using segment read scheduling.
Messick et al. (US Pub No. 2020/0073463) disclose the systems and methods for reduced boot power consumption using early BIOS controlled CPU power states to enhance power budgeting and allocation. An information handling system may include a server. The server may include a central processing unit (CPU), a memory, a non-volatile random-access memory (NVRAM) device, a performance state (P-state) limiting indicator stored in the NVRAM device, a P-state value stored in the NVRAM, and a basic input/output system (BIOS) stored in the memory.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175