DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: amendment & remarks filed on May 26, 2026.
This application has been examined. Claims 1-20 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art t which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-9, 15-16 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Lee et al. (“Lee”) (US Pub No. 2012/0016510).
In order to expedite and avoid piecemeal prosecution, the following rejection is made to the extent that the claims are understood, by considering those elements which are understood and interpreting their function in a manner which is consistent with the recited goals of the claims, and then applying the best available art.
The examiner relies on the entire teachings of Lee reference; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claim 1, Lee et al. disclose a method performed at a system-on-a-chip (SoC), comprising: obtaining parameters associated with estimated boot-up power consumption for different parts of the SoC (as shown in Fig. 4, which is reproduced below for ease of reference and convenience, Lee discloses a method performed by a semiconductor device described as a VLSI system or System on Chip (SoC). See Lee ¶ [0006] ("reducing power consumption of the VLSI system or SoC"), ¶ [0009] (semiconductor device 20 is a SoC), FIG. 4 (semiconductor device 20 comprising CPU 23, system bus 22, peripheral devices 29). Lee teaches obtaining parameters stored in a data storage device 21 (fuses) that indicate the performance (i.e., specifically leakage current and operational speed) of the semiconductor device. After power is applied (i.e., at boot-up), "[t]he processor 23...reads and decodes the data stored in the data storage device 21 through a system bus 22 after the power is applied to the system 10 or the semiconductor device 20." See Lee ¶ [0035] (reading fuse data post-power-on), ¶ [0033]-[0035] (fuse values '001' / '010' / '011' correspond to leakage current ranges <1 mA, 1–2 mA, 2–3 mA), ¶ [0024] (data indicates whether part was produced by fast/normal/slow process), FIG. 4 (data storage device 21 → processor 23). The leakage current and process corner data serve as the parameters associated with estimated power consumption, because Lee explicitly states that leakage current drives power consumption differences across parts (¶ [0010]);
PNG
media_image1.png
878
677
media_image1.png
Greyscale
and setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure, based on the corresponding parameters (in Lee teaches that, after decoding the fuse data obtained at power-on (boot-up), the clock control block 25 and the voltage control block 30 set, respectively, the operating frequency and supply voltage: "[t]he clock control block 25 may receive the decoded data output from the processor 23...and control or adjust the frequency of the clock signal CLK" and "[t]he voltage generator 33...generates at least one level-controlled supply voltage (VDD1,...,VDDm)...based on data relating to the performance...of the semiconductor device 20 stored in the data storage device 21." See Lee ¶¶ [0033]–[0038]; [0050]-[0054] (clock control block 25 adjusts CLK; voltage generator 33 adjusts VDD); ¶ [0046] (FIG. 5 step S30: control block controls frequency/voltage/body-bias); FIG. 4 (clock control block 25, voltage control block 30, voltage generator 33). The setting of voltage/frequency occurs immediately following power-on fuse read, squarely during the boot-up procedure. Lee's power-on fuse read and V/f setting is the boot-up procedure, the claim doesn't import the thermal motivation from the specification into the claim language, and the steps recited in claim 1 read directly on Lee's power-on sequence).
While Lee discloses all structural and functional elements recited in claim 1, Lee does not expressly characterize the fuse-stored leakage current and process-variation data as 'parameters associated with estimated boot-up power consumption,' nor does Lee frame the voltage/frequency setting step as specific to a 'boot-up procedure' for thermal mitigation purposes. It would have been obvious to a person of ordinary skill in the art to recognize that Lee's fuse-read, power-on voltage/frequency setting constitutes obtaining and using parameters associated with estimated boot-up power consumption, as the leakage current data read at power-on is inherently associated with the power consumption of the part during boot-up.
In regard to claims 2, 9, 16, Lee discloses wherein the parameters comprise at least one of (in Lee, explicitly teaches that the data stored in the fuses includes leakage current of the transistors embodied in the semiconductor device: "The performance of the semiconductor device includes the operational speed of the semiconductor device or the leakage current of the semiconductor device. The data, which is stored in the data storage device, includes...information about the current of at least one of transistors embodied in the semiconductor device." See Lee ¶ [0017] (summary: 'leakage current of the semiconductor device'), ¶ [0036]-[0038] (ATE programs '001'/'010'/'011' based on leakage current ranges: '<1 mA,' '1–2 mA,' '2–3 mA'), ¶ [0031] (data storage device 21 stores leakage current data), FIG. 3 (ATE programs leakage current data into fuses). Lee thus teaches that the parameters are the fuse-stored leakage current values.
Independent claims 8 (apparatus for wireless communication at a system on a chip (system)) and 15 (apparatus) recite the same operative limitations as method claim 1 in system and apparatus form respectively. Lee discloses a computer system (FIG. 1, element 100) comprising a processor (CPU 23) and memory (data storage device 21) that perform the identical operations. The method/system/apparatus distinction does not impart patentability where the underlying operative steps are the same. See MPEP § 2114.
Therefore, claims 8 and 15 are rejected on the same basis and mapping as claim 1 above.
5. Claims 3-5, 10-12, 17-19 are rejected under AIA 35 U.S.C. § 103 as being unpatentable over Lee et al. (“Lee”) in view of Cheriyan et al. (“Cheriyan”) (US No. 9,993,827).
The examiner relies on the entire teachings of Lee and Cheriyan references; the applicant should carefully consider the entire teachings of the above-mentioned references to better understand the examiner’s position.
In regard to claims 3, 10, 17, Lee discloses further: estimating the boot-up power consumptions for the different parts based on the open loop voltages and the leakage currents obtained for the different parts (in Lee, teaches that the processor 23 reads and decodes fuse data representing the leakage current and/or operational speed of the semiconductor device and outputs decoded data used to set voltage and frequency. Lee's processor 23 includes a look-up table (LUT): "The processor 23 may include a lookup table LUT (not shown). Accordingly, the processor 23 may decode data displaying performance, such as clock frequency, maximum operable frequency, operational speed, or leakage current...referring to the LUT." See Lee ¶ [0047]-[0052]. The decoded fuse data (leakage current bins) thus serves as an estimate of the device's power consumption class. Lee does not explicitly disclose a separate 'estimating' step that mathematically computes or estimates an absolute boot-up power consumption value for each part using both open loop voltage and leakage current in combination via a formula (e.g., the Power_CPU, Part equation of the instant application). Lee teaches parts into fast/normal/slow process categories using leakage current alone, without an explicit power estimation formula combining both OL voltage and IDDq. In the same field of endeavor, Cheriyan discloses the estimating power using both Open Loop (OL) voltage and leakage current as inputs (as shown in Fig. 2, which is reproduced below for ease of reference and convenience, Cheriyan discloses that the SoC evaluates an 'open-loop voltage' for the CPU at boot time to determine the safe corner voltage. Cheriyan discloses that the RPM uses a safe voltage table (LUT) indexed by corner (process class), and that the CPR module may use voltage margin data from manufacturing. The combination of leakage current (from Lee) and open-loop voltage (from Cheriyan) to estimate per-part boot-up power and select a voltage operating point would be obvious to a skilled artisan to achieve a finer-grained power estimation, as combining these two known process-variation indicators is a predictable optimization. See Cheriyan Col. 6:53-8:6 (open-loop voltage, process corner relationship); Col. 8:26-50 (safe voltage LUT); FIG. 2 (per-part process variation vs. voltage).
PNG
media_image2.png
887
678
media_image2.png
Greyscale
A POSITA would have been motivated to combine these references because both address the same problem that managing power consumption variations due to process corners/leakage in SoCs and applying Garg's fuse-based process data and Cheriyan's dynamic estimation and profile adjustment techniques specifically to estimate part-specific boot-up power (using OL voltage and IDDq/leakage) is a predictable, straightforward improvement. Boot-up is a well-known high-power transient phase where such estimation provides clear benefits in reducing unnecessary power draw and skin temperature rise, as recognized in the field. The combination yields no more than the predictable result of better-tailored V/F settings.
In regard to claims 4, 11,18, wherein setting at least one of operating voltages or operating frequencies for the different parts during a boot-up procedure comprises:
mapping the estimated boot-up power consumptions to values (in Lee, teaches mapping decoded fuse data (leakage/process class) to voltage and frequency settings. Lee's processor 23 with LUT maps the performance bins to V/f operating points. See Lee ¶ [0035]-[0038] (processor 23 decodes fuse data [Wingdings font/0xE0] clock control block 25 + voltage generator 33 set V and f).
and providing the values to a resource manager component that sets the operating voltages and operating frequencies for the different parts during the boot-up procedure (in Lee also discloses three power/process regions: fast process, normal process, slow process (¶ [0024]-[0025]), each assigned a different voltage/frequency combination. Lee does not teach: a resource manager component receiving per-part vote values; named corner vote values per region. In the same field of endeavor, Cheriyan discloses the Resource Power Manager (RPM) as resource manager receiving vote values (corners) per power region and setting PMIC CPU rail voltage (in Cheriyan, explicitly discloses a Resource Power Manager (RPM) which identified as a 'resource manager' that receives corner vote requests from SoC subsystem clients, maps each corner to a safe voltage using a LUT, and programs the PMIC supply rail. "[T]he RPM processor allows clients to vote or request an operating condition specified by the SoC design, referred to herein as a 'corner'." The corners include Turbo, Nominal (Nom), SVS, etc. The RPM selects the highest-voted corner, maps it to a voltage via a statically available safe-voltage table, and programs the power supply. See Abhishek Col. 3:1–45 (RPM, corners, voting); Col. 4:20–55 (LUT mapping corners to voltages); Col. 5:35–65 (PMIC programming by RPM); FIG. 1 (SoC subsystems → RPM/resource manager → power supply/PMIC). A POSITA would have been motivated to combine these because both references are directed to the same technical field (SoC power management accounting for process/leakage variations) and solve the closely related problem of excessive power draw due to process corners. Mapping estimated power (from Garg + Cheriyan's estimation techniques) into discrete regions/values and feeding them to a resource manager for V/F setting during boot-up represents a predictable application of known power-profile techniques to the known boot-time context. This yields the expected benefit of more precise, part-specific control that reduces unnecessary power/heat in high-leakage parts without sacrificing functionality that precisely the type of improvement routinely pursued in SoC design for thermal/power-constrained devices (e.g., XR headsets).
In regard to claims 5, 12, 19, wherein the values correspond to regions, each region defined by a range of boot-up power consumption (in Cheriyan, explicitly discloses a Resource Power Manager (RPM) which identified as a 'resource manager' that receives corner vote requests from SoC subsystem clients, maps each corner to a safe voltage using a LUT, and programs the PMIC supply rail. "[T]he RPM processor allows clients to vote or request an operating condition specified by the SoC design, referred to herein as a 'corner'." The corners include Turbo, Nominal (Nom), SVS, etc. The RPM selects the highest-voted corner, maps it to a voltage via a statically available safe-voltage table, and programs the power supply. See Abhishek Col. 3:1–45 (RPM, corners, voting); Col. 4:20–55 (LUT mapping corners to voltages); Col. 5:35–65 (PMIC programming by RPM); FIG. 1 (SoC subsystems → RPM/resource manager → power supply/PMIC). A POSITA would have been motivated to combine these because both references are directed to the same technical field (SoC power management accounting for process/leakage variations) and solve the closely related problem of excessive power draw due to process corners. Mapping estimated power (from Garg + Cheriyan's estimation techniques) into discrete regions/values and feeding them to a resource manager for V/F setting during boot-up represents a predictable application of known power-profile techniques to the known boot-time context. This yields the expected benefit of more precise, part-specific control that reduces unnecessary power/heat in high-leakage parts without sacrificing functionality that precisely the type of improvement routinely pursued in SoC design for thermal/power-constrained devices (e.g., XR headsets).
Examiner's note:
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the Applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the Applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passages as taught by the prior art or disclosed by the Examiner.
Allowable Subject Matter
6. Claims 6-7, 13-14, 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
7. The following is an Examiner's statement of reasons for the indication of allowable subject matter: Claims 6-7, 13-14, 20 are allowable over the prior art of record because the prior arts, cited in its entirety, or in combination, do not teach
wherein mapping the estimated boot-up power consumptions to values comprises: for each different part, mapping the estimated boot-up power consumption for that part to one of the regions (claims 6, 13, 20);
wherein: each region has a corresponding vote value; and providing the values to the resource manager component comprises providing the vote values to the resource manager component (claims 7, 14);
Conclusion
8. Claims 1-5, 8-12, 15-19 are rejected. Claims 6-7, 13-14, 20 are objected.
9. The prior arts made of record and not relied upon are considered pertinent to applicant's disclosure.
Ponnathota et al. (US Pub No. 2013/0311792) disclose the Open-loop voltage control of SoC power supply using LUT indexed by {frequency, process, temperature}; closed-loop hybrid AVS.
Gulati et al. (US No. 9,659,616) disclose a Fuse-based SoC power configuration with power manager (PMGR) reading fuses 26 at boot-up and controlling power rails via PMU 15.
Lai et al. (US No. 11,579,643) disclose the AVS scanning during boot code execution; SoC establishes voltage-frequency LUT during boot phase.
Shi et al. (US No. 8,909,999) disclose the dynamic voltage scaling using open-loop LUT indexed by frequency and process variation; SoC-level voltage/frequency control.
Kang et al. (US No. 7,583,555) disclose the performance manager sets V and f to minimum needed for impending task; process-variation-aware voltage reduction for faster parts.
Zhu et al. (US No. 9,223,327) disclose the universal AVS system for SoC using delay-line based PVT sensing; Qualcomm context, adaptive voltage per process corner.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to examiner Raymond Phan, whose telephone number is (571) 272-3630. The examiner can normally be reached on Monday-Friday from 6:30AM- 3:00PM. The Group Fax No. (571) 273-8300.
Communications via Internet e-mail regarding this application, other than those under 35 U.S.C. 132 or which otherwise require a signature, may be used by the applicant and should be addressed to [raymond.phan@uspto.gov].
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew Jung can be reached at (571) 270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
All Internet e-mail communications will be made of record in the application file. PTO employees do not engage in Internet communications where there exists a possibility that sensitive information could be identified or exchanged unless the record includes a properly signed express waiver of the confidentiality requirements of 35 U.S.C. 122. This is more clearly set forth in the Interim Internet Usage Policy published in the Official Gazette of the Patent and Trademark on February 25, 1997 at 1195 OG 89.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see hop://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
Any inquiry of a general nature or relating to the status of this application should be directed to the TC 2100 central telephone number is (571) 272-2100.
/RAYMOND N PHAN/
Primary Examiner, Art Unit 2175
Prosecution Insights