DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8 and 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hwang et al. (US PG-Pub No.: 2019/0206969 A1, hereinafter, “Hwang”).
Regarding claim 1, Hwang discloses a display pixel (see Hwang, FIG. 12) configured to emit light in a first direction (up-down), the display pixel comprising:
a substrate (110, FIG. 12);
a first transistor (T1, FIG. 12) that is formed on the substrate (110);
a first planarization layer (162, FIG .12) that overlaps the first transistor (T1) in the first direction (up-down);
a component (Cst, FIG. 12) that overlaps the first transistor (T1) in the first direction (up-down), wherein the component (Cst) comprises a component selected from the group consisting of: a capacitor (FIG. 12) and a transistor;
a second planarization layer (168+180, FIG. 12) that overlaps the component (Cst) in the first direction (up-down); and
an anode (191, ¶ [0143]) that overlaps the first transistor (T1) and the component (Cst) in the first direction (up-down, FIG. 12).
Regarding claim 2, Hwang discloses the display pixel defined in claim 1, wherein the component (Cst) is the capacitor (FIG. 12).
Regarding claim 3, Hwang discloses the display pixel defined in claim 2, wherein the capacitor (Cst) comprises first and second electrodes (155a+178, FIG .12).
Regarding claim 4, Hwang discloses the display pixel defined in claim 3, wherein the capacitor (Cst) comprises first and second dielectric layers (162+163, ¶ [0127]) between the first and second electrodes (155a+178), wherein the first dielectric layer (162) has a greater dielectric constant than the second dielectric layer (163, ¶ [0127]).
Regarding claim 5, Hwang discloses the display pixel defined in claim 4, wherein the first dielectric layer (162) has a first dielectric constant that is greater than 10 (¶ [0127]) and wherein the second dielectric layer (163) has a second dielectric constant that is between 1.5 and 10 (¶ [0127]).
Regarding claim 6, Hwang discloses the display pixel defined in claim 4, wherein the capacitor (Cst) further comprises a third dielectric layer (161) between the first and second electrodes (155a+178), wherein the second and third dielectric layers (161+163) are formed from a same material (¶ [0127]), and wherein the first dielectric layer (162) is interposed between the second and third dielectric layers (161+163, FIG. 12).
Regarding claim 7, Hwang discloses the display pixel defined in claim 4, wherein the first dielectric layer (162) comprises a material selected from the group consisting of: aluminum oxide, hafnium oxide, titanium oxide (¶ [0128]).
Regarding claim 8, Hwang discloses the display pixel defined in claim 3, wherein the capacitor (Cst) further comprises a third electrode (191, FIG. 12).
Regarding Claim 16, Hwang discloses the display pixel defined in claim 1, further comprising: a light-emitting diode (LD, FIG. 12) that comprises the anode (191).
Claims 1, 9, and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ji et al. (US PG-Pub No.: 2020/0135089 A1, hereinafter, “Ji”).
Regarding claim 1, Ji discloses a display pixel (see Ji, FIG. 5) configured to emit light in a first direction (up-down), the display pixel comprising:
a substrate (110, FIG. 5);
a first transistor (Tec, FIG. 5) that is formed on the substrate (110);
a first planarization layer (CIL, FIG .5) that overlaps the first transistor (Tec) in the first direction (up-down);
a component (Tdr, FIG. 5) that overlaps the first transistor (Tec) in the first direction (up-down), wherein the component (Tdr) comprises a component selected from the group consisting of: a capacitor and a transistor (FIG. 5);
a second planarization layer (ILD3, FIG. 5) that overlaps the component (Tdr) in the first direction (up-down); and
an anode (AE, FIG. 5) that overlaps the first transistor (Tec) and the component (Tdr) in the first direction (up-down, FIG. 5).
Regarding claim 9, Ji discloses the display pixel defined in claim 1, wherein the component (Tdr) is the transistor and wherein the transistor is a second transistor (FIG. 5).
Regarding claim 11, Ji discloses the display pixel defined in claim 9, further comprising: a capacitor (Cst, FIG. 5) that overlaps the second transistor (Tdr) in the first direction (up-down), wherein the capacitor (Cst) is interposed between the second transistor (Tdr) and the second planarization layer (ILD3, FIG. 5).
Regarding claim 12, Ji discloses the display pixel defined in claim 9, further comprising: a capacitor (Cst, FIG. 5) that overlaps the second transistor (Tdr) in the first direction (up-down), wherein the second planarization layer (to meet this limitation, the second planarization layer is CIL and the first planarization layer is ILD3) is interposed between the capacitor (Cst) and the second transistor (Tdr, FIG. 5).
Regarding claim 13, Ji discloses the display pixel defined in claim 12, further comprising: a third planarization layer (PL, FIG. 5) that overlaps the capacitor (Cst) in the first direction (up-down), wherein the third planarization layer (PL) is interposed between the anode (AE) and the capacitor (Cst, FIG. 5).
Claims 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xu et al. (US PG-Pub No.: 2022/0102460 A1, hereinafter, “Xu”).
Regarding claim 17, Xu discloses a display pixel (see Xu, FIGs. 1-2) comprising:
a first power supply terminal (VDD, FIG. 1);
a second power supply terminal (VSS, FIG. 1);
a light-emitting diode (61-63, FIGs. 1-2);
a drive transistor (T2, FIG. 1), wherein the drive transistor (T2) and the light-emitting diode (61-63) are connected in series between the first and second power supply terminals (VDD+VSS, FIGs. 1-2);
a switching transistor (T1, ¶ [0095]) that is connected to a gate of the drive transistor (T2, FIG. 1);
a substrate (10, FIG. 2A);
a first deck on the substrate (10) that includes the switching transistor (T1) and a first planarization layer (15, ¶ [0141]) that overlaps the switching transistor (T1); and a second deck on the first deck that includes the drive transistor (T2) and a second planarization layer (16, ¶ [0141]), that overlaps the drive transistor (T2, FIGs. 1-2).
Regarding claim 18, Xu discloses the display pixel defined in claim 17, further comprising: a capacitor (Cst, FIG. 1) that is connected to the gate of the drive transistor (T2, FIG. 1); and a third deck on the second deck that includes the capacitor (Cst) and a third planarization layer (13, FIG. 2A) that overlaps the capacitor (Cst, FIG. 2A).
Regarding claim 19, Xu discloses the display pixel defined in claim 18, further comprising: an anode (61, ¶ [0137]) for the light-emitting diode (61-63) on the third planarization layer (13, FIG. 2A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 10 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US PG-Pub No.: 2020/0135089 A1, hereinafter, “Ji”), as applied to claim 9 above, in view of Choi et al. (US PG-Pub No.: 2020/0013843 A1, hereinafter, “Choi”).
Regarding claim 10, Ji discloses the display pixel defined in claim 9.
Ji is silent regarding that the first and second transistors (Tec and Tdr) comprise respective first and second channel regions (ACT) formed from semiconducting oxide.
Choi, however, discloses a display (see Choi, FIG. 3), wherein a channel region (135, ¶ [0050]) of a transistor (255, FIG. 3) formed from semiconductor oxide (¶ [0050]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Ji’s first and second transistors comprising respective first and second channel regions formed from semiconducting oxide, as taught by Choi, since the selection of a known material (oxide semiconductor) based on its suitability for its intended use (to form channel) supports a prima facie obviousness determination. See MPEP § 2144.07.
Regarding claim 15, Ji discloses the display pixel defined in claim 1.
Ji is silent regarding that the first and second planarization layers comprise a siloxane material.
Choi, however, discloses a display (see Choi, FIG. 3), wherein a planarization layer (270, FIG. 3) comprising a siloxane material (¶ [0083]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Ji’s first and second planarization layers comprising a siloxane material, as taught by Choi, since the selection of a known material (siloxane) based on its suitability for its intended use (to form a planarization layer) supports a prima facie obviousness determination. See MPEP § 2144.07.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US PG-Pub No.: 2020/0135089 A1, hereinafter, “Ji”), as applied to claim 9 above, in view of Zhu et al. (US PG-Pub No.: 2022/0140047 A1, hereinafter, “Zhu”).
Regarding claim 14, Ji discloses the display pixel defined in claim 1, further comprising: a conductive via (FIG. 5) that extends through the first planarization layer.
Ji is silent regarding that the conductive via has a width that is less than 1 micron.
Zhu, however, discloses a display (see Zhu, FIG. 1), wherein conductive via have a width that is less than 1 micron (¶ [0060]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Ji’s conductive via with a width that is less than 1 micron, as taught by Zhu, in order to form small pixels with better resolution.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Ji et al. (US PG-Pub No.: 2020/0135089 A1, hereinafter, “Ji”) in view of Yu et al. (US PG-Pub No.: 2021/0226169 A1, hereinafter, “Yu”).
Regarding claim 20, Ji discloses a display (see Ji, FIGs. 1 and 3) comprising:
an array of display pixels (FIG. 1), wherein a display pixel in the array of display pixels comprises:
a light-emitting diode (P, FIG. 1) configured to emit light vertically (FIG. 3);
a drive transistor (Tdr, FIG. 3) with a first gate (GE for Tdr, FIG. 3) that is vertically overlapped by the light-emitting diode (P with AE, FIG. 3); and
an additional transistor (Ts, FIG. 3) with a second gate (GE for Ts) that is vertically overlapped by the light-emitting diode (P with AE) and the first gate (GE for Tdr, FIG. 3).
Ji is silent regarding that a pixel density greater than 1000 pixels per inch.
However, Yu discloses a display having a pixel density greater than 1000 pixels per inch (¶ [0008]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Ji’s display having a pixel density greater than 1000 pixels per inch, as taught by Yu, in order to form display with high resolution.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
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/XIA L CROSS/ Primary Examiner, Art Unit 2892
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