DETAILED ACTION
This Office action is in response to the amendment of 11/17/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/26/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 11, 7 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (US 2022/0300409 A1) hereinafter Duan et al. in further view of Sela et al. (US 2020/0356280 A1) hereinafter Sela et al.
Regarding claim 1, Duan et al. teaches a method for processing commands from a host computing device to a storage device, the method comprising:
identifying, by the storage device, a command from the host computing device, the command including a logical address (a controller/host interface of a flash memory device can receive a memory access command from a host and a determination can be made as to whether a first LBA received with the memory access command is indexed in an L2P region within the L2P cache Paragraph [0047]);
requesting, by the storage device, translation of the logical address into a physical address (for a read command, an LBA translation to find one or more physical addresses of one or more LBAs associated with the read command can be performed Paragraph [0038];
storing, by the storage device, the physical address in a cache (if the first LBA is not indexed in the L2P table, multiple L2P regions of the complete L2P table can be loaded from the flash memory to the L2P cache, and a physical address of the flash memory based on the first LBA and a L2P region can be determined Paragraph [0047]); and
transferring data according to the command based on the physical address (the memory access command can be executed using the physical address Paragraph [0047]).
Duan et al. does not appear to explicitly teach, however, Sela et al. teaches requesting, by the storage device to the host computing device, translation of the logical address into a physical address (after the read command message is transmitted by the host to the memory device, the memory device transmits a ready to transfer message to the host Paragraph [0067]); and receiving, by the storage device from the host computing device, the physical address (in response to the ready to transfer message, host transmits a data transfer message 534 to memory device which includes a plurality of indications of physical addresses in the memory device Paragraph [0067]. In response, memory device transmits the data read during the read operations from the memory device to the host Paragraph [0068]).
The disclosures of Duan et al. and Sela et al., hereinafter DS are analogous art to the claimed invention because they are in the same field of endeavor of command processing in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of DS before them, to modify the teachings of Duan et al. to include the teachings of Sela et al. since both DS teach processing I/O commands and address translation. Therefore it is applying a known technique (requesting and receiving a translation from the host computing device [0067]-[0068] of Sela et al.) to a known device (memory system address translation using a cache [0047] of Duan et al.) ready for improvement to yield predictable results (a translated physical address is received from the host computing device [0067]-[0068] of Sela et al.), KSR, MPEP 2143.
Regarding claim 7, DS teaches all of the features with respect to claim 1, as outlined above.
Duan et al. further teaches wherein the command includes a command to read the data from the storage device, wherein the logical address is for storing the data in a memory location of the host computing device (for a read command, the memory controller does an LBA translation to find one or more physical addresses of one or more LBAs associated with the read command Paragraph [0038]).
Claim 11 is rejected under 35 USC 103 for the same reasons as claim 1, as outlined above.
Claim 17 is rejected under 35 USC 103 for the same reasons as claim 7, as outlined above.
Claim(s) 2-4 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over DS in further view of Hutchison et al. (US 2020/0133567 A1) hereinafter Hutchison et al.
Regarding claim 2, DS teaches all of the features with respect to claim 1, as outlined above.
DS does not appear to explicitly teach, however, Hutchison et al. teaches starting, by the storage device, a first timer in response to identifying the command, wherein the requesting of the translation of the logical address into a physical address is based on detecting expiration of the first timer (a timer is started when a command is added to the heap and the queue can store the time for the next command timeout, and if the timer has expired, then the heap is checked to see if any individual commands have exceeded their time out. Paragraphs [0043], [0045]).
The disclosures of DS and Hutchison et al., hereinafter DSH are analogous art to the claimed invention because they are in the same field of endeavor of command processing in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of DSH before them, to modify the teachings of DS to include the teachings of Hutchison et al. since both DSH teach processing I/O commands and address translation. Therefore it is applying a known technique (starting a timer with the command and translating the LBA to a PBA based on the timer expiration [0043], [0045]) to a known device (memory system address translation using a cache [0047] of Duan et al.) ready for improvement to yield predictable results (a timer is started with the command and the address translation request is based on the timer expiration), KSR, MPEP 2143.
Regarding claim 3, DSH teaches all of the features with respect to claim 2, as outlined above.
Hutchison et al. further teaches wherein length of the first timer is shorter than a predicted latency of processing the command (the timer is set according to a required latency threshold [0048], in other words, should be shorter than the command timeout period Paragraph [0045]).
Regarding claim 4, DSH teaches all of the features with respect to claim 2, as outlined above.
Hutchison et al. further teaches wherein length of the first timer is dynamically computed based on a number of active commands to be processed (the latency threshold for competition is based on a number of commands to be processed, Paragraph [0045], in other words, the host depth queue Paragraph [0037], see claim 28).
Claim 12 is rejected under 35 USC 103 for the same reasons as claim 2, as outlined above.
Claim 13 is rejected under 35 USC 103 for the same reasons as claim 3, as outlined above.
Claim 14 is rejected under 35 USC 103 for the same reasons as claim 4, as outlined above.
Claim(s) 8-9 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over DS in further view of Kaniyur et al. (US 2007/0061549 A1) hereinafter Kaniyur et al.
Regarding claim 8, DS teaches all of the features with respect to claim 1, as outlined above.
DS does not appear to explicitly teach, however, Kaniyur et al. teaches monitoring progress of execution of the command, wherein the requesting of the translation of the logical address into a physical address is based on determining that a milestone has been reached (To service an I/O request, a full address translation is needed and performed by a DMA remap engine Paragraphs [0004]-[0005], wherein different I/O ports may send address translation requests to associated DMA remap engines within an I/O hub and to keep track of such requests as well as the progress of each request, the engine stores sideband flags to indicate the status of a TLB engine as well as flags to track the progress of the page walks Paragraph [0019]. For example, a TLB entry may be speculatively allocated to the address translation request by setting the commit flag of the TLB entry, that is, setting the commit flag is the milestone reached Paragraph [0020]).
The disclosures of DS and Kaniyur et al., hereinafter DSK are analogous art to the claimed invention because they are in the same field of endeavor of command processing in memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of DSK before them, to modify the teachings of DS to include the teachings of Kaniyur et al. since both DSK teach processing I/O commands and address translation. Therefore it is applying a known technique (monitoring the address translation request associated with an I/O and performing the translation based on a milestone reached Paragraph [0020] of Kaniyur et al.) to a known device (memory system address translation using a cache [0047] of Duan et al.) ready for improvement to yield predictable results (a TLB entry is speculatively allocated for the address translation request Paragraph [0020] of Kaniyur et al.), KSR, MPEP 2143.
Regarding claim 9, DSK teaches all of the features with respect to claim 8, as outlined above.
Kaniyur et al. further teaches wherein the monitoring includes monitoring a plurality of steps executed for the command (the DMA remap engine stores stone flags to indicate the status of each entry, for example, a commit flag indicates a TLB entry is speculatively allocated for the translation while a pending flag indicates a miss has occurred and a page walk is being performed Paragraphs [0019]-[0021]).
Claim 18 is rejected under 35 USC 103 for the same reasons as claim 8, as outlined above.
Claim 19 is rejected under 35 USC 103 for the same reasons as claim 9, as outlined above.
Allowable Subject Matter
Claims 5-6, 15-16, 10 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the claim recites “setting, by the storage device, a second timer; detecting expiration of the second timer based on the expiration of the second timer, requesting, by the storage device, the translation of the logical address into the physical address, wherein length of the second timer is based on an expected length of completing an event during processing of the command by the storage device,” which is not taught by the prior art. The prior art Duan et al. in view of Hutchison et al. teaches translation of the logical address based on expiration of a timer associated with a latency threshold. However, neither Duan nor Hutchison suggests utilizing more than one timer to perform the translation, nor basing the timer on an expected length of completing an specific event when the command is being processed.
Claim 6 depends upon claim 5 and would be allowable for at least the same reasons as claim 5, as outlined above. Claim 15 recites subject matter substantially similar to that of claim 5, thus, would be allowable for the same reasons identified above. Claim 16 depends upon claim 15 and would be allowable for at least the same reasons as claim 15, as outlined above.
Regarding claim 10, “wherein the milestone includes completion of sensing of signals from one or more memory cells of the storage device,” is not taught by the prior art. The closest prior art is Kaniyur et al. and Park (US 2004/0219745 A1) Kaniyur et al. teaches speculatively allocating a TLB entry for the address request associated with the execution of an I/O command, however, is silent with regards to detecting a read sense signal in order to perform the translation, and consequently, is silent with regards to determining a read sense operation has been completed. Park generally discusses using a read sense amplifier to perform the reading of data during I/O processing, however, is silent with regards to the translation request being dependent on a completion of the read sense operation.
Claim 20 recites subject matter substantially similar to that of claim 10, thus, would be allowable for the same reasons identified above.
Response to Arguments
Applicant’s arguments with respect to the rejection(s) of claim(s) 1 and 11 under Duan et al. have been fully considered and are persuasive. Specifically, it was argued that the prior art does not explicitly teach receiving a physical address from the host computing device to the storage device. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Sela et al. which discusses in response to the ready to transfer message sent by the storage device, the host transmits a data transfer message to memory device which includes a plurality of indications of physical addresses in the memory device (see rejection as outlined above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Widder et al. (US 2019/0004944 A1) teaches storing a copy of the address translation table in the host system which is used to convert host access requests to the actual flash access requests.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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JANE W. BENNER
Primary Examiner
Art Unit 2131
/JANE W BENNER/Primary Examiner, Art Unit 2139