DETAILED ACTION
This office action is in response to the filed application 18/755,522 on June 26, 2024.
Claims 1-20 are presented for examination.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 15-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kenny et al. (US 2024/0330092).
In regard to claim 15, Kenny et al. teach a network device comprising:
memory circuitry having error detection circuitry (memory, fig. 1, 120) and configured to store traffic forwarding decision data (memory 120, configuration 122, feedback packet queue 124, fig. 1);
data plane processing circuitry coupled to the memory circuitry and configured to access the memory circuitry for processing network traffic (control plane, fig. 5); and
control plane processing circuitry coupled to the memory circuitry and configured to sequentially access memory elements of the memory circuitry while a portion of the memory circuitry is accessed (the error comprises telemetry associated with a packet processing pipeline while processing the packet, para. 76) by the data plane processing circuitry to process the network traffic (the flow can be a sequence of packets being transferred between two endpoints, para. 16).
In regard to claim 16, Kenny et al. teach the network device defined in claim 15, wherein the control plane processing circuitry is configured to obtain an indication of a memory error based on a given memory element, in the memory elements, containing the memory error being accessed by the control plane processing circuitry (an error can be detected based on processing of a packet header and/or packet payload or with packet processing circuitry, para. 23, fig. 3A, 304).
In regard to claim 17, Kenny et al. teach the network device defined in claim 16, wherein the data plane processing circuitry and the memory circuitry are implemented on a common integrated circuit die (interface can be a standalone component or integrated onto a processor die, para. 51).
In regard to claim 18, Kenny et al. teach the network device defined in claim 15, wherein the control plane processing circuitry is configured to sequentially access memory elements of the memory circuitry by accessing each of the memory elements of the memory circuitry (the flow can be a sequence of packets being transferred between two endpoints, para. 16).
In regard to claim 19, Kenny et al. teach a network device comprising:
a packet processor configured to process network traffic (packet processing device configured to detect and report errors arising from processing packets, para. 37, fig. 1, 100, para. 10-13);
memory circuitry having error detection circuitry (memory, fig. 1, 120) and accessible by the packet processor when processing the network traffic (memory 120, configuration 122, feedback packet queue 124, fig. 1); and
processing circuitry coupled to the memory circuitry and configured to probe the memory circuitry for one or more memory errors while the packet processor accesses the memory circuitry to process the network traffic (an accelerator can include a packet processing pipeline that can detect and report errors arising from processing packets that are to be transmitted or were received, para. 9).
In regard to claim 20, Kenny et al. teach the network device defined in claim 19, wherein the processing circuitry is configured to probe the memory circuitry for one or more memory errors by accessing memory elements of the memory circuitry in a given order (an error can be detected based on processing of a packet header and/or packet payload or with packet processing circuitry, para. 23, fig. 3A, 304).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kenny et al. (US 2024/0330092) in further view of Singhal et al. (US 12,107,750).
In regard to claim 1, Kenny et al. teach a network device comprising:
a packet processor configured to process network traffic (packet processing device configured to detect and report errors arising from processing packets, para. 37, fig. 1, 100, para. 10-13);
memory circuitry having error detection circuitry (memory, fig. 1, 120), coupled to the packet processor, and configured to store data for processing the network traffic (memory 120, configuration 122, feedback packet queue 124, fig. 1); and
processing circuitry coupled to the memory circuitry and configured to: access the memory circuitry (errors or anomalies are identified in configuration 122, fig. 1, para. 13); and
correct the memory error (remedial action can include reprogram the network interface device to correctly process the packet associated with the error, para. 15).
Kenny et al. does not explicitly teach obtain, in response to accessing the memory circuitry, an indication of a memory error in the data prior to the data being accessed by the packet processor to process the network traffic.
Singhal et al. teach of implementing network probes to process the data packets that the network probes receive from the packet flow switch to process the data packets by determining key performance indicators regarding the communication session such as (e.g., bit rate, packet loss, jitter, drop rate, bit error rate, packet latency, voice quality, browsing quality, dropped call rate, network connection success rate, etc.) (col. 13 lines 5-25).
It would have been obvious to modify the device of Kenny et al. by adding Singhal et al. packet probes. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid monitoring data packets between the servers that transmit data and client devices (col. 5 lines 25-52).
In regard to claim 2, Kenny et al. teach the network device defined in claim 1, wherein the processing circuitry is configured to access the memory circuitry in parallel with the packet processor accessing the memory circuitry to process the network traffic (the error comprises telemetry associated with a packet processing pipeline while processing the packet, para. 76).
In regard to claim 3, Kenny et al. teach the network device defined in claim 1, wherein the processing circuitry is configured to access the memory circuitry by sequentially accessing memory elements in the memory circuitry (the flow can be a sequence of packets being transferred between two endpoints, para. 16).
In regard to claim 4, Kenny et al. teach the network device defined in claim 3, wherein a given memory element in the sequentially accessed memory elements stores a value that is part of the data and that contains the memory error and wherein the processing circuitry is configured to obtain the indication of the memory error in response to accessing the given memory element (a flow can be identified by a set of defined tuples or header field values and, for routing purpose, a flow is identified by the two tuples that identify the endpoints, para. 16).
In regard to claim 5, Kenny et al. teach the network device defined in claim 4, wherein the error detection circuitry is configured to detect the memory error when validating the value at the given memory element in response to the processing circuitry accessing the given memory element and wherein the obtained indication of the memory error is based on the memory error being detected by the error detection circuitry (an error can be detected based on processing of a packet header and/or packet payload or with packet processing circuitry, para. 23, fig. 3A, 304).
In regard to claim 6, Kenny et al. teach the network device defined in claim 3, wherein the processing circuitry is configured to access the memory circuitry by accessing each of the memory elements in the memory circuitry (the network interface device can process the packet … where errors can be detected based on processing of a packet header and/or packet payload independent from the processing of the packet, para. 23, fig. 3a).
In regard to claim 7, Kenny et al. teach the network device defined in claim 1, wherein the stored data for processing the network traffic comprises data for a routing table or data for an access control list (packet processors 102 can be configured to detect errors or anomalies, where errors or anomalies are identified in configuration, configuration can specify events described at least with respect to Table 1, para. 13).
In regard to claim 8, Kenny et al. teach the network device defined in claim 1, wherein the processing circuitry comprises control plane processing circuitry (control plane, fig. 5).
In regard to claim 9, Kenny et al. teach the network device defined in claim 8, wherein the memory circuitry comprises on-chip memory integrated with the packet processor on an integrated circuit die (interface can be a standalone component or integrated onto a processor die, para. 51).
In regard to claim 10, Kenny et al. teach the network device defined in claim 9, wherein the on-chip memory comprises static random-access memory (memory subsystem can include one or more varieties of random-access memory, para. 53).
In regard to claim 11, Kenny et al. teach the network device defined in claim 8, wherein the memory circuitry comprises discrete memory on an integrated circuit die separate from an integrated circuit die implementing the packet processor (interface can be a standalone component or integrated onto a processor die, para. 51, Fig. 6, 612, 610, 620).
In regard to claim 12, Kenny et al. teach the network device defined in claim 11, wherein the discrete memory comprises dynamic random-access memory (memory subsystem can include one or more varieties of random- access memory, para. 53).
In regard to claim 13, Kenny et al. teach the network device defined in claim 1 further comprising: a memory controller (memory controller could be a part of the processor or a part of the interface, para. 53, fig. 6), wherein the processing circuitry is configured to access the memory circuitry using the memory controller and is configured to obtain the indication of the memory error in the data from the memory controller (the network interface device can determine whether processing of the packet incurs an error, para. 23, fig. 3).
In regard to claim 14, Kenny et al. teach the network device defined in claim 13, wherein the memory controller is integrated with the packet processor on an integrated circuit die (interface can be a standalone component or integrated onto a processor die, para. 51, Fig. 6, 612, 610, 620).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Burdet et al. (US 12,309,056) fast reroute
Mishra et al. (US 2025/0016092) fault detection with probe packets
Zhao et al. (US 2020/0151075) fault detection on network devices
Seth et al. (US 10,397,085) failure detection of network devices
Smith et al. (US 2019/0171510) monitoring network devices
Osborne et al. (US 9,049,142) selective traffic
Azzam et al. (US 12,574,309) probes to mitigate lost packets
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 HYPERLINK "mailto:Loan.truong@uspto.gov" Loan.truong@uspto.gov
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