DETAILED ACTION
This office action is in response to applicant’s remarks filed on July 14, 2026 in application 18/755,522.
Claims 1-20 are presented for examination. Claims 1, 3-9, 11, 13 and 15-20 are amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 1-14 are allowed.
The following is an examiner’s statement of reasons for the allowance:
The examiner deemed claims 1-14 as novel when read as a whole for the limitations of a packet processor configured to process network traffic, a processing circuitry coupled to the memory circuitry and configured to obtain, in response to accessing the memory circuitry, an indication of a faulty value stored at a given memory element of the memory circuit prior to the faulty value being accessed by the packet processor to process the network traffic and correct the faulty value prior to the faulty value being accessed by the packet processor to process the network traffic.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kenny et al. (US 2024/0330092) in further view of in further view of Chunduri et al. (US 2023/0231798).
In regard to claim 15, Kenny et al. teach a network device comprising:
memory circuitry having error detection circuitry (memory, fig. 1, 120) and configured to store traffic forwarding decision data (memory 120, configuration 122, feedback packet queue 124, fig. 1);
data plane processing circuitry (packet processor 102 including its data plane, para. 12-13) coupled to the memory circuitry and configured to
receive network traffic (configured to perform action using information stored in a ternary content-addressable memory, para. 12), and
process the received network traffic using a portion of the traffic forwarding decision data by accessing a portion of the memory circuitry that stores the portion of the traffic forwarding decision data (perform matching action on received packets to identify packet processing rules and next hops using information stored, para. 12); and
control plane processing circuitry coupled to the memory circuitry and configured to execute control plane software (control plane software, para. 15).
Kenny et al. does not explicitly teach but Chunduri et al. teach of sequentially access memory elements of the memory circuitry to validate data stored in each of the accessed memory elements of the memory circuitry using the error detection circuitry (monitoring transmission through its links … error checking/correcting system that is used for bit errors detected by the CRC, para. 111, dynamically detect errors and provides an indication of the detected errors, para. 112), wherein the memory elements of the memory circuitry are sequentially accessed while the portion of the memory circuitry is accessed by the data plane processing circuitry to process the received network traffic (network 100 also includes a control plane through which each of the edge nodes 108 and internal nodes 110 is coupled to the network controller or may be co-extensive with the data plane, para. 63, fig. 1, dynamically detect errors and provides an indication of the detected errors while data may still flow through the link, para. 112).
It would have been obvious to modify the device of Kenny et al. by adding Chunduri et al. conditional routing delivery. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in allowing the data plane and the control plane to route data packets with a specified service level guarantees for the data flow (para. 64).
In regard to claim 16, Kenny et al. does not explicitly teach but Chunduri et al. teach the network device defined in claim 15, wherein the control plane processing circuitry is configured to detect an error in a value stored in a given memory element of the memory elements of the memory circuitry (monitoring transmission through its links … error checking/correcting system that is used for bit errors detected by the CRC, para. 111, dynamically detect errors and provides an indication of the detected errors, para. 112) by sequentially accessing the memory elements of the memory circuity (data in the data flow is separated into data packets for transmission, para. 64).
Refer to claim 15 for motivational statement.
In regard to claim 17, Kenny et al. teach the network device defined in claim 15, wherein the data plane processing circuitry and the memory circuitry are implemented on a common integrated circuit die (interface can be a standalone component or integrated onto a processor die, para. 51).
In regard to claim 18, Kenny et al. teach the network device defined in claim 15, wherein the control plane processing circuitry comprises a packet processor (packet processor 102 including its data plane, para. 12-13) and wherein the control plane processing circuitry comprises a central processing unit (control plane software executed on a server, para. 15).
In regard to claim 19, Kenny et al. teach a network device comprising:
a packet processor configured to process network traffic (packet processing device configured to detect and report errors arising from processing packets, para. 37, fig. 1, 100, para. 10-13);
memory circuitry having error detection circuitry (memory, fig. 1, 120) and accessible by the packet processor when processing the network traffic (memory 120, configuration 122, feedback packet queue 124, fig. 1); and
Kenny et al. does not explicitly teach but Chunduri et al. teach processing circuitry coupled to the memory circuitry and configured to probe the memory circuitry to detect one or more bit flips at one or more corresponding memory elements in the memory circuitry (monitoring transmission through its links … error checking/correcting system that is used for bit errors detected by the CRC, para. 111, dynamically detect errors and provides an indication of the detected errors, para. 112) while the packet processor accesses the memory circuitry to process the network traffic (dynamically detect errors and provides an indication of the detected errors while data may still flow through the link, para. 112).
Refer to claim 15 for motivational statement.
In regard to claim 20, Kenny et al. does not explicitly teach but Chunduri et al. teach the network device defined in claim 19, wherein the memory circuitry includes a plurality of memory elements that stores traffic forwarding decision data, wherein the plurality of memory elements include the one or more corresponding memory elements (a data flow is a group of related communications between a common set of endpoints … data in the data flow is separated into data packets for transmission … each packet may have a header with routing information that includes nodes and/or links describing a path that meets one or more SLOs that define service level guarantees for the data flow, para. 64) wherein the processing circuitry is configured to probe the memory circuitry by reading each memory element of the plurality of memory elements of the memory circuitry (monitoring transmission through its links … error checking/correcting system that is used for bit errors detected by the CRC, para. 111, dynamically detect errors and provides an indication of the detected errors, para. 112).
Refer to claim 15 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Weng et al. (2023/0077784) probe interface and tester for memory system
AHN (US 2023/0118580) probe card and tester
Konamki Vijayamunesswaralu et al. (US 2025/0231882) probes and lock
Bradbury et al. (US 7,523,352) probe device and logging error condition detected at each node.
Malboubi et al. (US 11,165,677) probe packets with agents
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Burdet et al. (US 12,309,056) fast reroute
Mishra et al. (US 2025/0016092) fault detection with probe packets
Zhao et al. (US 2020/0151075) fault detection on network devices
Seth et al. (US 10,397,085) failure detection of network devices
Smith et al. (US 2019/0171510) monitoring network devices
Osborne et al. (US 9,049,142) selective traffic
Azzam et al. (US 12,574,309) probes to mitigate lost packets
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LOAN TRUONG whose telephone number is 408-918-7552. The examiner can normally be reached on 10AM-6PM PST M-F.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached on 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 Loan.truong@uspto.gov
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