Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the preliminary amendment filed on 10/25/2024.
Drawings
The drawings are objected to because of the following informalities. Figures 1A, 1B, 2A, 2B, 2C, 3A, 3B, 4, 5A, 7A, and 7B should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g). Regarding Figs. 1A- 12D, the figures contain illegible words and letters due to poor resolution and/or grey scale backgrounds.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 3, 11, 15, and 20 are objected to because of the following informalities: Regarding claim 3, in line 1, “claim 1” appears that it should read as “claim 2“, as "CGD" was initially claimed in claim 2.
Regarding claim 11, in line 1, "the second plurality of photodiodes is evenly illuminated" appears that it should read as "wherein the second plurality of photodiodes is evenly illuminated".
Regarding claim 15, in line 1, “claim 12” appears that it should read as “claim 13“, as "CGD" was initially claimed in claim 13.
Regarding claim 20, in line 2, "a first optical pusle" appears that it should read as "a first optical pulse".
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 12, 13, and 14 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhang et al. (US Patent Application Publication US 2010/0019807 A1, hereinafter “Zhang”). Regarding claim 1, Zhang discloses (see Figs. 1, 2, and 3A-3D) a circuit for switching a power semiconductor device (see power MOSFET Q) comprising: a power semiconductor device (power MOSFET Q); and a controlled current pulse source (current-source gate driver circuit comprising inductor Lr, blocking capacitor Cb, and switches S1, S2; see [0073]) coupled to the power semiconductor device generating a positive current pulse (positive direction inductor current iLr during Mode 1 [t0, t1] charges the gate capacitor Cgs of Q; see [0075] and Fig. 3A) to switch ON the power semiconductor device and a negative current pulse (negative direction inductor current iLr during Mode 3 [t2, t3] discharges the gate capacitor Cgs of Q; see [0077] and Fig. 3C) to switch OFF the power semiconductor device. Regarding claim 2, Zhang discloses (see Figs. 1, 3A-3D) wherein the positive current pulse charges both a capacitance between a gate and a source CGS of the power semiconductor device and a capacitance between the gate and a drain CGD of the power semiconductor device concurrently (see [0066] "the time constant of the inductor and the equivalent capacitor (e.g., the sum of Cgs and Cgd) of the power switching device"; see also [0065] defining Cgd as the Miller capacitance; the inductor current pulse is applied to the gate terminal which is connected to both CGS and CGD, thereby charging both capacitances concurrently) to switch ON the power semiconductor device and the negative current pulse discharges both CGS and CGD concurrently (see [0077] and Fig. 3C; the negative direction inductor current iLr discharges the drain capacitor Cds2 of S2 and the gate capacitor Cgs of the MOSFET Q simultaneously, and since the gate terminal is connected to both CGS and CGD, both are discharged concurrently) to switch OFF the power semiconductor device. Regarding claim 12, Zhang discloses (see Figs. 1, 2, 3A-3D) a method for switching a power semiconductor device (power MOSFET Q) comprising: sending a controlled current pulse (inductor current iLr; see [0074]) to the power semiconductor device, wherein the controlled current pulse is a positive current pulse (positive direction iLr during Mode 1; see [0075] and Fig. 3A) to switch ON the power semiconductor device and a negative current pulse (negative direction iLr during Mode 3; see [0077] and Fig. 3C) to switch OFF the power semiconductor device. Regarding claim 13, Zhang discloses (see Figs. 1, 3A-3B) comprising charging both a capacitance between a gate and a source CGS (Cgs of Fig. 1) of the power semiconductor device and a capacitance between the gate and a drain CGD (gate-drain capacitance of Q which is inherent to MOSFET Q, see [0066] “In embodiments of the current-source gate driver described herein, the time constant of the inductor and the equivalent capacitor (e.g., the sum of Cgs and Cgd) of the power switching device is much larger (for example, 10 to 20 times larger) than the switching transition time (i.e., turn on time or turn off time) of the power switching device.”) of the power semiconductor device with the positive current pulse concurrently (see [0066] and [0075] Mode1; the positive inductor current is applied to the gate terminal, which is inherently connected to both Cgs and Cgd per [0065]; both capacitances are charged concurrently) to switch ON the power semiconductor device. Regarding claim 14, Zhang discloses (see Figs. 1, 3C-3D) comprising discharging both a capacitance between a gate and a source CGS of the power semiconductor device and a capacitance between the gate and a drain CGD of the power semiconductor device concurrently by the negative current pulse (see [0077]; the negative inductor current iLr discharges the gate capacitor Cgs through the gate terminal, and since the gate terminal is inherently connected to both CGS and CGD per [0065], both are discharged concurrently) to switch OFF the power semiconductor device.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3-7, and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Liu et al. (US Patent Application Publication US 2012/0068683 A1, hereinafter “Liu”). Regarding claim 3, Zhang does not explicitly disclose wherein the controlled current pulse source adjusts the negative current pulse to drain out a displacement current going through CGD.
However, Liu teaches (see Figs. 2(a), 3, and 4(f1)-4(f2)) wherein the controlled current pulse source (“Current Source Driver”) adjusts the negative current pulse to address displacement current through CGD (see [0039] discussing the gate current diversion problem during the power MOSFET switching transition due to body diode conduction in S4; see [0054] describing that during turn-off, diodes Ds1-Ds5 are driven on, clamping Vgs at about -3.5V, resulting in a more negative voltage applied to the source inductor Ls per Equation (1); see [0062] describing that the gate discharge current is not diverted until Vgs reaches a much more negative voltage, thereby significantly reducing switching time and turn-off loss).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the controlled current pulse source adjusts the negative current pulse to drain out a displacement current going through CGD, as taught by Liu, because it can help reduce gate current diversion during switching transitions, reduce switching time, and reduce turn-off loss (see [0062] of Liu). Regarding claim 4, Zhang does not disclose comprising at least one clamping diode coupled in parallel to the controlled current pulse source to limit a transient voltage between the gate and the source of the power semiconductor device.
However, Liu teaches (see Figs. 2(a) and 4(f2)) comprising at least one clamping diode (plurality of diodes Ds1-Ds5 connected in series; see [0043]) coupled in parallel to the controlled current pulse source (coupled between gate and source of the power MOSFET Q, in parallel with the bi-directional switch S4/S5) to limit a transient voltage between the gate and the source of the power semiconductor device (the series diodes define and clamp the negative gate-to-source voltage at about -3.5V during the turn-off transition; see [0054]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang to comprise at least one clamping diode coupled in parallel to the controlled current pulse source to limit a transient voltage between the gate and the source of the power semiconductor device, as taught by Liu, because it can help provide a controlled negative gate voltage to accelerate turn-off and mitigate body diode conduction (see [0040]-[0041] of Liu). Regarding claim 5, Zhang does not disclose comprising at least one clamping diode coupled in parallel to the controlled current pulse source in each voltage direction.
However, Liu teaches (see Figs. 2(a) and 4(b)-4(f2)) at least one clamping diode coupled in parallel to the controlled current pulse source in each voltage direction (during turn-on, the gate voltage is clamped to Vc through S2 per [0050]; during turn-off, diodes Ds1-Ds5 clamp the negative gate voltage per [0054]; the bi-directional switch S4/S5 with body diodes provides clamping in each voltage direction between gate and source).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang to comprise at least one clamping diode in each voltage direction, as taught by Liu, because it can help provide a controlled negative gate voltage to accelerate turn-off and mitigate body diode conduction (see [0040]-[0041] of Liu). Regarding claim 6, Zhang does not disclose wherein the at least one clamping diode has a breakdown voltage which will be an on-voltage level of a gate-to-source voltage of the power semiconductor device. However, Liu teaches (see [0044]) wherein the at least one clamping diode has a breakdown voltage which will be an on-voltage level of a gate-to-source voltage of the power semiconductor device (Q) (see [0044] "a Zener diode may be used in place of the series circuit of diodes"; a Zener diode inherently has a breakdown voltage that would define the on-voltage level of the gate-to-source voltage).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the at least one clamping diode has a breakdown voltage which will be an on-voltage level of a gate-to-source voltage of the power semiconductor device, as taught by Liu, because it allows the designer to precisely define the gate drive voltage level (see Liu [0044]). Regarding claim 7, Zhang does not disclose wherein the at least one clamping diode has a forward bias voltage which will be an off-level voltage of the power semiconductor device. However, Liu teaches (see Fig. 2(a) and [0043]-[0044]) wherein the at least one clamping diode (Ds1-Ds5) has a forward bias voltage which will be an off-level voltage of the power semiconductor device (Q) (the plurality of series diodes Ds1-Ds5 have cumulative forward bias voltage drops that define the negative gate-to-source voltage, i.e., the off-level voltage of about -3.5V; see [0054]; see also [0044] "The number of diodes may vary depending on the power switching device used, and the desired negative gate to source voltage").
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the at least one clamping diode has a forward bias voltage which will be an off-level voltage of the power semiconductor device, as taught by Liu, because it allows the designer to precisely set the desired negative gate voltage by selecting the number of series diodes (see [0044] of Liu).
Regarding claim 15, Zhang does not explicitly disclose comprising adjusting the negative current pulse to drain out a displacement current going through CGD.
However, Liu teaches (see Figs. 2(a), 3, 4(f1)-4(f2)) adjusting the gate drive current (via “Current Source Driver”) during turn-off to address displacement current through CGD by providing a more negative gate-to-source voltage (see [0039] discussing the gate current diversion problem during the power MOSFET switching transition due to body diode conduction in S4; see [0054] describing that during turn-off, diodes Ds1-Ds5 are driven on, clamping Vgs at about -3.5V, resulting in a more negative voltage applied to the source inductor Ls per Equation (1); see [0062] describing that the gate discharge current is not diverted until Vgs reaches a much more negative voltage, thereby significantly reducing switching time and turn-off loss).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Zhang to comprise adjusting the negative current pulse to drain out a displacement current going through CGD, as taught by Liu, because it can help reduce gate current diversion and switching loss (see [0062] of Liu). Regarding claim 16, Zhang does not disclose comprising limiting a transient voltage between the gate and the source of the power semiconductor device.
However, Liu teaches (see Figs. 2(a), 4(f2)) limiting a transient voltage between the gate and the source of the power semiconductor device (series diodes Ds1-Ds5 and bi-directional switch S4/S5 limit the gate-to-source voltage to about -3.5V; see [0054]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Zhang to include limiting a transient voltage between the gate and the source, as taught by Liu, because it can help protect the power semiconductor device from excessive gate voltage excursions and provide a controlled negative gate voltage (see [0040]-[0041] of Liu). Regarding claim 17, Zhang discloses (see Figs. 1, 2, 3A-3D) a circuit for switching a power semiconductor device comprising: a power semiconductor device (power MOSFET Q); a controlled current pulse source (inductor Lr, Cb, S1, S2; see [0073]) coupled to the power semiconductor device generating a positive current pulse (positive direction iLr; see [0075] and Fig. 3A) to switch ON the power semiconductor device and a negative current pulse (negative direction iLr; see [0077] and Fig. 3C) to switch OFF the power semiconductor device, wherein the positive current pulse charges both a capacitance between a gate and a source CGS of the power semiconductor device and a capacitance between the gate and a drain CGD of the power semiconductor device concurrently (see [0066] "the time constant of the inductor and the equivalent capacitor (e.g., the sum of Cgs and Cgd) of the power switching device"; see also [0065] defining Cgd as the Miller capacitance; the inductor current pulse is applied to the gate terminal which is connected to both CGS and CGD, thereby charging both capacitances concurrently) to switch ON the power semiconductor device and the negative current pulse discharges both CGS and CGD concurrently (see [0077] and Fig. 3C; the negative direction inductor current iLr discharges the drain capacitor Cds2 of S2 and the gate capacitor Cgs of the MOSFET Q simultaneously, and since the gate terminal is connected to both CGS and CGD, both are discharged concurrently) to switch OFF the power semiconductor device.
Zhang does not explicitly disclose wherein the controlled current pulse source adjusts the negative current pulse to drain out a displacement current going through CGD; and at least one clamping diode coupled in parallel to the controlled current pulse source to limit a transient voltage between the gate and the source of the power semiconductor device.
However, Liu teaches (see Figs. 2(a), 3, 4(f1)-4(f2)) wherein the controlled current pulse source (“Current Source Driver”) adjusts the negative current pulse to address displacement current going through CGD (see [0039] discussing the gate current diversion problem during the power MOSFET switching transition due to body diode conduction in S4; see [0054] describing that during turn-off, diodes Ds1-Ds5 are driven on, clamping Vgs at about -3.5V, resulting in a more negative voltage applied to the source inductor Ls per Equation (1); see [0062] describing that the gate discharge current is not diverted until Vgs reaches a much more negative voltage, thereby significantly reducing switching time and turn-off loss); and at least one clamping diode (diodes Ds1-Ds5; see [0043]) coupled in parallel to the controlled current pulse source to limit a transient voltage between the gate and the source of the power semiconductor device (see [0054]; Vgs clamped at about -3.5V).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the controlled current pulse source adjusts the negative current pulse to drain out a displacement current going through CGD, and to include at least one clamping diode coupled in parallel to the controlled current pulse source to limit a transient voltage between the gate and the source, as taught by Liu, because it can help reduce gate current diversion during switching transitions, reduce turn-off time, reduce switching loss, and provide a controlled negative gate voltage to mitigate body diode conduction (see [0040]-[0041] and [0062] of Liu).
Claims 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Meyer et al. (US Patent 5,391,997, hereafter “Meyer”).
Regarding claim 8, Zhang does not disclose wherein the controlled current pulse source comprises a first plurality of photodiodes connected in series.
However, Meyer teaches (see sole Figure) wherein a current/voltage source (10) for driving a power semiconductor device (72) comprises a first plurality of photodiodes connected in series (photovoltaic array 40 including serially coupled diodes 36 and 38; see col. 2, lines 61-63, "Photovoltaic array 40 includes one or more serially coupled diodes such as diodes 36 and 38 and is responsive to an optical signal").
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the controlled current pulse source comprises a first plurality of photodiodes connected in series, as taught by Meyer, because it can help provide galvanic isolation between the control circuit and the power stage, thereby enhancing noise immunity and enabling high-side gate driving without a separate isolated power supply.
Regarding claim 9, Zhang does not disclose wherein the first plurality of photodiodes is evenly illuminated with a first optical pulse generating a voltage larger than Von for the power semiconductor device. However, Meyer teaches (see sole Figure) wherein the first plurality of photodiodes is evenly illuminated with a first optical pulse (photovoltaic array 40 is illuminated by the optical input signal at input node 12; see col. 2, lines 61-66) generating a voltage larger than Von for the power semiconductor device (see col. 4, lines 3-8, "Photovoltaic array 40 includes one or more optical diodes like 36 and 38 serially connected anode to cathode to produce a voltage level and current sufficient to raise the gate potential of MOSFET 72 above its source voltage and turn on and hold on MOSFET 72").
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the first plurality of photodiodes is evenly illuminated with a first optical pulse generating a voltage larger than Von, as taught by Meyer, because it can help provide galvanic isolation between the control circuit and the power stage, thereby enhancing noise immunity and enabling high-side gate driving without a separate isolated power supply.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zhang in view of Liu, and further in view of Meyer.
Regarding claim 18, Zhang does not disclose wherein the controlled current pulse source comprises a first plurality of photodiodes connected in series.
However, Meyer teaches (see sole Figure) a first plurality of photodiodes connected in series (photovoltaic array 40 including serially coupled diodes 36 and 38; see col. 2, lines 61-63, "Photovoltaic array 40 includes one or more serially coupled diodes such as diodes 36 and 38 and is responsive to an optical signal") for driving a power semiconductor device (72).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Zhang wherein the controlled current pulse source comprises a first plurality of photodiodes connected in series, as taught by Meyer, because it can help provide galvanic isolation between the control circuit and the power stage, thereby enhancing noise immunity and enabling high-side gate driving without a separate isolated power supply.
Allowable Subject Matter
Claims 10, 11, 19, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 10, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “the controlled current pulse source comprises a second plurality of photodiodes connected in series and parallel to the first plurality of photodiodes, wherein the second plurality of photodiodes are an opposite polarity from the first plurality of photodiodes.”. Claim 11 is objected due to its dependency on claim 10. Regarding Claim 19, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “the controlled current pulse source comprises a second plurality of photodiodes connected in series and parallel to the first plurality of photodiodes, wherein the second plurality of photodiodes are an opposite polarity from the first plurality of photodiodes,”. Claim 20 is objected due to its dependency on claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 4,777,387 A discloses a fast turn-off circuit for a photovoltaic driven MOSFET. Mazumder et al. (Mazumder and Sarkar, "Optically Activated Gate Control for Power Electronics," IEEE Trans. Power Electronics, vol. 26, no. 10, pp. 2863-2886, Oct. 2011) discloses optical gate control mechanisms for modulating switching dynamics of power semiconductor devices via CGS and CGD charging/discharging rate control.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JYE-JUNE LEE whose telephone number is (571)270-7726. The examiner can normally be reached on M-F 9 AM - 5 PM.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838