DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 8-9, & 15-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Li Heqing et al (Translation of CN # 208818756).
Regarding Independent claim 1, Li Heqing teaches:
A current detection circuit for a direct-current to direct-current (DC-DC) converter, the DC-DC converter comprising a high-side transistor and a low-side transistor coupled in series between an input end and a ground with a switch node formed between the high-side transistor and the low-side transistor, the switch node being coupled to an inductor, the current detection circuit comprising:
a first detection circuit (Fig. 1 Element Qsen. See paragraphs 0004-0011 & 0019-0024.) configured to detect a current provided by the low-side transistor to the inductor during a turn-on period of the low-side transistor (Paragraph 0013.), thereby generating a low-side detecting current (Fig. 1 Element Isen. See paragraphs 0004-0011 & 0019-0024.); and
a processing circuit (Fig. 1 Element Circuit accepting Isen. See paragraphs 0019-0024.) comprising a first capacitor (Fig. 1 Element Csample. See paragraphs 0019-0024.) having a first end coupled to the ground (Fig. 1 Element Csample. See paragraphs 0019-0024.) and configured to perform an operation during a first and a second switch cycle (Fig. 1 Element Csample and the ground it is connected to. See paragraphs 0019-0024 wherein the capacitor is disclosed working in both the first working cycle and the second working cycle.), wherein the operation includes:
outputting a cycle detecting current based on a terminal voltage established at a second end of the first capacitor (Fig. 1 Elements Rsen & Csample. See paragraphs 0017-0025. “The sampling resistor (Rsen) converts the detected load current (Isen) into a voltage signal.” See also Fig. 2 and the signals produced. );
increasing the terminal voltage established on the first capacitor by applying a constant current during a first period of the first switch cycle (Fig. 1 Elements Rsen & Csample wherein voltage would necessarily increase with an applied voltage. See paragraphs 0021-0023 wherein the in Csample is disclosed in the first working cycle wherein the high-side is off & the low side is on.), wherein the first period is a turn-on period of the high-side transistor or a turn-off period of the low-side transistor (Fig. 1 Elements Rsen & Csample. See paragraph 0021.);
varying the terminal voltage with the low-side detecting current generated during a second period of the first switch cycle (See paragraphs 0023-0024 wherein the second working cycle is disclosed. Paragraph 0021 discloses the “sampling current Isen flows through the sampling resistor (Rsen) and generates a voltage drop, which is the sampling voltage.”); and
determining a magnitude of the constant current to be applied during the second switch cycle based on levels of the terminal voltages established at least at two time points during the first switch cycle (See paragraphs 0019-0024 wherein the load current is detected and a constant current is disclosed being achieved through adjustment of the CC error amplifier.);
wherein the at least two time points include at least one time point within the turn-on period of the low-side transistor (See Fig. 2 and all possible time points that exist in the images plotted. Any two time points can be found in the necessary region. See paragraph 0023 wherein “the second working cycle, the high-side PMOS transistor (QP) is off, the low-side NMOS transistor (QN) is on, the first switch (SW1) is off, and
the second switch (SW2) is off.”), which occurs during the second period of the first switch cycle (See paragraphs 0019-0024.).
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Regarding claim 2, Li Heqing teaches all elements of claim 1, upon which this claim depends.
Li Heqing teaches the at least two time points include a first time point in the first period when the high-side transistor is turned on (See Fig. 2 and all possible time points that exist in the images plotted. Any two time points can be found in the necessary region. See paragraph 0023 wherein “the second working cycle, the high-side PMOS transistor (QP) is off, the low-side NMOS transistor (QN) is on, the first switch (SW1) is off, and the second switch (SW2) is off.”), and the at least one time point in the second period includes a second time point (See Fig. 2 and all possible time points that exist in the images plotted. Any time point can be found in the necessary region.); and the processing circuit is further configured to adjust the magnitude of the constant current during the second switch cycle based on a comparison result between a first value of the terminal voltage established on the first capacitor at the first time point and a second value of the terminal voltage established on the first capacitor at the second time point (See paragraphs 0019-0024.).
Regarding claim 4, Li Heqing teaches all elements of claim 1, upon which this claim depends.
Li Heqing teaches an interval between the first time point and an end time of a first period in the first switch cycle is smaller than or equal to a first predetermined time length (Any interval can be defined with these attributes based on the plots of Fig. 2.).
Regarding claim 8, Li Heqing teaches all elements of claim 2, upon which this claim depends.
Li Heqing teaches the processing circuit comprises: a current-to-voltage converting circuit configured to convert the low-side detecting current outputted by the first detection circuit into a voltage (Fig. 1 Element Rsen. Paragraph 0019.); a first switch coupled between the second end of the first capacitor and the current-to-voltage converting circuit and configured to be turned off during a first period and turned on during a second period (Fig. 1 Elements Rsen SW3, SW4, & Csample. Paragraph 0019.); a current source circuit configured to provide the constant current (Fig. 1 Element Vin. Paragraph 0019.); a second switch coupled between the current source circuit and the second end of the first capacitor and configured to be turned on during the first period and turned off during the second period (Fig. 1 Elements SW1, SW2, & Csample. Paragraph 0019.); and a voltage-to-current converting circuit coupled to the second end of the first capacitor and configured to convert the terminal voltage established on the first capacitor into the cycle detecting current (See paragraph 0021 wherein it states that “the sampled voltage signal (Vsen_FB) needs to be fed back to the input of the CC error amplifier for constant current control. If it is used as a discrimination signal for the STEP_DOWN converter to switch from continuous operation mode to intermittent operation mode, the sampled voltage signal needs to be input to the input of the DMD comparator for comparison.”).
Regarding claim 9, Li Heqing teaches all elements of claim 8, upon which this claim depends.
Li Heqing teaches the processing circuit further comprises an adjusting circuit coupled to the current source circuit and comprising: a sample and hold circuit configured to sample the terminal voltages established on the first capacitor, thereby acquiring the first value and the second value (Fig. 1 Elements Csample, SW3 and buf. See paragraph 0019 wherein the “third switch (SW3), the sampling capacitor (Csample), and the input signal buffer amplifier (buf) constitute the sample-and-hold circuit.); a comparison circuit configured to compare the first value and the second value provided by the sample and hold circuit, thereby outputting an adjusting signal (Fig. 1 Element DMD comparator. See paragraph 0019.); and a current adjusting circuit configured to adjust the magnitude of the constant current provided by the current source circuit during the second switch cycle based on the adjusting signal (Fig. 1 Element CC error amplifier.).
Regarding claim 15, Li Heqing teaches all elements of claim 1, upon which this claim depends.
Li Heqing teaches the processing circuit is configured to perform the operation during each switch cycle among multiple sets of switch cycles (See paragraphs 0019-0024 wherein the switches are disclosed being turned on & off.).
Regarding Independent claim 16, Li Heqing teaches:
A current detection method for a direct-current to direct-current (DC-DC) converter, the DC-DC converter comprising a high-side transistor and a low-side transistor coupled in series between an input end and a ground, a switch node between the high-side transistor and the low-side transistor being coupled to an inductor, the current detection method, during each switch cycle among a plurality of switch cycles of the DC-DC converter, comprising:
outputting a cycle detecting current (Fig. 1 Elements Isen & Qsen. See paragraphs 0004-0011 & 0019-0024.) based on a terminal voltage established on a second end of a first capacitor (Fig. 1 Elements Rsen & Csample. See paragraphs 0017-0025. “The sampling resistor (Rsen) converts the detected load current (Isen) into a voltage signal.”), wherein a first end of the first capacitor is coupled to the ground (Fig. 1 Element Csample and the ground it is connected to. See paragraphs 0019-0024.);
detecting a current (Fig. 1 Element Isen. See paragraphs 0004-0011 & 0019-0024.) provided by the low-side transistor to the inductor during a turn-on period of the low-side transistor for acquiring a low-side detecting current (Fig. 1 Elements Isen & Qsen. See paragraphs 0004-0011 & 0019-0024.);
increasing the terminal voltage established on the first capacitor using a constant current during a first period (Fig. 1 Elements Rsen & Csample. See paragraphs 0021-0023 wherein the in Csample is disclosed in first working cycle wherein the high-side is off & the low side is on.), wherein the first period is a turn-on period of the high-side transistor or a turn-off period of the low-side transistor (Fig. 1 Elements Rsen & Csample. See paragraphs 0021-0023 wherein the in Csample is disclosed in first working cycle wherein the high-side is off & the low side is on. See also Fig. 2.); and
varying the terminal voltage established on the first capacitor with the low-side detecting current using the low-side detecting current during a second period (See paragraphs 0019-0024.), wherein:
the second period and the first period form a switch cycle of the DC-DC converter (See paragraphs 0019-0024.);
each set of switch cycles includes a first switch cycle and a second switch cycle of the DC-DC converter (See paragraphs 0019-0024.);
the first switch cycle and the second switch cycle are consecutive switch cycles (See paragraphs 0019-0024.);
a magnitude of the constant current during the second switch cycle in each set of switch cycles is determined based on levels of the terminal voltage established on the first capacitor at least at two time points in the first switch cycle (See Fig. 2 and all possible time points that exist in the images plotted. Any two time points can be found in the necessary region. See paragraph 0023 wherein “the second working cycle, the high-side PMOS transistor (QP) is off, the low-side NMOS transistor (QN) is on, the first switch (SW1) is off, and the second switch (SW2) is off.” See paragraphs 0019-0024 wherein the current is fed back into the input of the CC amplifier to maintain the proper level.); and
the at least two time points include at least one time point in the second period when the low-side transistor is turned on (See Fig. 2 and all possible time points that exist in the images plotted. Any two time points can be found in the necessary region. See paragraph 0023 wherein “the second working cycle, the high-side PMOS transistor (QP) is off, the low-side NMOS transistor (QN) is on, the first switch (SW1) is off, and the second switch (SW2) is off.”).
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Regarding claim 17, Li Heqing teaches all elements of claim 16, upon which this claim depends.
Li Heqing teaches the at least two time points include a first time point in the first period when the high-side transistor is turned on (See Fig. 2 and all possible time points that exist in the images plotted. Any two time points can be found in the necessary region. See paragraph 0023 wherein “the second working cycle, the high-side PMOS transistor (QP) is off, the low-side NMOS transistor (QN) is on, the first switch (SW1) is off, and the second switch (SW2) is off.”), and the at least one time point in the second period includes a second time point (See Fig. 2 and all possible time points that exist in the images plotted. Any time point can be found in the necessary region.), the current detection method further comprising: adjusting the magnitude of the constant current during the second switch cycle based on a comparison result between a first value of the terminal voltage established on the first capacitor at the first time point and a second value of the terminal voltage established on the first capacitor at the second time point (See paragraphs 0019-0024.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5-7 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over Li Heqing et al (Translation of CN # 208818756).
Regarding claim 5, Li Heqing teaches all elements of claim 4, upon which this claim depends.
Li Heqing does not explicitly teach the first predetermined time length is equal to 10ns.
But it would have been obvious to one of ordinary skill in the art before the effective time of filing to have the first predetermined time length is equal to 10ns because this is a form of routine optimization wherein one is reducing the amount of time to perform a given task. See MPEP Section 2144.05 II A.
Regarding claim 6, Li Heqing teaches all elements of claim 4, upon which this claim depends.
Li Heqing does not explicitly teach the first predetermined time length is equal to one-tenth of the first period in the first switch cycle.
But it would have been obvious to one of ordinary skill in the art before the effective time of filing to have the first predetermined time length be equal to one-tenth of the first period in the first switch cycle because this is a form of routine optimization wherein one is reducing the amount of time to perform a given task. See MPEP Section 2144.05 II A.
Regarding claim 7, Li Heqing teaches all elements of claim 4, upon which this claim depends.
Li Heqing teaches the first detection circuit includes an operational amplifier (Fig. 1 Element OP.).
Li Heqing does not explicitly teach the second time point is after an end time of a setting time of the operational amplifier during the first switch cycle, and a time length between the end time of the setting time and the second time point is smaller than or equal to a second predetermined time length.
But it would have been obvious to one of ordinary skill in the art before the effective time of filing to have the second time point be after an end time of a setting time of the operational amplifier during the first switch cycle, and a time length between the end time of the setting time and the second time point is smaller than or equal to a second predetermined time length because this is a form of routine optimization wherein one is reducing the amount of time to perform a given task. See MPEP Section 2144.05 II A.
Regarding claim 19, Li Heqing teaches all elements of claim 17, upon which this claim depends.
Li Heqing does not explicitly teach an interval between the first time point and an end time of the first period in the first switch cycle is smaller than or equal to a first predetermined time length.
But it would have been obvious to one of ordinary skill in the art before the effective time of filing to have an interval between the first time point and an end time of the first period in the first switch cycle is smaller than or equal to a first predetermined time length because this is a form of routine optimization wherein one is reducing the amount of time to perform a given task. See MPEP Section 2144.05 II A.
Allowable Subject Matter
Claims 3, 10-14, 18, & 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art listed does not anticipate alone or combine in an obvious manner to teach the invention claimed by applicant.
Regarding claim 3,
The current detection circuit of claim 2, wherein the processing circuit is further configured to: adjust the magnitude of the constant current during the second switch cycle to be smaller than the magnitude of the constant current during the first switch cycle when the first value is larger than the second value; and adjust the magnitude of the constant current during the second switch cycle to be larger than the magnitude of the constant current during the first switch cycle when the first value is smaller than the second value.
Regarding claim 10,
The current detection circuit of claim 9, wherein the current adjusting circuit comprises: a trigger configured to output a trigger signal based on the adjusting signal and a clock signal, wherein: a pulse of the clock signal lasts from a fourth time point to a third time point; the second time point, the third time point and the fourth time point are in the second period of the first switch cycle; the third time point is after the second time point; and the fourth time point is between the second time point and the third time point; and an up/down counter configured to adjust an output number based on the trigger signal so as to match the magnitude of the constant current provided by the current source circuit with the output number.
Regarding claim 11,
The current detection circuit of claim 10, wherein an interval between the second time point and the fourth time point is larger than or equal to a setup time of the trigger.
Regarding claim 12,
The current detection circuit of claim 10, wherein an interval between the fourth time point and the third time point is larger than or equal to a retaining time of the trigger.
Regarding claim 13,
The current detection circuit of claim 8, wherein the sample and hold circuit comprises: a voltage buffering circuit coupled to the second end of the first capacitor ; a third switch coupled between the voltage buffering circuit and a first input end of the comparison circuit; a second capacitor including: a first end coupled to a first node between the third switch and the first input end of the comparison circuit; and a second end coupled to the ground; a fourth switch coupled between the voltage buffering circuit and a second input end of the comparison circuit; and a third capacitor including: a first end coupled to a second node between the fourth switch and the second input end of the comparison circuit; and a second end coupled to the ground.
Regarding claim 14,
The current detection circuit of claim 13, wherein: the third switch is configured to be switched from a turn-on state to a turn-off state at the first time point and switched from the turn-off state to the turn-on state at the third time point, enabling the second capacitor to retain a voltage of the first value between the first time point and the third time point; the second time point and the third time point are in the second period of the first switch cycle, and the third time point is after the second time point; and the fourth switch is configured to be switched from the turn-on state to the turn-off state at the second time point and switched from the turn-off state to the turn-on state at the third time point, enabling the third capacitor to retain a voltage of the second value between the second time point and the third time point.
Regarding claim 18,
The current detection method of claim 17, further comprising: adjusting the magnitude of the constant current during the second switch cycle to be smaller than the magnitude of the constant current during the first switch cycle when the first value is larger than the second value; and adjusting the magnitude of the constant current during the second switch cycle to be larger than the magnitude of the constant current during the first switch cycle when the first value is smaller than the second value.
Regarding claim 20,
The current detection method of claim 19, wherein: the low-side detecting current is detected by a first detection circuit which includes an operational amplifier; the second time point is after an end time of a setting time of the operational amplifier during the first switch cycle; and a time length between the end time of the setting time and the second time point is smaller than or equal to a second predetermined time length.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The prior art listed but not cited represents the previous state of the art and analogous art that teaches some of the limitations claimed by applicant.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER P MCANDREW whose telephone number is (469)295-9025. The examiner can normally be reached Monday-Thursday 6-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lee Rodak can be reached on 571-270-5628. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CHRISTOPHER P MCANDREW/Primary Examiner, Art Unit 2858