Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
2. This office action is in response to communication filed on 06/27/2025. Claims 1 -20 are pending on this application.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
4. Claims 1, 7-10, and 14-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Michel Pub. No. 2023/0012330.
Regarding claim 1. Fig. 13A and Fig. 13B of Michel discloses a switched-capacitor circuit (1310), comprising: a first sampling capacitor array (16Cu….1Cu), configured to sample a first input voltage (Vin) in a sampling phase (samples1); a control circuit (1340), configured to determine magnitude of a first preset voltage (VDD) according to the first input voltage (Vin) , and configured to adjust the first input voltage sampled (Vn) by the first sampling capacitor array (16Cu….1Cu) in a preset phase (convert phase) according to magnitude of the first input voltage (magnitude Vin) , so as to generate a first adjusted voltage (Vresidue); and a charge-transfer circuit (switching current sources VDED/Ground), configured to amplify (VDD/Ground current sources) the first adjusted voltage (Vresidue) in a charge-transfer phase (Phase of E1, E2) so as to generate a first output voltage at a first output terminal (Vsample2 terminal in Fig. 13B) , and configured to provide the first preset voltage (VDD/Ground) to the first output terminal (Vsample2 terminal in Fig. 13B) in the preset phase (convert phase).
Regarding claim 7. The switched-capacitor circuit of claim 1, Fig. 13A and 13B of Michel further discloses wherein the control circuit (1340) comprises: an ADC (paragraph 0071) , configured to (see Fig. 11) compare the first input voltage (Vin in Fig. 11) with a plurality of voltage thresholds (0…FS) , so as to determine a first voltage range (FS) including the first input voltage (Vin in Fig. 11) from a plurality of voltage ranges (0…FS/2…FS in Fig. 11) , and configured to output a first digital code (comp1 in 1340) corresponding to the first voltage range (FS in Fig. 11), wherein the plurality of voltage ranges (0…FS/2…FS in Fig. 11) are identified by the plurality of voltage thresholds arranged in ascending order (ascending order 0…FS/2…FS); and a decoder (SAR controller 1340) , configured to determine the magnitude of the first preset voltage (magnitude of VDD) according to the first digital code (comp1 in 1340) .
Regarding claim 8. The switched-capacitor circuit of claim 7, , Fig. 11, Fig. 13A and Fig. 13B of Michel further discloses wherein when the first input voltage (Vin) is in an M-th voltage range (FS…FS/2) of a plurality of voltage ranges (ranges of voltage 0…FS/2…FS in Fig. 11), the decoder (SAR 1340) is configured to set the first preset voltage (ground 0 in Fig. 11) to be smaller than a common voltage (FS/2), wherein M is a positive integer (positive of SAR Zoom ranges in Fig. 11); and when the first input voltage (Vin) is in an (M+1)-th voltage range (FS/2…0 in Fig. 11) of the plurality of voltage ranges (ranges of voltage 0…FS/2…FS in Fig. 11), the decoder (SAR 1340) is configured to set the first preset voltage (FS in Fig. 11) to be larger than the common voltage (FS/2 in Fig. 11).
Regarding claim 9. The switched-capacitor circuit of claim 7, Fig. 11 further discloses wherein when the first input voltage (Vin) is in a P-th voltage range (0) of the plurality of voltage ranges (0….FS/2….FS) , the decoder (SAR Zoom) is configured to set the first preset voltage (0) to be smaller than a common voltage (FS/2), wherein P is an odd number (first voltage range of 0) , when the first input voltage (Vin) is in a Q-th voltage range (FS) of the plurality of voltage ranges (ranges of voltage 0…FS/2…FS in Fig. 11), the decoder (SAR Zoom) is configured to set the first preset voltage (FS) to be larger than the common voltage (FS/2) , wherein Q is an even number (second voltage range FS).
Regarding claim 10. Fig. 13A and Fig. 13B of Michel discloses a switched-capacitor circuit (1310), comprising: a first sampling capacitor array (16Cu….1Cu), configured to sample a first input voltage (Vin) in a sampling phase (Sample1) ; a control circuit (1340) , configured to determine magnitude of a first reference voltage (Ground/VREF+) and magnitude of a first preset voltage (VDD/Ground switching current sources) according to a relationship between the first input voltage (Vin) and a plurality of voltage thresholds (0…FS/2…FS in Fig. 11), and configured to couple the first reference voltage (Vref) to the first input voltage (Vin) sampled by the first sampling capacitor array (16Cu….1Cu) in a preset phase (Convert switch phase), so as to generate a first adjusted voltage (Vresidue) ; and a charge-transfer circuit (switching current sources) , configured to amplify the first adjusted voltage (Vresidue) in a charge-transfer phase (E1, E2) , so as to generate a first output voltage (Vsample2 in Fig. 13) at a first output terminal (terminal of Vsamples) , and configured provide the first preset voltage (VDD/Ground of current sources) to the first output terminal (Vsample2 in Fig. 13B) in the preset phase (convert switch phase) .
Regarding claim 14. The switched-capacitor circuit of claim 10, Fig. 11, 13A and Fig. 13B of Michel further discloses wherein the control circuit (1340) is configured to compare the first input voltage (Vin in Fig. 11) with the plurality of voltage thresholds (0…FS in Fig. 11) is compared to threshold (0…FS/2…FS in Fig. 11), in a case of the plurality of voltage thresholds (0…FS/2…FS in Fig. 11) being arranged in ascending order (ascending order of 0…FS in Fig. 11), when the first input voltage (Vin in Fig. 11) is adjacent to a J-th voltage threshold (FS/2) of the plurality of voltage thresholds (of 0…FS in Fig. 11), and is smaller than the J-th voltage threshold (FS/2 in Fig. 11) , the control circuit (1340) is configured to set the first preset voltage (Ground in Fig. 11) to be smaller than a common voltage (FS/2 in Fig. 11) , wherein J is an odd number (odd number of F/2…FS in Fig. 11), in the case of the plurality of voltage thresholds of (0…FS in Fig. 11) being arranged in the ascending order (ascending order of 0…FS in Fig. 11), when the first input voltage ( Vin in Fig. 11) is adjacent to the J-th voltage threshold (FS/2 in Fig. 11) , and is larger than or equal to the J-th voltage threshold (FS/2 in Fig. 11) , the control circuit (1340) is configured to set the first preset voltage (FS in Fig. 11) to be larger than the common voltage (FS/2 in Fig. 11).
Regarding claim 15. Fig. 6 of Michel discloses a pipelined ADC, comprising a plurality of converter circuit systems (610, 620, 630; ADC), wherein each converter circuit system (each of 610, 620, 630; ADC) comprises (see Fig. 13A and 13B) : a first sampling capacitor array (16Cu…1Cu) , configured to sample a first input voltage (Vin) in a sampling phase (sampler1) ; a control circuit (1340) , configured to determine magnitude of a first preset voltage (VDD/Ground of current sources) according to the first input voltage (Vin) , and configured to adjust the first input voltage (Vin) sampled by the first sampling capacitor array (16Cu…1Cu) in a preset phase (Convert switching phase) according to magnitude of the first input voltage (magnitude of Vin) , so as to generate a first adjusted voltage (Vresidue) ; and a charge-transfer circuit (switching current sources VDD/Ground) , configured to amplify the first adjusted voltage (Vresidue) in a charge-transfer phase (E1/E2 phase) , so as to generate a first output voltage (Vsample2 in Fig. 13B) at a first output terminal (output terminal of Vsample2 in Fig. 13B) , and configured to provide the first preset voltage (VDD/Ground of current sources) to the first output terminal (Vsample2 terminal in Fig. 13B) in the preset phase (Convert switching phase).
Allowable Subject Matter
5. Claims 2-6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a second sampling capacitor array, configured to sample a second input voltage in the sampling phase, wherein the control circuit is configured to determine the magnitude of the first preset voltage and magnitude of a second preset voltage according to an input voltage difference between the first input voltage and the second input voltage, and configured to adjust the second input voltage sampled by the second sampling capacitor array in the preset phase according to magnitude of the second input voltage, so as to generate a second adjusted voltage, wherein the charge-transfer circuit is configured to amplify the second adjusted voltage in the charge-transfer phase so as to generate a second output voltage at a second output terminal, and configured to provide the second preset voltage to the second output terminal in the preset phase, wherein a phase of the first preset voltage is opposite to a phase of the second preset voltage.
6. Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a second sampling capacitor array, configured to sample a second input voltage in the sampling phase, wherein the control circuit is configured to compare an input voltage difference between the first input voltage and the second input voltage with the plurality of voltage thresholds, so as to determine the magnitude of the first reference voltage, the magnitude of the first preset voltage, magnitude of a second reference voltage and magnitude of a second preset voltage, and configured to couple the second reference voltage to the second input voltage sampled by the second sampling capacitor array in the preset phase, so as to generate a second adjusted voltage, wherein the charge-transfer circuit is configured to amplify the second adjusted voltage in the charge-transfer phase, so as to generate a second output voltage at a second output terminal, and configured to provide the second preset voltage to the second output terminal in the preset phase, wherein a phase of the first preset voltage is opposite to a phase of the second preset voltage.
7. Claims 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Prior art does not teach: a second sampling capacitor array, configured to sample a second input voltage in the sampling phase, wherein the control circuit is configured to determine the magnitude of the first preset voltage and magnitude of a second preset voltage according to an input voltage difference between the first input voltage and the second input voltage, and configured to adjust the second input voltage sampled by the second sampling capacitor array in the preset phase according to magnitude of the second input voltage, so as to generate a second adjusted voltage, wherein the charge-transfer circuit is configured to amplify the second adjusted voltage in the charge-transfer phase, so as to generate a second output voltage at a second output terminal, and configured to provide the second preset voltage to the second output terminal in the preset phase, wherein a phase of the first preset voltage is opposite to a phase of the second preset voltage.
Contact Information
8. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Linh Van Nguyen whose telephone number is (571) 272-1810. The examiner can normally be reached from 8:30 – 5:00 Monday-Friday.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mr. Dameon E. Levi can be reached at (571) 272-2105. The fax phone numbers for the organization where this application or proceeding is assigned are (571-273-8300) for regular communications and (571-273-8300) for After Final communications.
02/12/2026
/LINH V NGUYEN/Primary Examiner, Art Unit 2845