DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to interpretation under 35 U.S.C. 112(f) has been fully considered but is maintained. In particular, although the applicant’s responses may address the hardware limitations of the claimed video decoder, the amendments still do not sufficiently address the structural concerns of the claimed video encoder that encodes and is configured to perform operations. See the claim interpretation to understand the present interpretation.
Applicant’s arguments with respect to claim 3-4 and 12-13 rejected under 35 U.S.C. 112(b) has been fully considered and is withdrawn. However, there are new indefinite limitations which require attention. See the section related to rejections under 35 U.S.C. 112(b) for further details.
Applicant’s arguments with respect to claim(s) 1, 10, and 19 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “encoding, by the video encoder” in claims 1-20.
Review of the specification discloses the following:
-“video encoder”, ¶34 and fig. 4 discloses a “a video encoding device 404 is implemented on a second APD 116B” and ¶23-24 that discloses auxiliary processors 114 that include accelerated processing devices 116 in the form of “central processing unit, graphics processing unit, parallel processing unit” or as “a fixed function processor that processes data according to fixed hardware circuitry”.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-9 and 19-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. In particular, the claimed inventions refer to “the encoder” without disclosing an encoder previously, rendering the claimed encoder indefinite. For the purposes of examination, the first reference to “the encoder” will be interpreted as “an
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1-2,10-11,19 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of- Strom; Jacob et al. (US 20140177971 A1)
Regarding claim 1, Bai teaches,
A method for performing a video transcoding operation, (¶85 and fig. 11-12, “integrated transcoder” depicted in fig. 11 and “method for integrated transcoding” depicted in fig. 12) the method comprising:
receiving, by a video decoder of a computing device, source video data (¶85,55, and fig. 11, “input video elementary stream” into the “Input Decoder (1101)” as depicted in fig. 11 operational with general purpose “computing system”) in a first coding scheme; (¶85 and fig. 11, entropy decoder 1102 recovers “original encoding parameters” of input video elementary stream read into input decoder 1101 depicted in fig. 11)
writing, by the video decoder, (¶85 and fig. 11, “decoding loop 1103” reconstructs video frames as depicted in fig. 11) at least one block of decoded video data from the source video data to a buffer; (¶85 and fig. 11, reconstructed “input video elementary stream” frames from decoding loop 1103 “subsequently written to a Look-ahead buffer memory (1106)” as depicted in fig. 11)
encoding, by the video encoder, (¶85 and fig. 11, “output encoder” 1109 depicted in fig. 11) video data written to the buffer; (¶85 and fig. 11, “output encoder uses the Filtered Video frame” from adaptive post/pre-filter 1107 that uses video frames from “look-ahead buffer memory (1106)” as depicted in fig. 11) into a second coding scheme different from the first coding scheme; (¶85, “encoding parameters of the input video elementary stream into estimates of the output video elementary stream” converted by Input/Output Parameter Translator (1104) depicted in fig. 11)
But does not explicitly teach,
repeating the writing and encoding for a plurality of further iterations, wherein each further iteration is initiated in response to encoding one or more blocks of video data in the second coding scheme,
wherein during the repeating, the writing and the encoding are performed in parallel using direct synchronization independent of an operating system of the computing device.
However, Kazui teaches additionally,
repeating the writing and encoding for a plurality of further iterations, (¶65-67, “source encoding unit 13 generates local decoded picture used to generate prediction for each block to be encoded later “for each block” including output write request for local decoded picture of “blocks of the coding target picture”) wherein each further iteration is initiated (¶58 and 65-67, generate prediction block for each block “in accordance with the coding mode” for “carrying out these processes for each block” for each picture) in response to encoding one or more blocks of video data (¶58 and 65-67, generate prediction block for each block “in accordance with the coding mode selected for each picture”) in the second coding scheme. (¶58 and 65-67, “coding mode selected for each picture”)
Kazui discloses a coding that is repeated for each block of a picture predicted using a select coding mode. It is further capable of repeating this process for each picture being coded. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui which is capable of read and write requests for local decoded picture in a buffer. Using the teachings of Kazui allows for coding that can improve coding efficiency.
Strom teaches additionally,
wherein during the repeating, the writing and the encoding are performed in parallel (¶90, “variable length encoding and the writing to the pixel value buffer can be conducted at least partly in parallel”) using direct synchronization independent of an operating system of the computing device. (¶90 and 110, “write sequence of symbols to the pixel value buffer while variable length encoding other blocks” conducted at least partially in parallel where the “variable length encoder 110” of device 100 “operates serially on the pixel values of the multiple blocks”)
Strom discloses a device which operates in a configuration that serially operates on pixel values. It is a device which also encodes and writes in parallel by writing a sequence of symbols into a pixel value buffer while variable length encoding other blocks. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom which compresses and writes content in parallel. This allows for a technique that can efficiently handle pixel value buffers in connection with a computer graphic system.
Regarding claim 2, Bai with Kazui with Strom teach the limitations of claim 1,
Kazui teaches additionally,
providing, from the video encoder to the video decoder, (¶65-67 and fig. 4, “source encoding unit 13” outputs a write request to “the buffer interface unit 14” as depicted in fig. 4) a request for the block of decoded video; (¶65-67 and fig. 4, “source encoding unit 13” outputs a write request for a local decoded picture “corresponding to all the blocks of the coding target picture” to the buffer interface unit 14) wherein the writing is performed in response to the request. (¶65-67, in response to “request for writing a local decoded picture, the buffer interface unit 14 writes the local decoded picture” corresponding to all the blocks of the coding target picture)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom which is capable of read and write requests for local decoded picture in a buffer. Using the teachings of Kazui allows for coding that can improve coding efficiency.
Regarding claim 10, Bai teaches,
A system for performing a transcoding operation, (¶85 and fig. 11-12, integrated transcoding implemented by “integrated transcoder” depicted in fig. 11) the system comprising:
a video decoder; (¶85 and fig. 11, “Input Decoder (1101)” and various elements depicted in fig. 11) and
a video encoder that is communicatively coupled to the video decoder, (¶85 and fig. 11, “Input Decoder (1101)” comprising an “Entropy Decoder (1102) and a Decoding Loop (1103)” as depicted in fig. 11)
wherein the video decoder is configured to: (¶85 and fig. 11, “Input Decoder (1101)” comprising an “Entropy Decoder (1102) and a Decoding Loop (1103)”)
receive source video data in a first coding scheme; (¶85 and fig. 11, “input video elementary stream” decoded by the Input Decoder (1101) into reconstructed “video frames” as depicted in fig. 11)
write at least one block of decoded video data from the source data to a buffer; (¶85 and fig. 11, “Decoding Loop (1103)” of Input Decoder (1101) reconstructs “the video frames which can be subsequently written to a Look-ahead buffer memory (1106)” as depicted in fig. 11)
wherein the video encoder configured to: (¶85 and fig. 11, “output encoder” 1109 depicted in fig. 11, to “calculate the output bitstream”)
encode video data written to the buffer; (¶85 and fig. 11, “output encoder uses the Filtered Video frame” from adaptive post/pre-filter 1107 that uses video frames from “look-ahead buffer memory (1106)” as depicted in fig. 11) into a second coding scheme different from the first coding scheme; (¶85, “encoding parameters of the input video elementary stream into estimates of the output video elementary stream” converted by Input/Output Parameter Translator (1104) depicted in fig. 11)
But does not explicitly teach,
receiving, from an video encoder, information indicating a block of decoded video; and
wherein the video encoder and the video decoder are collectively configured to:
repeat the write and the encode for a plurality of further iterations, wherein each further iteration is initiated in response to encoding one or more blocks of video data in the second coding scheme, wherein during the plurality of iterations, the write and the encode are performed in parallel using direct synchronization independent of an operating system of the system.
However, Kazui teaches additionally,
wherein the video decoder is configured to: (¶58 and fig. 4, “buffer interface unit 14” receiving “outputs” from source encoding unit 13)
receiving, from an video encoder, (¶58 and fig. 4, “encoding unit 13”, depicted in fig. 4, “outputs a request for reading”) information indicating a block of decoded video; (¶58 and fig. 4, “encoding unit 13”, depicted in fig. 4, “outputs a request for reading” from frame buffer 15 a “local decoded picture” in accordance to selected “coding mode”) and
wherein the video encoder and the video decoder are collectively configured (¶78,65-67, and fig. 4-5, “video encoding apparatus 10 and the video decoding apparatus 20 perform substantially the same operation” which communicate “encoded video” by the video encoding apparatus 10 to the video decoding apparatus 20 depicted in figs. 4 and 5) to:
repeat the writing and encoding for a plurality of further iterations, (¶65-67, “source encoding unit 13 generates local decoded picture used to generate prediction for each block to be encoded later “for each block” including output write request for local decoded picture of “blocks of the coding target picture”) wherein each further iteration is initiated (¶58 and 65-67, generate prediction block for each block “in accordance with the coding mode” for “carrying out these processes for each block” for each picture) in response to encoding one or more blocks of video data (¶58 and 65-67, generate prediction block for each block “in accordance with the coding mode selected for each picture”) in the second coding scheme, (¶58 and 65-67, “coding mode selected for each picture”)
Kazui discloses a coding that is repeated for each block of a picture predicted using a select coding mode. It is further capable of repeating this process for each picture being coded. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui which is capable of read and write requests for local decoded picture in a buffer. Using the teachings of Kazui allows for coding that can improve coding efficiency.
Strom teaches additionally,
wherein during the plurality of iterations, the write and the encode are performed in parallel (¶90, “variable length encoding and the writing to the pixel value buffer can be conducted at least partly in parallel”) using direct synchronization independent of an operating system of the computing device. (¶90 and 110, “write sequence of symbols to the pixel value buffer while variable length encoding other blocks” conducted at least partially in parallel where the “variable length encoder 110” of device 100 “operates serially on the pixel values of the multiple blocks”)
Strom discloses a device which operates in a configuration that serially operates on pixel values. It is a device which also encodes and writes in parallel by writing a sequence of symbols into a pixel value buffer while variable length encoding other blocks. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom which compresses and writes content in parallel. This allows for a technique that can efficiently handle pixel value buffers in connection with a computer graphic system.
Regarding claim 11, Bai with Kazui with Strom teach the limitations of claim 10,
Kazui teaches additionally,
video encoder provides a request (¶65-67 and fig. 4, “source encoding unit 13” outputs a write request) for the block of decoded video (¶65-67 and fig. 4, “source encoding unit 13” outputs a write request for a local decoded picture “corresponding to all the blocks of the coding target picture” to the buffer interface unit 14) to the video decoder; (¶65-67 and fig. 4, “source encoding unit 13” outputs a write request to “the buffer interface unit 14” as depicted in fig. 4) and
the video decoder (¶67, “buffer interface unit 14”) writes the block of decoded video data to the buffer (¶67, buffer interface unit 14 “writes the local decoded picture in the frame buffer 15” corresponding to all the blocks of the coding target picture) in response to the request. (¶67, the buffer interface unit 14 writes the local decoded picture “in response to a request for writing a local decoded picture”)
Kazui discloses a coding that is repeated for each block of a picture predicted using a select coding mode. It is further capable of repeating this process for each picture being coded. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom which is capable of read and write requests for local decoded picture in a buffer. Using the teachings of Kazui allows for coding that can improve coding efficiency.
Regarding claim 19, it is the non-transitory computer readable medium claim of method claim 1.
Bai teaches additionally,
A non-transitory computer-readable medium (¶62 and fig. 3, “system memory 312” depicted in fig. 3 such as “non-volatile memory, such as read only memory (ROM)”) storing instructions (¶62, system memory 312 contains data such as “application software 306” operated by processing unit 303) that, when executed by a computing device, (¶62 and 59, “application software 306” operated by processing unit 303 that can be “an x-86 compatible processor” or “ATHLON 64 processor”) cause the computing device to perform operations (¶62, “application software 306” operated by processing unit 303) comprising:
Refer to rejection of claim 1 to teach the additional limitations of claim 19.
Claim 3,12 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of -Strom; Jacob et al. (US 20140177971 A1) in view of Hsu; Steve Hengchen et al. (US 11595154 B1)
Regarding claim 3, Bai with Kazui with Strom teaches the limitations of claim 2,
Kazui teaches additionally,
buffer is in the video encoder (¶57,55, and fig. 4, “frame buffer 15” as an example of a “decoded picture buffer” DPB in “video encoding apparatus 10” as depicted in fig. 4) and the buffer is divided into N buffer blocks, (¶57,106, Fig. 4 and 8, frame buffer 15 depicted in fig. 4 DPB that includes banks “Bank 0” to “Bank 7” as depicted in fig. 8) where N is an integer greater than one; (¶57 and fig. 8, frame buffer 15 with corresponding “bank numbers” from bank 0 to bank 7 as depicted in fig. 8)
But does not explicitly teach the additional limitations of claim 3,
However, Hsu teaches additionally,
wherein the request for the block of decoded video data in a first iteration (29:7-27, “candidate processing loop” performed for a “number of interleaved sub-blocks”) comprises a request for the video decoder to write N blocks of decoded video data (29:7-27, candidate processing loop performed for a number of interleaved sub-blocks and “writing the sub-blockss in de-interleaved order, into decoder input buffers 1116”) to the buffer. (29:7-27, “decoder input buffers 1116”)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the block processing of Hsu which writes a number of a block to the decoder buffer. This allows for techniques that can support higher throughput.
Regarding claim 12, dependent on claim 11, it is the system claim similar to method claim 3, dependent on claim 2. Refer to rejection of claim 3 to teach the limitations of claim 12.
Claim 4,13 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Takeuchi; Kenshiro (US 20170099494 A1)
Regarding claim 4, Bai with Kazui with Strom teaches the limitations of claim 2,
Kazui teaches additionally,
the buffer is divided into N buffer blocks, (¶57,106, Fig. 4 and 8, frame buffer 15 depicted in fig. 4 DPB that includes banks “Bank0” to “Bank 7” as depicted in fig. 8) wherein N is an integer greater than one; (¶57 and fig. 8, frame buffer 15 with corresponding “bank numbers” from bank 0 to bank 7 as depicted in fig. 8)
But does not explicitly teach the additional limitations of claim 4,
However, Takeuchi teaches additionally,
wherein the request for the block of decoded video data (¶84, “writes the local decoding picture” of combined one or more “local decoding blocks for one picture”) in each of the further iterations (¶84, writes local decoding picture by obtaining “one or more of the local decoding blocks” according to “encoding sequence”) further comprises requesting the video decoder to write a next block (¶84, “decoding unit 29” writes “one or more of the local decoding blocks” according to “the encoding sequence”) of decoded video data into a buffer block (¶84, “buffer 11”) storing decoded video data used for encoding a previous block of video data. (¶84, “decoding unit 29 writes the local decoding picture” by combining one or more of the local decoding blocks according to the “encoding sequence of the each CTU to the buffer 11”)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the sequential writing of Takeuchi which obtains decoding blocks according to an encoding sequence. This allows for implementing techniques that can support solutions able to improve encoding efficiency when coding moving picture data.
Regarding claim 13, dependent on claim 12, it is the system claim similar to method claim 4, dependent on claim 2. Refer to rejection of claim 4 to teach the limitations of claim 13.
Claim 5-6,14-15 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Gao; Wei et al. (US 20190104321 A1)
Regarding claim 5, Bai with Kazui with Strom teach the limitations of claim 1,
But does not explicitly teach the limitations of claim 5,
However, Gao teaches additionally,
video decoder (¶26-27,31 and fig. 1, “video decoder 109” as part of encoding subsystem 102 as depicted in fig. 1) is implemented in a first accelerated processing device, (¶26-27,31 and fig. 1, “video decoder 109” operable to decode “video data with an APU”) and the video encoder (¶26-27,30-31 and fig. 1, “video encoder 108” as part of encoding subsystem 102 as depicted in fig. 1) is implemented in a second accelerated processing device. (¶26-27,30-31 and fig. 1, “video encoder 108” may generate encoded output “video data with an APU”)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the subsystem of Gao which implements encoding and decoding with an APU. This type of hardware is adaptable and can provide the functionality needed for both encode and decode of video data.
Regarding claim 6, Bai with Kazui with Strom with Gao teach the limitations of claim 5,
Gao teaches additionally,
the first (¶26-27,31, and fig. 1, “video decoder 109” depicted in fig. 1) and second accelerated processing devices (¶26-27,31, and fig. 1, “video encoder 108” depicted in fig. 1) are on a same auxiliary processor. (¶26-27,31, and fig. 1, “video decoder 109” and “video encoder 108” both part of the same “encoding subsystem 102” as depicted in fig. 1)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the subsystem of Gao which implements both encoding and decoding with an encoding subsystem. This type of hardware is adaptable and can provide the functionality needed for both encode and decode of video data.
Regarding claim 14, dependent on claim 10, it is the system claim similar to claim 5, dependent on claim 1. Refer to rejection of claim 5 to teach the limitations of claim 14.
Regarding claim 15, dependent on claim 14, it is the system claim similar to claim 6, dependent on claim 5. Refer to rejection of claim 6 to teach the limitations of claim 15.
Claim 7,16 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Tseng; Yi-Chen et al. (US 20240048740 A1)
Regarding claim 7, Bai with Kazui with Strom teaches the limitations of claim 1,
But does not explicitly teach the additional limitations of claim 7,
However, Tseng teaches additionally,
video decoder (¶14 and fig. 1, “image decoder 14” as part of “image processing device 1” depicted in fig. 1) receives the source video data from a USB device (¶17 and fig. 1, receive “input frame IMGi” from a video source such as “a camera”, “a video recorder”, or “other digital image sources”) operating in accordance with a USB Video Class (UVC) standard. (¶14,16-17, and fig. 1, image processing device 1 supports “universal serial bus video class (UVC)” which includes “image decoder 14” as depicted in fig. 1)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the image processing of Tseng which can handle the use of universal serial bus (UVC) standard. Using this standard allows for a system that can adopt other communication standards.
Regarding claim 16, dependent on claim 10, it is the system claim similar to claim 7, dependent on claim 1. Refer to rejection of claim 7 to teach the limitations of claim 16.
Claim 8 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Cheng; Chia-Yun et al. (US 20160029022 A1)
Regarding claim 8, Bai with Kazui with Strom teaches the limitations of claim 1,
But does not explicitly teach the additional limitations of claim 8,
However, Cheng teaches additionally,
a block size of the block of decoded video data (¶60-61 and fig. 7, storage device 705 used to “buffer the decoding result of the smaller-sized coding unit”) written to the buffer (¶60-61 and fig. 7, “storage device 705”, depicted in fig. 7, buffering input coding units “generated from the first processing circuit 701”) is different from a block size of the block of encoded video data in the second coding scheme. (¶6 and fig. 71, “larger-sized coding unit is generated” as output from second processing circuit 703, when coding unit is generated by following from preceding pipeline stage “first processing circuity 701” to following pipeline stage “second processing unit 703” as depicted in fig. 7)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the processing of Cheng which can input smaller units and output larger units. This allows for techniques that can improve decoding efficiency of smaller sized input coding units.
Claim 9,18 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Okamoto; Akira (US 20100037013 A1)
Regarding claim 9, Bai with Kazui with Strom teaches the limitations of claim 2,
But does not explicitly teach the additional limitations of claim 9,
However, Okamoto teaches additionally,
video decoder is inactive (¶88,60, and fig. 1, “idle time is caused” when decoded data D2 is output from decoder 2 “during writing of the decoded data D2” from decoder D2 as shown in fig. 1) and maintains an internal state during a period (¶88 and fig. 1, decoder 2 “writing the decoded data D2 into the memory 1” when “idle time is caused”) between writing the block of decoded video data to the buffer (¶88 and fig. 1, decoder 2 “writing the decoded data D2 into the memory 1” formed by decoding the encoded data D1 as 4 depicted in fig. 1) and receiving a next request for a block of decoded video from the video encoder. (¶88 and fig. 1, decoder 2 writing the decoded data D2 into the memory 1 after “reading out the encoded data D6” from encoder 4 as depicted in fig. 1)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the memory access of Okamoto which has idle time during the writing of decoded data. Incorporating Okamoto allows for effective use of idle time when accessing writing and readout from a memory.
Regarding claim 18, dependent on claim 11, it is the system claim similar to claim 9, dependent on claim 2. Refer to rejection of claim 9 to teach the limitations of claim 18.
Claim 17 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Sundaram; Vijay et al. (US 20210321093 A1)
Regarding claim 17, Bai with Kazui with Strom teaches the limitations of claim 10,
But does not explicitly teach the additional limitations of claim 17,
However, Sundaram teaches additionally,
second coding scheme comprises an AV1 format (¶52,63, and fig. 4, “decoding” proceeds with video coding standards, “such as AV1”) and the video decoder writes at least one block of decoded video data (¶52 and 63, “list decoded blocks” when decoder includes maintaining a buffer which “dynamically gets updated”) by writing a complete row of superblocks to the buffer. (¶52 and 63, “list decoded blocks in an IBC search space buffer” which maintains a buffer that gets “dynamically updated” listing the largest sub-blocks of a super-block in raster orders)
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to combine the integrated transcoder of Bai with the coding control of Kazui with the device of Strom with the AV1 format of Sundaram which stores decoded super blocks. This allows for buffer lists that do not need to store addresses.
Claim 20 rejected under 35 U.S.C. 103 as being unpatentable over Bai; Junfeng et al. (US 20100158126 A1) in view of KAZUI; Kimihiko et al. (US 20160134888 A1) in view of Strom; Jacob et al. (US 20140177971 A1) in view of Hsu; Steve Hengchen et al. (US 11595154 B1) in view of Takeuchi; Kenshiro (US 20170099494 A1)
Regarding claim 20, dependent on claim 19, it is the non-transitory computer-readable medium claim similar to the combination of claim 2 dependent on claim 1, claim 3 dependent on claim 2, and claim 4 dependent on claim 2. Refer to rejection of claims 2, 3, and 4 to teach the limitations of claim 20.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIMMY S LEE whose telephone number is (571)270-7322. The examiner can normally be reached Monday thru Friday 10AM-8PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joseph G. Ustaris can be reached at (571) 272-7383. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JOSEPH G USTARIS/Supervisory Patent Examiner, Art Unit 2483
/JIMMY S LEE/Examiner, Art Unit 2483
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