DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/27/2024, 08/19/2024, 12/03/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata et al. [US 2019/0006306 A1], “Shibata” in view of Obu et al. [US 2018/0309417 A1], “Obu”.
Regarding claim 1, Shibata discloses a semiconductor device (Fig. 2, 100A) comprising:
a semiconductor substrate (Fig. 2, 10, ¶[0040]);
at least one transistor (21a through 21c, ¶[0041]) on the semiconductor substrate (10) and including a plurality of semiconductor layers (Fig. 11, ¶[0086] - ¶[0089] teaches the structure of transistor) ;
an electrode (22a) for the transistor (21a through 21c) ;
an organic insulating film (42, ¶[0042]) having an opening in a region overlapping the transistor and the electrode (as shown) in plan view in a first direction perpendicular to the semiconductor substrate (10); and
a bump (30a) over the at least one transistor (21a through 21c ) in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film (as shown the bump (30a) is electrically connected to electrode (22a) through electrode (23a)),
Shibata does not disclose a width of the bump in a second direction parallel to the semiconductor substrate is smaller than a width of the opening of the organic insulating film in the second direction.
However, Obu discloses a semiconductor device with a plurality of insulation-electrode configurations. In the embodiment of figure 1C, the bonding pad (Fig. 1C, 140) is form over the insulating protective film (121). In an alternative embodiment of figure 24B, the insulating protective film (Fig. 24B, 121) is formed on the first metal film (120) and the semiconductor devices (47). A plurality of openings (122) for bonding are formed in the protective film (121). The openings (122) are disposed at positions which are located inside the first metal film (120) in plan view and which partially overlap the plurality of devices (47). Further, Obu discloses a width of the bonding pad (Fig. 24B, 140) in a second direction parallel to the substrate (40) is smaller than a width of the opening (122) of the insulating protective film (121) in the second direction, in order to prevent the protective film from damages during bonding (¶[0012]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to change the size of the opening in the insulating layer as taught in Obu in the device of Shibata such that a width of the bump in a second direction parallel to the semiconductor substrate is smaller than a width of the opening of the organic insulating film in the second direction because such a modification will prevent the protective film from damages during bonding (¶[0012] of Obu).
Regarding claim 2, Shibata as modified discloses claim 1, Shibata discloses the at least one transistor (Fig. 2, 21a through 21c) includes a plurality of transistors (21a through 21c) that are aligned in the second direction (as shown), and the bump (30a) and the opening of the organic insulating film extend over the plurality of transistors ( as shown).
Regarding claim 3, Shibata as modified discloses claim 1, Shibata as modified discloses an inorganic insulating film (Fig. 2, 41, ¶[0042]) between the semiconductor substrate (10) and the organic insulating film (42), wherein the inorganic insulating film (41) has an opening in a region overlapping the opening of the organic insulating film (42) and the bump in plan view in the first direction, and the bump overlaps a peripheral edge portion of the opening of the inorganic insulating film (as shown) (The Examiner notes the organic layer (42) as modified in claim I is wider than the bump therefore portions of the inorganic insulating film (41) has an opening in a region overlapping the opening of the organic insulating film (42). Further, the Examiner notes the term “overlapping” does not require direct contact between the bump and the inorganic insulating film).
Regarding claim 4, Shibata as modified discloses claim 1, Shibata as modified discloses the bump (Fig. 2 annotated below, 30a) includes a first portion (FP), and a second portion (SP) inside the opening of the organic insulating film (42) and between the first portion (FP) and the transistor (21a-c) in the first direction, and a width of the first portion of the bump is smaller than a width of the second portion of the bump (as shown below).
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Regarding claim 7, Shibata as modified discloses claim 2, Shibata as modified discloses an inorganic insulating film (Fig. 2, 41, ¶[0042]) between the semiconductor substrate (10) and the organic insulating film (42), wherein the inorganic insulating film (41) has an opening in a region overlapping the opening of the organic insulating film (42) and the bump in plan view in the first direction, and the bump overlaps a peripheral edge portion of the opening of the inorganic insulating film (as shown) (The Examiner notes the organic layer (42) as modified in claim I is wider than the bump therefore portions of the inorganic insulating film (41) has an opening in a region overlapping the opening of the organic insulating film (42). Further, the Examiner notes the term “overlapping” does not require direct contact between the bump and the inorganic insulating film).
Regarding claim 8, Shibata as modified discloses claim 2, Shibata as modified discloses the bump (Fig. 2 annotated above, 30a) includes a first portion (FP), and a second portion (SP) inside the opening of the organic insulating film (42) and between the first portion (FP) and the transistor (21a-c) in the first direction, and a width of the first portion of the bump is smaller than a width of the second portion of the bump (as shown below).
Regarding claim 9, Shibata as modified discloses claim 3, Shibata as modified discloses the bump (Fig. 2 annotated above, 30a) includes a first portion (FP), and a second portion (SP) inside the opening of the organic insulating film (42) and between the first portion (FP) and the transistor (21a-c) in the first direction, and a width of the first portion of the bump is smaller than a width of the second portion of the bump (as shown below).
Regarding claim 10, Shibata as modified discloses claim 7, Shibata as modified discloses the bump (Fig. 2 annotated above, 30a) includes a first portion (FP), and a second portion (SP) inside the opening of the organic insulating film (42) and between the first portion (FP) and the transistor (21a-c) in the first direction, and a width of the first portion of the bump is smaller than a width of the second portion of the bump (as shown below).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shibata et al. [US 2019/0006306 A1], “Shibata”.
Regarding claim 13, Shibata discloses a semiconductor device (Fig. 2, 100A) comprising:
a semiconductor substrate (10);
at least one transistor (21a-21c) on the semiconductor substrate (10) and including a plurality of semiconductor layers (Fig. 11, ¶[0086] - ¶[0089] teaches the structure of transistor);
an electrode (22a) for the transistor (21a through 21c);
an organic insulating film (42, ¶[0042]) having an opening in a region overlapping the transistor and the electrode in plan view in a first direction perpendicular to the semiconductor substrate (as shown); and
a bump (30a plus 24a) over the at least one transistor (21a through 21c ) in plan view in the first direction and electrically connected to the electrode through the opening of the organic insulating film (as shown the bump (30a) is electrically connected to electrode (22a) through electrode (23a)),
wherein a width of the bump in a second direction parallel to the semiconductor substrate is equal to a width of the opening of the organic insulating film in the second direction (as shown the lower part of the bump is equal to opening of the organic insulating film).
Regarding claim 14, Shibata as modified discloses claim 13, Shibata discloses the bump (Fig. 2 annotated above, 30a) includes a first portion (FP), and a second portion (SP) inside the opening of the organic insulating film (42) and between the first portion (FP) and the transistor (21a-c) in the first direction, and a width of the first portion of the bump is smaller than a width of the second portion of the bump (as shown below).
Allowable Subject Matter
Claims 5, 6, 11, and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakatani et al. [US 2003/0030142 A1] discloses an electrode structure an first insulating film between the semiconductor substrate and the second insulating film, wherein the first insulating film has an opening in a region overlapping the opening of the second insulating film and the bump in plan view in the first direction, and the bump overlaps a peripheral edge portion of the opening of the first insulating film (Fig. 15).
Sasaki et al. [US 2018/0247926 A1] discloses an insulating protective film covers the pad conductive layer. The insulating protective film includes an opening that exposes a partial area of a surface of the pad conductive layer, and that covers another area. A first bump is formed on the pad conductive layer on a bottom surface of the opening, and a second bump at least partially overlaps the protection circuit in plan view .
Abrokwah et al. [US 9,508,661 B2] disclose a metal layer is disposed over a top surface the dielectric layer and the transistor.
Dungan et al [US 2019/0131175 A1] disclose a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor.
Shibata et al. [US 2020/0194394 A1] disclose a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
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