DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/27/2026 has been entered.
Response to Amendment
This office action is in response to the amendment filed on 03/27/2026. Claims 1-9 are pending. Claims 1-4 and 6-9 are amended.
Response to Arguments
Applicant's arguments filed 03/27/2026 have been fully considered but they are not persuasive.
On page 5 of the Remarks, Applicant argues, with respect to the drawing objection for not showing features of claim 2, that claim 2 has been amended to recite “the arithmetic pipeline outputs, to the instruction issuer, inhibition information…” which is allegedly shown in Figs. 9 and 10. However, this argument is not persuasive because Fig. 9 shows the address generator outputting inhibition information to the RSE, however, the address generator is shown to be separate from the arithmetic unit 72 in Fig. 9, and Fig. 10 shows INHB being received by the RSE but does not show the arithmetic pipeline outputting INHB. The Examiner understands the load pipeline to include the address generator of execution unit 70 and the load-store unit 80, as shown in Fig. 7, and the arithmetic pipeline to include the fixed-point arithmetic unit 72 of execution unit 70 as shown in Fig. 8. Since there is no indication that the address generator of the execution unit 70 is included in the arithmetic pipeline (none of the figures that show the arithmetic pipeline show it as including the address generator) and since Fig. 7 clearly shows the address generator as part of the load pipeline, a 112(a) rejection for claim 2 is given below.
On page 8 of the Remarks, Applicant submits that Huck does not teach "a selector configured to selectively output the second data when the second data is output from the load pipeline, and selectively output the arithmetic result data output from the arithmetic unit when the second data is not output from the load pipeline; and a register file including a first port configured to directly receive the first data output from the load pipeline, a second port configured to directly receive the second data or the arithmetic result data selectively output from the selector, and a plurality of registers configured to hold the data received by the first port or the second port" and argues, with respect to Huck, that “The first multiplexer 410 is not configured to selectively output the memory data signal 408b when the memory data signal 408b is output from the memory 404, nor is the first multiplexer 410 configured to selectively output arithmetic result data output from an arithmetic unit or processor 402 when the memory data signal 408b is not output from the memory 404.” and that “There is no direct path from the memory 404 to a register port of the register file 416, and Huck does not disclose or suggest a configuration in which a register port of the register file 416 directly receives the memory data signal 408a or 408b from the memory 404.”
However, this argument is not persuasive because it only considers Huck individually and does not consider how Chan and Huck are combined in the rejection to teach the claimed selector and register file. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The rejection modifies the load pipeline of Chan to support the load pair instruction of Huck by using the shared multiplexer 862 (see Chan Fig. 8) to load the second data of the load pair instruction (as suggested by Huck’s use of multiplexer 410 to load data from memory).
Applicant’s argument that “The first multiplexer 410 is not configured to selectively output the memory data signal 408b when the memory data signal 408b is output from the memory 404, nor is the first multiplexer 410 configured to selectively output arithmetic result data output from an arithmetic unit or processor 402 when the memory data signal 408b is not output from the memory 404.” is not persuasive because it does not consider that the combination of Chan and Huck would selectively output second data from the shared multiplexer when it is output from memory as a result of executing a load pair instruction, otherwise the shared multiplexer would output arithmetic result data when there is a bubble (i.e., when second data is not output) as suggested by Chan’s disclosure of giving port 230 to pipeline 210G-6C when there is a bubble.
Applicant’s argument that “There is no direct path from the memory 404 to a register port of the register file 416, and Huck does not disclose or suggest a configuration in which a register port of the register file 416 directly receives the memory data signal 408a or 408b from the memory 404.” is not persuasive because it does not consider that Chan teaches that the load pipeline 210 GL has its own write port 240, see col 4 lines 46-58, which discloses “a first port configured to directly receive the first data output from the load pipeline” in the combination.
Applicant’s argument that “Chan does not disclose or suggest a configuration in which one of the two data from the pipeline 210 is not supplied to the shared multiplexer 862, and there is no disclosure or suggestion in Chan with regard to the register file 220 including a first port 240 configured to directly receive the first data output from the pipeline 210, and a second port 230 configured to directly receive the second data or the arithmetic result data from the LSU 250 selectively output from the shared multiplexer 862” is not persuasive because Chan discloses that pipeline 210 GL has its own write port 240 which does not supply data to the shared multiplexer 862, see col 4 lines 46-58, and the combination with Huck would receive the second data or arithmetic result data selectively output from the shared multiplexer.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. The following features must be shown or canceled from the claims:
The arithmetic pipeline outputting inhibition information to the instruction issuer (claim 2)- Fig. 9 shows the address generator outputting inhibition information to the RSE, however, the address generator is shown to be separate from the arithmetic unit 72 in Fig. 9. Fig. 10 shows INHB being received by the RSE but does not show the arithmetic pipeline outputting INHB.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites “a load pipeline… configured to read… from the memory” which suggests that the memory is separate from the load pipeline, however, Fig. 1 shows a memory that is part of the load pipeline. Examiner suggests replacing “read” with --output-- (i.e., a load pipeline… configured to output first data and second data… from the memory)
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 2-4 and 9 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 2 recites “the arithmetic pipeline outputs, to the instruction issuer, inhibition information…” in lines 3-4. However, the specification does not describe the arithmetic pipeline as outputting the inhibition information. Instead, [0063] of the specification discloses that the address generator outputs the inhibition information and Fig. 7 shows the address generator as part of the load pipeline, which supports that the load pipeline outputs the inhibition information. Fig. 9 shows the address generator outputting INHB but the address generator is shown to be separate from the arithmetic unit 72 and Fig. 10 does not show any inhibition information being output from the arithmetic pipeline 70A, the INHB signal in Fig. 10 does not come from the arithmetic pipeline shown in Fig. 10.
Claim 4 recites “the instruction issuer that is inhibited of the issuance of the arithmetic instruction” in lines 4-5. The wording of this limitation is interpreted as the arithmetic instruction is inhibited from being issued to the instruction issuer. However, the specification does not describe inhibiting the issuance of the arithmetic instruction to the instruction issuer. Instead, [0068] discloses that the address generator outputs inhibition information to the RSE (which is understood to be the instruction issuer) and the RSE inhibits the issuance of the arithmetic instruction, which is different from the RSE itself being “inhibited of the issuance of the arithmetic instruction”.
Claim 9 recites “the instruction issuer is inhibited of the issuance of the arithmetic instruction” in lines 2-3. The wording of this limitation is interpreted as the arithmetic instruction is inhibited from being issued to the instruction issuer. However, the specification does not describe inhibiting the issuance of the arithmetic instruction to the instruction issuer. Instead, [0068] discloses that the address generator outputs inhibition information to the RSE (which is understood to be the instruction issuer) and the RSE inhibits the issuance of the arithmetic instruction, which is different from the RSE itself being “inhibited of the issuance of the arithmetic instruction”.
Claims dependent on a rejected base claim are further rejected based on their dependence.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380.
Regarding claim 1, Chan teaches:
1. A processor comprising:
an arithmetic pipeline (Fig. 4 pipeline 210G-6C) including an arithmetic unit configured to execute an arithmetic instruction and output arithmetic result data (col 5 line 4: pipeline 210G-6C (see Fig. 4) executes six cycle latency instructions and Addendum 1 shows 6 cycle GFU arithmetic instructions, which indicates that 210G-6C is an arithmetic pipeline that includes an arithmetic unit that executes an arithmetic instruction and the output of the execution is arithmetic result data);
a load pipeline including a memory (Fig. 4 pipeline 210GL and the memory it communicates with (see col 4 lines 46-49)) configured to read first data from the memory based on a first load instruction, and output the read first data, the first data amounting to one unit of data (col 4 lines 46-58: pipeline 210GL (see Fig. 4) executes memory access instructions such as register loads and communicates with the memory, which indicates that 210GL reads data from the memory based on a register load instruction and the output from memory is read first data, the);
a selector configured to selectively output the arithmetic result data output from the arithmetic unit (Fig. 8: multiplexer 862 is a selector that selects an output of 210G-6C); and
a register file (Fig. 1, 220) including a first port configured to directly receive the first data output from the load pipeline (col 4 lines 46-58: the load pipeline 210 GL has its own write port 240, which is a first port that receives data directly from the load pipeline), a second port configured to directly receive the arithmetic result data selectively output from the selector (col 3 lines 53-55 discloses a separate write port 230 for each functional unit 120 (including GFU 120.0), which is shared by the GFU pipelines, see col 4 lines 64-65, using multiplexer 862 of the GFU to output data to the write port 230, see col 8 lines 32-39 and Fig. 8; that is, the GFU write port 230 is a second port that directly receives the data output from the multiplexer/selector of the GFU), and a plurality of registers configured to hold the data received by the first port or the second port, wherein:
each register of the plurality of registers is configured to hold data amounting to one unit (the registers of the register file 220, see Fig. 1, are a plurality of registers that hold data received by 230 or 240, any data stored in each register is a unit of data);
the arithmetic result data is stored in one register of the plurality of registers specified by the arithmetic instruction (Fig. 4 shows pipeline 210G-6C sending results to the writeback stage and col 3 lines 44-45 discloses that the writeback stage stored instruction results to the register file, which indicates that the arithmetic result data of the pipeline 210G-6C is stored in a register specified by the arithmetic instruction executed by the pipeline, see also col 19 lines 1-3 describing instructions that have a destination register specifier rd, which also indicates that the arithmetic instruction specifies a destination register to store its results to)
Chan does not teach:
a load pipeline configured to read first data and second data, amounting to two units of data, in parallel from a memory based on a first load instruction, and output the read first data and second data, the second data amounting to one unit of data;
a selector configured to selectively output the second data when the second data is output from the load pipeline, and selectively output the arithmetic result data output from the arithmetic unit when the second data is not output from the load pipeline;
the first data and the second data are stored in two registers of the plurality of registers specified by the first load instruction,
the first load instruction updates values of the two registers of the plurality of registers, and
However, Huck teaches:
loading first data and second data in parallel from a memory based on a first load instruction, and output the read first data and second data (col 8 lines 17-31: the load pair instruction 200 loads a pair of independent registers from a pair of memory locations in a single processor cycle; that is, the load pair instruction loads first and second data in parallel and outputs the read first data and second data from memory);
a selector configured to select the second data when the second data is output (Fig. 4: multiplexor 410 is a selector that selects the second data when it is output from the memory).
wherein the first data and the second data are stored in two registers specified by the first load instruction, the first load instruction updates values of the two registers of the plurality of registers (col 6 lines 44-50: the load pair instruction 200 specifies a first target register to load/update with the first data and a second target register to load/update with the second data, see also Fig. 4 showing the load pair instruction 200 specifying target 1 and target 2);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the load pipeline of Chan to support the load pair instruction of Huck by adding an input to shared multiplexer 862 for the load pipeline 210GL to use for the second data of a load pair instruction. In this combination, the load pipeline will read first data and second data in parallel from memory, the shared multiplexer 862 will select the read second data when it is output, otherwise it may select the output of pipeline 210G-6C when the second data is not output (see Chan col 5 lines 23-24 describing that port 230 is only given to pipeline 210G-6C when there is a bubble), and the first data and second data will be stored in two registers. One of ordinary skill in the art would have been motivated to make this modification to improve efficiency over conventional register load instructions that load only a single register (Huck col 8 lines 26 -31).
Regarding claim 7, Chan in view of Huck teaches:
7. The processor as claimed in claim 1, wherein:
the load pipeline reads data amounting to one unit of data from the memory based on a second load instruction, and outputs the read data to the first port as the first data (Chan col 3 lines 56-58 describes writing results of load instructions to the register file via write port 240 and col 4 lines 46-49 describes the load pipeline 210 GL executing register loads and communicating with cache and memory, this indicates that the load instructions of Chan reads data from the memory and outputs the read data to the first port 240, any one of the load instructions of Chan may be a second load instruction and any data read and output to port 240 by that instruction is a unit of data), and
the second load instruction updates a value of one register of the plurality of registers (Chan col 3 lines 56-58 describes writing results of load instructions to the register file, any register that the second load instruction writes the read data to will update a value of that register).
Regarding claim 8, Chan in view of Huck teaches:
8. The processor as claimed in claim 1, wherein the load pipeline generates data selection information based on information indicating execution of the first load instruction transmitted within the load pipeline, and supplies the data selection information to the selector to control the selector to selectively output the second data (Chan teaches that circuit 880 controls the multiplexer 862 selection (i.e., by generating data selection information) based a valid signal, see col 8 lines 31-45; in the combination, the circuit 880 would generate the selection information for controlling the multiplexer 862 from a valid load signal (i.e., information indicating execution of the first load instruction transmitted within the load pipeline) to control the multiplexer to select the second data read by the first load instruction).
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380 and Hinton US 5,555,432
Regarding claim 2, Chan in view of Huck teaches:
2. The processor as claimed in claim 1,
Chan in view of Huck does not teach:
an instruction issuer configured to issue the arithmetic instruction,
wherein the load pipeline outputs, to the instruction issuer, inhibition information for inhibiting issuance of the arithmetic instruction for outputting the arithmetic result data to the selector in a cycle identical to a cycle in which the second data is output to the selector based on the first load instruction.
However, Hinton teaches:
an instruction issuer configured to issue an instruction (col 5 lines 14-18: the reservation station 105 is an instruction issuer that issues/dispatches instructions),
wherein an execution unit outputs, to the instruction issuer, inhibition information for inhibiting issuance of the instruction (col 7 lines 7-32: an execution unit sends/outputs inhibit signals (i.e., inhibition information) over bus 114 (which goes to the reservation station/instruction issuer, see Figure 2) for inhibiting scheduling/issuance of an instruction with an execution time corresponding to the inhibit signal).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the processor of Chan in view of Huck to inhibit issuing instructions to prevent write port conflicts as taught by Hinton such that the combination would include a reservation station that receives inhibition signals from the arithmetic pipeline for inhibiting issuance of any instruction (including arithmetic instructions) that would complete execution in the same cycle as an already executing load instruction (i.e., inhibit issuance of the arithmetic instruction for outputting the arithmetic result data to the selector in a cycle identical to a cycle in which the second data is output to the selector based on the first load instruction). One of ordinary skill in the art would have been motivated to make this modification to efficiently issue instructions such that they do not conflict for the write port (Hinton col 7 lines 7-12).
Regarding claim 3, Chan in view of Huck and Hinton teaches:
3. The processor as claimed in claim 2, wherein an output timing of the inhibition information to the instruction issuer is set such that a number of cycles from the output of the inhibition information to the output of the second data to the selector is equal to a number of cycles from the issuance of the arithmetic instruction to the output of the arithmetic result data to the selector (Hinton col 7 lines 7-32 describes sending inhibit signals corresponding to different execution times to prevent issuing an instruction with an execution time that would complete execution during the same clock cycle as an already executing instruction, this indicates that the inhibit signal has an output timing that is set to equal the number of cycles that a conflicting instruction (which may be an arithmetic instruction in the combination) would take to complete (from its issuance to outputting its result to the multiplexer/selector)).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380 and Sidman US 5,680,641.
Regarding claim 5, Chan in view of Huck teaches:
5. The processor as claimed in claim 1,
Chan in view of Huck does not teach:
wherein the load pipeline outputs, to the selector, data selection information for causing the selector to select the second data, in a cycle in which the second data is output to the selector.
However, Sidman teaches a load/store control logic that outputs selection information to a multiplexer that connects an ALU and data bus to a register bank port (which is analogous to the multiplexer 862 of Chan), see col 5 lines 33-36 and lines 43-50.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the load pipeline of Chan in view of Huck to include the load/store control logic of Sidman such that the load pipeline of the combination would output data selection information that causes the multiplexer to select the second data when the second data is output to the multiplexer. One of ordinary skill in the art would have been motivated to make this modification to efficiently control the multiplexer from the load pipeline to select data when it is output.
Regarding claim 6, Chan in view of Huck and Sidman teaches:
6. The processor as claimed in claim 5, wherein the load pipeline generates the data selection information based on information indicating execution of the first load instruction transmitted within the load pipeline (Sidman col 5 lines 43-50 indicates that the load/store control logic generates the selection information using information from the instruction decode and logic control block, in the combination, the load/store control logic of the load pipeline will generate the data selection information (to select the second data loaded by the load pair instruction) using information indicating execution of the load pair instruction transmitted within the pipeline from the decoder).
Prior Art Considerations
Examiner notes that the amendments to claims 4 and 9 describing the instruction issuer being inhibited of the issuance of the arithmetic instruction overcomes the previous rejection, therefore the prior art rejection of claims 4 and 9 has been withdrawn. However, these claims are currently rejected under 112(a) as the amendments raise written description issues. Examiner further notes that amendments to overcome the 112(a) rejection would likely affect the prior art considerations given for these claims.
Conclusion
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/KASIM ALLI/Examiner, Art Unit 2182 /JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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