DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in response to the amendment filed on 08/17/2026. Claims 1-9 are pending. Claims 1-4 and 9 are amended.
Response to Arguments
Applicant's arguments filed 08/17/2026 have been fully considered but they are not persuasive.
In response to applicant's arguments against Chan and Huck individually with respect to claim 1 (see Remarks, pages 7-8) and claim 8 (see Remarks, pages 9), one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
On page 8 of the Remarks, Applicant submits:
The Office Action alleges that it would have been obvious to one of ordinary skill in the art to modify the load pipeline (210GL) of Chan to support the load pair instruction (200) of Huck by adding an input to the multiplexer (862) for the second data.
However, combining Chan and Huck in this manner does not arrive at the structure of amended independent claim 1. In Huck, the memory data signals (408a, 408b) output from the memory (404) pass through the multiplexors (410, 420) to reach the register ports (416a, 416b). Neither Chan nor Huck discloses or suggests a register file (74A) having a first port (WP1) configured to directly receive first data from a load pipeline, and a second port (WP2) configured to directly receive second data from the load pipeline or arithmetic result data from an arithmetic unit (72) selectively output from a selector (73).
However, this argument is not persuasive because it does not consider that the write port 240 of Chan is a first port configured to directly receive first data from the load pipeline and shared write port 230 (which is connected to the output of the multiplexer 862) of the combination is a second port configured to directly receive second data from the load pipeline (as the combination modifies the multiplexer 862 to input the second data from the load pipeline) or arithmetic result data from the arithmetic pipeline (as Chan teaches the multiplexer 862 receives result data from the arithmetic pipeline 210G-6C, see Fig. 8) selectively output from the selector/multiplexor 862. Thus, the combination of Chan and Huck would arrive at the structure of claim 1.
On pages 9-10 of the Remarks, Applicant submits:
In the asserted combination, the Office Action alleges that Chan's circuit 880 generates selection control based on a "valid load signal". However, in the present invention, the load pipeline transmits information INF indicating execution of the first load instruction (LDP) within the load pipeline and outputs that transmitted information as data selection information DSEL to selector 73.
Neither Chan nor Huck discloses or suggests generating data selection information based on information indicating execution of a load instruction transmitted within a load pipeline and supplying the data selection information to a selector to control the selector to selectively output second data.
However, this argument is not persuasive because it does not consider that the valid load signal of the combination (which would indicate a valid instruction in the pipeline, analogous to the valid instruction signals described in col 8 lines 5-22 of Chan) is information indicating execution of the load instruction transmitted within the load pipeline that would be used to generate data selection information using circuit 880 to control the selector/multiplexer 862 (analogous to how circuit 880 uses the valid instruction signals to control multiplexer 862) to selectively output the second data (which is provided to the multiplexer 862 in the combination).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380.
Regarding claim 1, Chan teaches:
1. A processor comprising:
an arithmetic pipeline (Fig. 4 pipeline 210G-6C) including an arithmetic unit configured to execute an arithmetic instruction and output arithmetic result data (col 5 line 4: pipeline 210G-6C (see Fig. 4) executes six cycle latency instructions and Addendum 1 shows 6 cycle GFU arithmetic instructions, which indicates that 210G-6C is an arithmetic pipeline that includes an arithmetic unit that executes an arithmetic instruction and the output of the execution is arithmetic result data);
a load pipeline including a memory (Fig. 4 pipeline 210GL and the memory it communicates with (see col 4 lines 46-49)) configured to output first data from the memory based on a first load instruction, the first data amounting to one unit of data (col 4 lines 46-58: pipeline 210GL (see Fig. 4) executes memory access instructions such as register loads and communicates with the memory, which indicates that 210GL outputs first data from the memory based on a register load instruction);
a selector configured to selectively output the arithmetic result data output from the arithmetic unit (Fig. 8: multiplexer 862 is a selector that selects an output of 210G-6C); and
a register file (Fig. 1, 220) including a first port configured to directly receive the first data output from the load pipeline (col 4 lines 46-58: the load pipeline 210 GL has its own write port 240, which is a first port that receives data directly from the load pipeline), a second port configured to directly receive the arithmetic result data selectively output from the selector (col 3 lines 53-55 discloses a separate write port 230 for each functional unit 120 (including GFU 120.0), which is shared by the GFU pipelines, see col 4 lines 64-65, using multiplexer 862 of the GFU to output data to the write port 230, see col 8 lines 32-39 and Fig. 8; that is, the GFU write port 230 is a second port that directly receives the data output from the multiplexer/selector of the GFU), and a plurality of registers configured to hold the data received by the first port or the second port, wherein:
each register of the plurality of registers is configured to hold data amounting to one unit (the registers of the register file 220, see Fig. 1, are a plurality of registers that hold data received by 230 or 240, any data stored in each register is a unit of data);
the arithmetic result data is stored in one register of the plurality of registers specified by the arithmetic instruction (Fig. 4 shows pipeline 210G-6C sending results to the writeback stage and col 3 lines 44-45 discloses that the writeback stage stored instruction results to the register file, which indicates that the arithmetic result data of the pipeline 210G-6C is stored in a register specified by the arithmetic instruction executed by the pipeline, see also col 19 lines 1-3 describing instructions that have a destination register specifier rd, which also indicates that the arithmetic instruction specifies a destination register to store its results to)
Chan does not teach:
a load pipeline configured to output first data and second data, amounting to two units of data, in parallel from a memory based on a first load instruction, the second data amounting to one unit of data;
a selector configured to selectively output the second data when the second data is output from the load pipeline, and selectively output the arithmetic result data output from the arithmetic unit when the second data is not output from the load pipeline;
the first data and the second data are stored in two registers of the plurality of registers specified by the first load instruction,
the first load instruction updates values of the two registers of the plurality of registers, and
However, Huck teaches:
loading first data and second data in parallel from a memory based on a first load instruction, and output the first data and second data (col 8 lines 17-31: the load pair instruction 200 loads a pair of independent registers from a pair of memory locations in a single processor cycle; that is, the load pair instruction loads first and second data in parallel and outputs the read first data and second data from memory);
a selector configured to select the second data when the second data is output (Fig. 4: multiplexor 410 is a selector that selects the second data when it is output from the memory).
wherein the first data and the second data are stored in two registers specified by the first load instruction, the first load instruction updates values of the two registers of the plurality of registers (col 6 lines 44-50: the load pair instruction 200 specifies a first target register to load/update with the first data and a second target register to load/update with the second data, see also Fig. 4 showing the load pair instruction 200 specifying target 1 and target 2);
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the load pipeline of Chan to support the load pair instruction of Huck by adding an input to shared multiplexer 862 for the load pipeline 210GL to use for the second data of a load pair instruction. In this combination, the load pipeline will read first data and second data in parallel from memory, the shared multiplexer 862 will select the read second data when it is output, otherwise it may select the output of pipeline 210G-6C when the second data is not output (see Chan col 5 lines 23-24 describing that port 230 is only given to pipeline 210G-6C when there is a bubble), and the first data and second data will be stored in two registers. One of ordinary skill in the art would have been motivated to make this modification to improve efficiency over conventional register load instructions that load only a single register (Huck col 8 lines 26 -31).
Regarding claim 7, Chan in view of Huck teaches:
7. The processor as claimed in claim 1, wherein:
the load pipeline reads data amounting to one unit of data from the memory based on a second load instruction, and outputs the read data to the first port as the first data (Chan col 3 lines 56-58 describes writing results of load instructions to the register file via write port 240 and col 4 lines 46-49 describes the load pipeline 210 GL executing register loads and communicating with cache and memory, this indicates that the load instructions of Chan reads data from the memory and outputs the read data to the first port 240, any one of the load instructions of Chan may be a second load instruction and any data read and output to port 240 by that instruction is a unit of data), and
the second load instruction updates a value of one register of the plurality of registers (Chan col 3 lines 56-58 describes writing results of load instructions to the register file, any register that the second load instruction writes the read data to will update a value of that register).
Regarding claim 8, Chan in view of Huck teaches:
8. The processor as claimed in claim 1, wherein the load pipeline generates data selection information based on information indicating execution of the first load instruction transmitted within the load pipeline, and supplies the data selection information to the selector to control the selector to selectively output the second data (Chan teaches that circuit 880 controls the multiplexer 862 selection (i.e., by generating data selection information) based a valid signal, see col 8 lines 31-45; in the combination, the circuit 880 would generate the selection information for controlling the multiplexer 862 from a valid load signal (i.e., information indicating execution of the first load instruction transmitted within the load pipeline) to control the multiplexer to select the second data read by the first load instruction).
Claims 2-3 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380 and Hinton US 5,555,432
Regarding claim 2, Chan in view of Huck teaches:
2. The processor as claimed in claim 1,
Chan in view of Huck does not teach:
an instruction issuer configured to issue the arithmetic instruction,
wherein the load pipeline outputs, to the instruction issuer, inhibition information for inhibiting issuance of the arithmetic instruction for outputting the arithmetic result data to the selector in a cycle identical to a cycle in which the second data is output to the selector based on the first load instruction.
However, Hinton teaches:
an instruction issuer configured to issue an instruction (col 5 lines 14-18: the reservation station 105 is an instruction issuer that issues/dispatches instructions),
wherein an execution unit outputs, to the instruction issuer, inhibition information for inhibiting issuance of the instruction (col 7 lines 7-32: an execution unit sends/outputs inhibit signals (i.e., inhibition information) over bus 114 (which goes to the reservation station/instruction issuer, see Figure 2) for inhibiting scheduling/issuance of an instruction with an execution time corresponding to the inhibit signal).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the processor of Chan in view of Huck to inhibit issuing instructions to prevent write port conflicts as taught by Hinton such that the combination would include a reservation station that receives inhibition signals from the load pipeline for inhibiting issuance of any instruction (including arithmetic instructions) that would complete execution in the same cycle as an already executing load instruction (i.e., inhibit issuance of the arithmetic instruction for outputting the arithmetic result data to the selector in a cycle identical to a cycle in which the second data is output to the selector based on the first load instruction). One of ordinary skill in the art would have been motivated to make this modification to efficiently issue instructions such that they do not conflict for the write port (Hinton col 7 lines 7-12).
Regarding claim 3, Chan in view of Huck and Hinton teaches:
3. The processor as claimed in claim 2, wherein an output timing of the inhibition information from the load pipeline to the instruction issuer is set such that a number of cycles from the output of the inhibition information to the output of the second data to the selector is equal to a number of cycles from the issuance of the arithmetic instruction to the output of the arithmetic result data to the selector (Hinton col 7 lines 7-32 describes sending inhibit signals corresponding to different execution times to prevent issuing an instruction with an execution time that would complete execution during the same clock cycle as an already executing instruction, this indicates that the inhibit signal from the load pipeline of the combination would have an output timing that is set to equal the number of cycles that a conflicting instruction (which may be an arithmetic instruction in the combination) would take to complete (from its issuance to outputting its result to the multiplexer/selector)).
Regarding claim 9, Chan in view of Huck and Hinton teaches:
9. The processor as claimed in claim 2, wherein:
the instruction issue inhibits the issuance of the arithmetic instruction in a specific cycle next to a cycle in which the inhibition information is output from the load pipeline to the instruction issuer (in the combination, the reservation station will inhibit issuing the arithmetic instruction to the arithmetic pipeline after (i.e., in a cycle next to a cycle in which) it receives inhibition information output from the load pipeline, see Hinton col 7 lines 7-32 and the example of Hinton Fig. 4 and corresponding description), and
the arithmetic pipeline executes the arithmetic instruction in any cycle except for the specific cycle (since the reservation station will dispatch the arithmetic instruction for execution when the required resources are available (in a different cycle that the cycle that the arithmetic pipeline is inhibited), see Hinton col 8 lines 28-38, any cycle that the arithmetic pipeline executes the arithmetic instruction in the combination is a cycle that is not the cycle that the arithmetic pipeline is inhibited issuance of the instruction).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380, Hinton US 5,555,432, and Slavenburg US 6,044,451 (cited in 892 dated 09/08/2025).
Regarding claim 4, Chan in view of Huck and Hinton teaches:
4. The processor as claimed in claim 2,
Chan in view of Huck and Hinton does not teach:
wherein the arithmetic pipeline executes a dummy arithmetic operation in response to a receiving no arithmetic instruction from the instruction issuer that inhibits the issuance of the arithmetic instruction.
However, Slavenburg teaches generating a NOP for any unit that does not receive and opcode, see col 6 lines 41-46.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the arithmetic pipeline of Chan in view of Huck and Hinton to execute a NOP/dummy arithmetic operation when the arithmetic pipeline is inhibited of the issuance of an instruction (from the instruction issuer) as taught by Slavenburg. One of ordinary skill in the art would have been motivated to make this modification because executing a NOP is a known technique on the known device of a processor for controlling a pipeline to do nothing and would yield the predictable result of the pipeline doing nothing when no instruction is received, which would simplify control of the pipeline (relative to controlling the pipeline to do something else when no instruction is received).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Chan US 6,163,837 in view of Huck US 6,408,380 and Sidman US 5,680,641.
Regarding claim 5, Chan in view of Huck teaches:
5. The processor as claimed in claim 1,
Chan in view of Huck does not teach:
wherein the load pipeline outputs, to the selector, data selection information for causing the selector to select the second data, in a cycle in which the second data is output to the selector.
However, Sidman teaches a load/store control logic that outputs selection information to a multiplexer that connects an ALU and data bus to a register bank port (which is analogous to the multiplexer 862 of Chan), see col 5 lines 33-36 and lines 43-50.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the load pipeline of Chan in view of Huck to include the load/store control logic of Sidman such that the load pipeline of the combination would output data selection information that causes the multiplexer to select the second data when the second data is output to the multiplexer. One of ordinary skill in the art would have been motivated to make this modification to efficiently control the multiplexer from the load pipeline to select data when it is output.
Regarding claim 6, Chan in view of Huck and Sidman teaches:
6. The processor as claimed in claim 5, wherein the load pipeline generates the data selection information based on information indicating execution of the first load instruction transmitted within the load pipeline (Sidman col 5 lines 43-50 indicates that the load/store control logic generates the selection information using information from the instruction decode and logic control block, in the combination, the load/store control logic of the load pipeline will generate the data selection information (to select the second data loaded by the load pair instruction) using information indicating execution of the load pair instruction transmitted within the pipeline from the decoder).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/KASIM ALLI/Examiner, Art Unit 2183
/JYOTI MEHTA/Supervisory Patent Examiner, Art Unit 2183
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