DETAILED ACTION
Claims 1-20 are pending. Claim 1, 8, and 15 are in independent form.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
With respect to the 101 rejections, the examiner respectfully disagrees that they have been overcome. The analyzer circuitry being coupled to a memory bank does not recite anything beyond generic general purpose computing arrangement. The additional step of “adjusting operation of the at least one memory bank . . .,” this additional element is so broad that it may be interpreted as merely writing data to a memory. It is, therefore, directed to electronic recordkeeping / storing and retrieving information in memory, which the courts have recognized as well‐understood, routine, and conventional.
The examiner respectfully disagrees with Applicant’s arguments regarding the prior art teaching of the independent claims. Applicant appears to read the claims narrowly as requiring some formal classification or diagnosis, for example. But limitations narrowing the invention to that interpretation do not appear in the claims. The claims are written broadly enough to encompass the teachings of Healy.
The examiner also respectfully disagrees with the arguments regarding claim 12 and the motivation to combine. Applicant essentially argues that Crosland does not have anything to do with attack detection and security while Heal does and so the motivation is not present. Healy is not solely directed to detecting a cryogenic attack. As can be seen in paragraphs 0020, 0021, 0031, 0043, and elsewhere, Healy is directed to detecting failures in DRAM in addition to attacks. This argument is not persuasive.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-6, 8-11, 13, 15-16, and 18-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1
Claims 1-6 recite a method. Thus, these claims are directed to a method, which is one of the statutory categories of invention. Claims 8-11 and 13 recite a processing system comprising a processor connected to a memory unit. Thus, these claims are directed a system, which is one of the statutory categories of invention. Claims 15-16 and 18-20 recite a method. Thus, these claims are directed to a method, which is one of the statutory categories of invention.
Next, the claims are evaluated to determine whether the claims recite a judicial exception.
Regarding claim 1:
Step 2A Prong 1: Abstract Idea
Claim 1 recites:
determining a fault mode for at least one memory bank based on one or more error correction code (ECC) errors identified in an error log associated with at least one memory bank; and (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding pattern matching. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III).)
generating a recommended management solution for the at least one memory bank in response to the fault mode. (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding pattern matching. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III).)
Step 2A Prong 2: Additional Elements
Claim 1 additionally recites,
by a fault analyzer circuitry operably coupled to at least one memory bank (This limitation is a step that merely performs the above step on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).)
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.04(d), 2106.05(g).
Step 2B: Significantly More
Claim 1 additionally recites,
by a fault analyzer circuitry operably coupled to at least one memory bank (This limitation is a step that merely performs the above step on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).)
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to general purpose computer components to perform limitations which amounts to no more than mere instructions to apply the exception using a generic computer component.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.05(g). Furthermore, the additional element is so broad that it may be interpreted as merely writing data to a memory (such as a log). It is, therefore, directed to electronic recordkeeping / storing and retrieving information in memory, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).
Regarding Claim 2, representative claim for claim 9:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 2 additionally recites,
wherein the recommended management solution is at least one of logging the one or more ECC errors (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)), retiring a memory page (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)), and recording a return merchandise authorization (This limitation is a step that merely transmits data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 2, representative claim for claim 9, additionally recites,
wherein the recommended management solution is at least one of logging the one or more ECC errors (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)), retiring a memory page (This limitation is a step that is merely and end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)), and recording a return merchandise authorization (This limitation is a step that merely transmits data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to receiving or transmitting data and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 3:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 3 additionally recites,
testing at least one cell of the memory bank to determine an ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than merely data gathering and an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 3 additionally recites,
testing at least one cell of the memory bank to determine an ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than merely an end step or application of the concepts in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 4:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 4 additionally recites,
logging the ECC error (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)); and
clearing the at least one memory bank in response to identifying the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 4 additionally recites,
logging the ECC error (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)); and
clearing the at least one memory bank in response to identifying the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 5:
Step 2A Prong 1: Abstract Idea
predicting a failure rate of the at least one memory bank based on the fault mode, wherein the failure rate is indicated by a predetermined set of data based on occurrence of the fault mode (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation and can be assisted by the use of pen and paper. Furthermore, the prediction is based solely on variables and data that is not recited as being gathered in this step. It is merely, a prediction based on analysis of data. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III)).
Step 2A Prong 2: Additional Elements
There are no additional elements in this claim.
Step 2B: Significantly More
There are no additional elements in this claim.
Regarding Claim 6:
Step 2A Prong 1: Abstract Idea
predicting the failure rate comprises predicting the failure rate based on a specified set of failure rates for memory banks (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation and can be assisted by the use of pen and paper. Furthermore, the prediction is based solely on variables and data that is not recited as being gathered in this step. It is merely, a prediction based on analysis of data. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III)).
Step 2A Prong 2: Additional Elements
There are no additional elements in this claim.
Step 2B: Significantly More
There are no additional elements in this claim.
Regarding Claim 8:
Step 2A Prong 1: Abstract Idea
Claim 8 recites:
identify one or more error correction code (ECC) errors based on error logs to determine a fault mode of at least one memory bank (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding pattern matching. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III).)
Step 2A Prong 2: Additional Elements
Claim 8 additionally recites,
a processor connected to a memory unit and configured to (This limitation is a step that merely performs the above step on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).)
store a recommended management solution for the at least one memory bank based on the fault mode (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.04(d), 2106.05(g).
Step 2B: Significantly More
Claim 8 additionally recites,
a processor connected to a memory unit and configured to (This limitation is a step that merely performs the above step on a computer in its ordinary capacity for tasks or merely adding a general-purpose computer or computer components after the fact to an abstract idea does not integrate a judicial exception into a practical application or provide significantly more. See MPEP 2106.05(f)(2).)
store a recommended management solution for the at least one memory bank based on the fault mode (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)).
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to general purpose computer components to perform limitations which amounts to no more than mere instructions to apply the exception using a generic computer component.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.05(g). Furthermore, the additional element is so broad that it may be interpreted as merely writing data to a memory (such as a log). It is, therefore, directed to electronic recordkeeping / storing and retrieving information in memory, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).
Regarding Claim 10:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 10 additionally recites,
test at least one cell of the memory bank to determine the fault mode to identify the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 10 additionally recites,
test at least one cell of the memory bank to determine the fault mode to identify the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 11:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 11 additionally recites,
log the ECC error (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)); and
clear the at least one memory bank in response to identifying the at least one memory bank has the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 11 additionally recites,
log the ECC error (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3)); and
clear the at least one memory bank in response to identifying the at least one memory bank has the ECC error (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 13:
Step 2A Prong 1: Abstract Idea
predict a failure rate of the memory unit based on the fault mode. (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation and can be assisted by the use of pen and paper. Furthermore, the prediction is based solely on variables and data that is not recited as being gathered in this step. It is merely, a prediction based on analysis of data. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III)).
Step 2A Prong 2: Additional Elements
There are no additional elements in this claim.
Step 2B: Significantly More
There are no additional elements in this claim.
Regarding claim 15:
Step 2A Prong 1: Abstract Idea
Claim 15 recites:
determine a fault mode of the at least one memory bank; (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation regarding pattern matching. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III).)
Step 2A Prong 2: Additional Elements
Claim 15 additionally recites,
testing at least one memory bank of a dynamic random-access memory (DRAM) identified in error logs (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
storing a recommended management solution for the at least one memory bank in response to the fault mode (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step/apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.04(d), 2106.05(g).
Step 2B: Significantly More
Claim 15 additionally recites,
testing at least one memory bank of a dynamic random-access memory (DRAM) identified in error logs (This limitation is a step that is merely an end step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
storing a recommended management solution for the at least one memory bank in response to the fault mode (This limitation is a step that merely transmits/stores data. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than mere data gathering and an end step/apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to general purpose computer components to perform limitations which amounts to no more than mere instructions to apply the exception using a generic computer component.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
The limitation “adjusting operation of the at least one memory bank . . .” is an additional element that amounts to adding insignificant extra-solution activity to the judicial exception. See MPEP §§ 2106.05(g). Furthermore, the additional element is so broad that it may be interpreted as merely writing data to a memory (such as a log). It is, therefore, directed to electronic recordkeeping / storing and retrieving information in memory, which the courts have recognized as well‐understood, routine, and conventional when they are claimed in a generic manner. See MPEP § 2106.05(d)(II).
Regarding Claim 16:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 16 additionally recites,
performing at least one of a read operation and a write operation for each row of the memory bank (This limitation is a step that is merely an apply it step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 16 additionally recites,
performing at least one of a read operation and a write operation for each row of the memory bank (This limitation is a step that is merely an apply it step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 18:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 18 additionally recites,
prior to retrieving the error logs from the DRAM, resetting a processing unit associated with the DRAM (This limitation is a step that is merely an apply it step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 18 additionally recites,
prior to retrieving the error logs from the DRAM, resetting a processing unit associated with the DRAM (This limitation is a step that is merely an apply it step insignificant application. Therefore, this step is an insignificant application, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3))
The combination of these additional elements are no more than an apply it step in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 19:
Step 2A Prong 1: Abstract Idea
The abstract idea is inherited from the respective parent claims.
Step 2A Prong 2: Additional Elements
Claim 19 additionally recites,
wherein the management solution is based on a number uncorrectable errors at the memory bank (This limitation is a step that merely further defines the data that is transmitted/stored. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3));
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Step 2B: Significantly More
Claim 19 additionally recites,
wherein the management solution is based on a number uncorrectable errors at the memory bank (This limitation is a step that merely further defines the data that is transmitted/stored. Therefore, this step is a mere data gathering, extra solution activity that is understood to be merely nominal. See MPEP 2106.05(g)(3));
The combination of these additional elements are no more than mere data gathering in conjunction with the abstract idea in order to provide data for the mental process and mathematical calculation to be applied to. Therefore, this does not meaningfully limit the claim, see MPEP 2106.05(g)(3).
As discussed in Step 2A, Prong Two above, the extra solution activity defined are recited at a high level of generality. These elements amount to an end step/apply it step and are well-understood, routine, conventional activity. See MPEP 2106.05(d) subsection II.
Accordingly, even in combination, these additional elements do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(d) and 2106.05(f)(2). The claim does not contain significantly more than the judicial exception.
Regarding Claim 20:
Step 2A Prong 1: Abstract Idea
predicting a failure rate of DRAM based on the fault mode. (This limitation is a step that covers performance of this limitation in the mind in the form of making an observation and can be assisted by the use of pen and paper. Furthermore, the prediction is based solely on variables and data that is not recited as being gathered in this step. It is merely, a prediction based on analysis of data. Therefore, this limitation recites a mental process. See MPEP 2106.04(a)(2)(III)).
Step 2A Prong 2: Additional Elements
There are no additional elements in this claim.
Step 2B: Significantly More
There are no additional elements in this claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-11, 13-15, and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Publication No. 2016/0239663 to Healy et al. (“Healy”).
Regarding claim 1, Healy discloses:
A method, comprising:
determining, by a fault analyzer circuitry operably coupled to at least one memory bank, a fault mode for at least one memory bank based on one or more error correction code (ECC) errors identified in an error log associated with at least one memory bank (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; Paragraph [0026] “The error count is a running tally of the number of errors discovered by the ECC controller 108”; wherein the error log is the location the counts are stored in which in this case is the error logging unit, storing any information regarding behavior can be equated to a log; additionally, the fault mode can be interpreted as the tally of errors found in particular memory banks which would indicate a fault occurring, the process of detecting these errors/faults would be equated to the detection step and therefore the ECC controller is equated to the fault analyzer circuit);
generating a recommended management solution for the at least one memory bank in response to the fault mode (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; Paragraph [0041], “the memory controller may compare the number of new errors in a particular register bank to a bank-specific threshold. In other embodiments, the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; and Paragraph [0042], “When the memory controller determines that there is a significant number of new errors, the memory controller may schedule a repair action per operation 310. In some embodiments, the memory controller may immediately perform the repair action after determining that there is a significant number of new errors and available repair resources”; and wherein the recommended management solution for the memory bank errors could be scrubbing specific memory or removing specific memory from use; wherein the management solution can be based on a number of new errors at a particular address or register bank and therefore can be interpreted as at least one memory bank; Examiner also notes that a solution for at least one memory bank could imply the entire DRAM as well interpreted broadly); and
adjusting operation of the at least one memory bank based on the recommended management solution (see paragraphs 0022 and 0042, disclosing a repair action such as a scrub or sparing or excluding memory locations; the examiner interprets that scheduled repairs are executed).
Regarding claim 2, Healy discloses all of the elements of claim 1 and further discloses:
wherein the recommended management solution is at least one of logging the one or more ECC errors, retiring a memory page (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; wherein the recommended management solution for the memory bank errors could be removing specific memory from use), and recording a return merchandise authorization.
Regarding claim 3, Healy discloses all of the elements of claim 1 and further discloses:
wherein determining the fault mode further comprises:
testing at least one cell of the memory bank to determine an ECC error (Healy: Paragraph [0036], “As part of, or following, a read, write, or refresh operation of a word at a memory address, the ECC controller may check the word for errors at operation 204. The ECC controller may check the word for errors using an existing error-correcting code or algorithm, such as a Hamming Code or a Reed-Solomon code”, wherein the checking of the word can be interpreted as testing the specific memory location for an error).
Regarding claim 4, Healy discloses all of the elements of claim 3 and further discloses:
further comprising:
logging the ECC error (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; wherein the flag is set for an uncorrectable error is detected); and
clearing the at least one memory bank in response to identifying the ECC error (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; wherein the recommended management solution for the memory bank ecc could be scrubbing specific memory which the Examiner interprets as clearing the at least one memory bank).
Regarding claim 5, Healy discloses all of the elements of claim 1 and further discloses:
wherein generating the recommended management solution comprises:
predicting a failure rate of the at least one memory bank based on the fault mode, wherein the failure rate is indicated by a predetermined set of data based on occurrence of the fault mode (Healy: Paragraph [0021], “An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM”; wherein “predetermined set of data based on occurrence of the fault mode” can be interpreted as a threshold of error count; and then a failure rate would be interpreted as the maximum number of error the memory can tolerate and in which the respective action as seen in claim 1 can be taken).
Regarding claim 6, Healy discloses all of the elements of claim 5 and further discloses:
wherein predicting the failure rate comprises predicting the failure rate based on a specified set of failure rates for memory banks (Healy: Paragraph [0046], “The decision parameters 411 are parameters utilized by the failure detection unit 410 to determine error indicators, such as the error rate and error acceleration of the DRAM, and thresholds to compare with the error indicators to predict failure in the DRAM. For example, the decision parameters may include thresholds 411A, 411B, and 411C, as well as time periods 411D and 411E. The first threshold 411A may be the maximum tolerable error count; the second threshold 411B may be the maximum tolerable error rate; and, the third threshold 411C may be the maximum tolerable error acceleration. The first time period 411D may be used in calculating an error rate, while the second time period 411E may be used to calculate an error acceleration”; Paragraph [0028], “the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106”; wherein the determining error indicators such as error rate based on a specified maximum tolerable error rate which can be interpreted as a specified set (can be a single value) for the memory banks).
Regarding claim 7, Healy discloses all of the elements of claim 1 and further discloses:
wherein determining the fault mode comprises:
retrieving an address from the error log (Healy: Paragraph [0044], “When the ECC controller 406 detects an error, it stores memory information in the error logging unit 408”; Paragraph [0041], “the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; Paragraph [0045], “Memory information may include the error address 408A, which is the memory address of a cell in which the ECC controller 406 detected an error, and an error count 408B, which is a running tally of the number of errors found by the ECC controller 406 since the error logging unit 408 was last reset”; wherein the retrieving an address consists of the memory information that was stored by the logging unit and is retrieved in order to compare to thresholds; additionally the address can be tied to a row or column); and
decoding the address into at least one of channel, bank, and row associated with the at least one memory bank (Healy: Paragraph [0044], “When the ECC controller 406 detects an error, it stores memory information in the error logging unit 408”; Paragraph [0041], “the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; Paragraph [0045], “Memory information may include the error address 408A, which is the memory address of a cell in which the ECC controller 406 detected an error, and an error count 408B, which is a running tally of the number of errors found by the ECC controller 406 since the error logging unit 408 was last reset”; wherein the retrieving an address consists of the memory information that was stored by the logging unit and is retrieved the errors is compared therefore “decoding” broadly can be interpreted as including understanding that its part of a row or column).
Regarding claim 8, Healy discloses:
A processing system, comprising:
a processor connected to a memory unit (Healy: Paragraph [0023], “In some embodiments, the major components of the computer system 101 may include one or more CPUs 102, a memory controller 105, a memory 104, a terminal interface 113, a storage interface 114, an input/output (I/O) device interface 116, and a network interface 118, all of which may be communicatively coupled, directly or indirectly, for inter-component communication via a memory bus 103, an I/O bus 112, and an I/O bus interface unit 111”) and configured to:
identify one or more error correction code (ECC) errors based on error logs to determine a fault mode of at least one memory bank (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; Paragraph [0026] “The error count is a running tally of the number of errors discovered by the ECC controller 108”; wherein the error log is the location the counts are stored in which in this case is the error logging unit, storing any information regarding behavior can be equated to a log; additionally, the fault mode can be interpreted as the tally of errors identified in particular memory banks which would indicate a fault occurring, the process of detecting these errors/faults would be equated to the identification step); and
store a recommended management solution for the at least one memory bank based on the fault mode (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; Paragraph [0041], “the memory controller may compare the number of new errors in a particular register bank to a bank-specific threshold. In other embodiments, the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; and Paragraph [0042], “When the memory controller determines that there is a significant number of new errors, the memory controller may schedule a repair action per operation 310. In some embodiments, the memory controller may immediately perform the repair action after determining that there is a significant number of new errors and available repair resources”; and wherein the recommended management solution for the memory bank errors could be scrubbing specific memory or removing specific memory from use; wherein the management solution can be based on a number of new errors at a particular address or register bank and therefore can be interpreted as at least one memory bank; Examiner also notes that a solution for at least one memory bank could imply the entire DRAM as well interpreted broadly; and finally storing a solution could be interpreted as scheduling the repair action or even broader it could be interpreted as being in memory which the execution of a function such as a memory scrub would have to be stored in memory in order to be executed); and
adjusting operation of the at least one memory bank based on the recommended management solution (see paragraphs 0022 and 0042, disclosing a repair action such as a scrub or sparing or excluding memory locations; the examiner interprets that scheduled repairs are executed).
Regarding claim 9, Healy discloses all of the elements of claim 8 and further discloses:
wherein the recommended management solution is at least one of logging the one or more ECC errors, retiring a memory page (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; wherein the recommended management solution for the memory bank errors could be removing specific memory from use), and recording a return merchandise authorization.
Regarding claim 10, Healy discloses all of the elements of claim 8 and further discloses:
wherein the processor is further configured to:
test at least one cell of the memory bank to determine the fault mode to identify the ECC error (Healy: Paragraph [0036], “As part of, or following, a read, write, or refresh operation of a word at a memory address, the ECC controller may check the word for errors at operation 204. The ECC controller may check the word for errors using an existing error-correcting code or algorithm, such as a Hamming Code or a Reed-Solomon code”, wherein the checking of the word can be interpreted as testing the specific memory location for an error).
Regarding claim 11, Healy discloses all of the elements of claim 10 and further discloses:
wherein the processor is further configured to:
log the ECC error (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; wherein the flag is set for an uncorrectable error is detected); and
clear the at least one memory bank in response to identifying the at least one memory bank has the ECC error (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; wherein the recommended management solution for the memory bank ecc could be scrubbing specific memory which the Examiner interprets as clearing the at least one memory bank).
Regarding claim 13, Healy discloses all of the elements of claim 8 and further discloses:
wherein the processor is further configured to:
predict a failure rate of the memory unit based on the fault mode (Healy: Paragraph [0021], “An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM”; wherein “predetermined set of data based on occurrence of the fault mode” can be interpreted as a threshold of error count; and then a failure rate would be interpreted as the maximum number of error the memory can tolerate and in which the respective action as seen in claim 8 can be taken).
Regarding claim 14, Healy discloses all of the elements of claim 8 and further discloses:
wherein the processor is further configured to:
retrieve an address from the error logs (Healy: Paragraph [0044], “When the ECC controller 406 detects an error, it stores memory information in the error logging unit 408”; Paragraph [0041], “the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; Paragraph [0045], “Memory information may include the error address 408A, which is the memory address of a cell in which the ECC controller 406 detected an error, and an error count 408B, which is a running tally of the number of errors found by the ECC controller 406 since the error logging unit 408 was last reset”; wherein the retrieving an address consists of the memory information that was stored by the logging unit and is retrieved in order to compare to thresholds; additionally the address can be tied to a row or column); and
decode the address into at least one of channel, bank, and row (Healy: Paragraph [0044], “When the ECC controller 406 detects an error, it stores memory information in the error logging unit 408”; Paragraph [0041], “the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; Paragraph [0045], “Memory information may include the error address 408A, which is the memory address of a cell in which the ECC controller 406 detected an error, and an error count 408B, which is a running tally of the number of errors found by the ECC controller 406 since the error logging unit 408 was last reset”; wherein the retrieving an address consists of the memory information that was stored by the logging unit and is retrieved the errors is compared therefore “decoding” broadly can be interpreted as understanding that its part of a row or column).
Regarding claim 15, Healy discloses:
A method, comprising:
testing at least one memory bank of a dynamic random-access memory (DRAM) identified in error logs to determine a fault mode of the at least one memory bank (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; Paragraph [0026] “The error count is a running tally of the number of errors discovered by the ECC controller 108”; Paragraph [0046], “The decision parameters 411 are parameters utilized by the failure detection unit 410 to determine error indicators, such as the error rate and error acceleration of the DRAM, and thresholds to compare with the error indicators to predict failure in the DRAM. For example, the decision parameters may include thresholds 411A, 411B, and 411C, as well as time periods 411D and 411E. The first threshold 411A may be the maximum tolerable error count; the second threshold 411B may be the maximum tolerable error rate”; wherein the error log is the location the counts are stored in which in this case is the error logging unit, storing any information regarding behavior can be equated to a log; additionally, the fault mode can be interpreted as the tally of errors identified in particular memory banks which would indicate a fault occurring, the process of detecting these errors/faults and comparing them to the thresholds would broadly be interpreted as testing a memory bank); and
storing a recommended management solution for the at least one memory bank in response to the fault mode (Healy: Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; Paragraph [0041], “the memory controller may compare the number of new errors in a particular register bank to a bank-specific threshold. In other embodiments, the memory controller may compare the number of new errors at a particular address (including at a particular row or column) to appropriate address thresholds”; and Paragraph [0042], “When the memory controller determines that there is a significant number of new errors, the memory controller may schedule a repair action per operation 310. In some embodiments, the memory controller may immediately perform the repair action after determining that there is a significant number of new errors and available repair resources”; and wherein the recommended management solution for the memory bank errors could be scrubbing specific memory or removing specific memory from use; wherein the management solution can be based on a number of new errors at a particular address or register bank and therefore can be interpreted as at least one memory bank; Examiner also notes that a solution for at least one memory bank could imply the entire DRAM as well interpreted broadly; and finally storing a solution could be interpreted as scheduling the repair action or even broader it could be interpreted as being in memory which the execution of a function such as a memory scrub would have to be stored in memory in order to be executed); and
adjusting operation of the at least one memory bank based on the recommended management solution (see paragraphs 0022 and 0042, disclosing a repair action such as a scrub or sparing or excluding memory locations; the examiner interprets that scheduled repairs are executed).
Regarding claim 19, Healy discloses all of the elements of claim 15 and further discloses:
wherein the recommended management solution is based on a number uncorrectable errors at the memory bank (Healy: Paragraph [0028], “In some embodiments, the error logging unit 110 may store bank-specific error counts that tally the number of errors found in particular memory banks within the DRAM 106. Additionally, the error logging unit 110 may store an uncorrectable error flag that alerts the memory controller 105 whenever an uncorrectable error is found in the DRAM 106”; Paragraph [0022], “A “repair action” includes any action performed on the DRAM to repair or prevent soft errors. For example, in some embodiments the repair action may be running a memory scrub operation. In other embodiments, particularly when a memory cell or row has had numerous errors, the repair action may be to spare or mark the hardware such that the computer system will no longer store information in the affected memory cell or row, or ultimately to replace the DRAM”; wherein uncorrectable errors are logged that will trigger a solution).
Regarding claim 20, Healy discloses all of the elements of claim 15 and further discloses:
further comprising:
predicting a failure rate of DRAM based on the fault mode (Healy: Paragraph [0021], “An “error indicator” is any information about the DRAM that may be compared to established thresholds to determine whether failure of the DRAM, or a cryogenic attack on the DRAM, is occurring. For example, an error indicator may be the error count, the error rate, the error acceleration, or the DRAM temperature. An “associated threshold” is a threshold that corresponds to a given error indicator. For example, the associated threshold of an error count may be the maximum number of errors the DRAM can tolerate, while the associated threshold of an error rate may be the maximum tolerable rate of new errors in the DRAM”; wherein “predetermined set of data based on occurrence of the fault mode” can be interpreted as a threshold of error count; and then a failure rate would be interpreted as the maximum number of error the memory can tolerate and in which the respective action as seen in claim 15 can be taken).
Claim Rejections - 35 USC § 103
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Healy in view of U.S. Patent No. 8,607,105 to Crosland et al. ("Crosland").
Regarding claim 12, Healy teaches all of the elements of claim 10. However, Healy does not appear to teach:
wherein the processor is further configured to:
disable system interrupt handlers in response to testing the at least one memory bank.
However, in the same field of endeavor, Crosland teaches:
wherein the processor is further configured to:
disable system interrupt handlers in response to testing the at least one memory bank (Crosland: Col. 1, lines 22-32, “Generally speaking, in a software system, software interrupts have to be disabled when memory modules in the system are being tested. For example, in a typical software memory test, contents of the memory region to be tested need to be copied and saved before the memory region is tested. Generally, software interrupts are disabled for the whole duration of the test which includes, making a copy of the memory region to be tested, testing the memory region, and restoring the contents of the memory from the safe copy. Interrupts are only re-enabled after the test is completed and the contents of the memory are restored”; wherein software interrupts must be disabled during memory region testing; although the art teaches the elements at hand, Crosland also teaches alternatives to this solution, however, the Examiner recommends Applicant to consider MPEP 2131.05 where art that teaches away can still disclose the elements that are taught away from).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Healy by disabling system interrupt handlers when testing memory regions, as taught by Crosland. One of ordinary skill in the art would have been motivated to use the methods of Crosland because Crosland describes the elements as well known or that generally software systems use system interrupts in order to test. (Crosland: Col. 1, lines 22-32).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Healy in view of U.S. Publication No. 2024/0290414 to Kim et al. ("Kim").
Regarding claim 16, Healy teaches all of the elements of claim 15. However, Healy does not appear to teach:
wherein testing the at least one memory bank comprises:
performing at least one of a read operation and a write operation for each row of the memory bank.
However, in the same field of endeavor, Kim teaches:
wherein testing the at least one memory bank comprises:
performing at least one of a read operation and a write operation for each row of the memory bank (Kim: Paragraph [0024], “The test program may include a test algorithm or pattern for performing the test operation. For example, the test host 112 may store particular data in a storage area of the DUT, i.e., a memory cell array 122 of the memory device 120, read the data, and then determine a pass or fail status of the test operation depending on whether the read data is identical to the particular data. The test host 112 may measure a change in voltage, current, and/or frequency under various driving conditions for the memory device 120 to test whether the range of the change is acceptable. The test host 112 may test the operation of a particular circuit of the memory device 120, and in particular may test the repair circuit 124 to detect faults in the repair circuit 124”; Paragraph [0108], “The test host may individually test each address bit by sequentially providing addresses of memory cell rows of each of the memory banks as the test addresses. The test host may test the address bits in parallel by providing the same test addresses as the first addresses. The test host may perform a scan test on a path where the repair enable signals are generated by providing addresses configured to cause the repair enable signals to toggle as the test addresses. The test host may determine pass or fail of the path where the repair enable signals are generated by providing a hit signal pattern that causes the repair enable signals to toggle to the lines carrying the hit signals”; wherein the test host tests each row of each memory bank and test operation is defined as storing data then reading the data to determine pass or fail).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Healy by testing each row of a memory banks, as taught by Kim. One of ordinary skill in the art would have been motivated to use the methods of Kim because it would improve reliability of memory devices by detecting faults. (Kim: Paragraph [0002]).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Healy in view of Kim in view of Crosland.
Regarding claim 17, the Healy/Kim combination teaches all of the elements of claim 16. However, the combination does not appear to teach:
further comprising:
disabling system interrupt handlers in response to performing at least one of the read operation and the write operation.
However, in the same field of endeavor, Crosland teaches:
further comprising:
disabling system interrupt handlers in response to performing at least one of the read operation and the write operation (Crosland: Col. 1, lines 22-32, “Generally speaking, in a software system, software interrupts have to be disabled when memory modules in the system are being tested. For example, in a typical software memory test, contents of the memory region to be tested need to be copied and saved before the memory region is tested. Generally, software interrupts are disabled for the whole duration of the test which includes, making a copy of the memory region to be tested, testing the memory region, and restoring the contents of the memory from the safe copy. Interrupts are only re-enabled after the test is completed and the contents of the memory are restored”; wherein software interrupts must be disabled during memory region testing).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by the Healy/Kim combination by disabling system interrupt handlers when testing memory regions, as taught by Crosland. One of ordinary skill in the art would have been motivated to use the methods of Crosland because Crosland describes the elements as well known or that generally software systems use system interrupts in order to test. (Crosland: Col. 1, lines 22-32).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Healy in view of U.S. Publication No. 2010/0202237 to Moshayedi et al. ("Moshayedi").
Regarding claim 18, Healy teaches all of the elements of claim 15. However, Healy does not appear to teach:
further comprising:
prior to retrieving the error logs from the DRAM, resetting a processing unit associated with the DRAM.
However, in the same field of endeavor, Moshayedi teaches:
further comprising:
prior to retrieving the error logs from the DRAM, resetting a processing unit associated with the DRAM (Moshayedi: Paragraph [0055], “During production test, controller 110 can be held in reset to allow DRAM 120 and SD/MMC+ flash 130 to be tested. Thus, FET switches 163 and 164 on the DDR interface are held in the proper state when controller 110 is held in reset”; wherein controller 110 is associated with the DRAM; although not directly associated, the claim as worded does not need direct correlation. Therefore, the controller being held in reset prior to the testing reads on prior to retrieving the error logs).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method taught by Healy by resetting a processing unit prior to the testing, as taught by Moshayedi. One of ordinary skill in the art would have been motivated to use the methods of Moshayedi because it would improve restore time as well a performance of read and write operations. (Moshayedi: Paragraphs [0029] and [0003]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US 20150135026 A1.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JASON B BRYAN/Primary Examiner, Art Unit 2114
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