DETAILED ACTION
Re Application No. 18756181, this action responds to the RCE dated 02/04/2026.
At this point, claim 1, 9, 11, and 16-17 have been amended. Claims 5, 15, and 18-19 have been cancelled. Claims 1-4, 6-14, 16-17, and 20 are pending.
The present application is being examined under the pre-AIA first to invent provisions.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/04/2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Examiner notes Applicant’s amended claims dated 02/04/2026. In view of the amended claims, claims 1-17 and 19-20 are still rejected under 35 USC § 112, second paragraph, for the following reasons:
Claims 1, 11, and 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention, for the following reasons:
Claim 1 only, language “performing a cache look-up routine in the one or more caches and the plurality of memory devices to select a first memory device from the one or more caches coupled to the interface device” (claim 1, lines 8-10). This limitation is indefinite, because it is unclear whether this limitation contains a typographical error (i.e. it should read “the one or more caches of the plurality of memory devices”), or if it actually means that the cache look-up is performed both on the one or more caches, as well as the plurality of memory devices. It is noted that claims 11 and 17 omit the limitation “and the plurality of memory devices”. If it is the latter, then it is unclear how performing the cache lookup on the plurality of memory devices is distinct in any way from performing the lookup on the one or more caches, as the plurality of memory devices already include the one or more caches; moreover, the other enumerated devices in the plurality of memory devices are described as DRAM DIMMs, not caches, so it is not clear how these other DRAM DIMMs would function in a cache lookup operation. In fact, the result of this cache look-up routine is specified as selecting a memory device from the one or more caches, so it does not even appear that the cache lookup could be serviced from the DRAM DIMMs, as they are not the one or more caches;
Claims 1, 11, and 17, language “retrieving a first part of the information that is stored in the first memory device as first information when the information is stored in the one or more caches; retrieving second portion of the information from the persistent memory or the plurality of DRAM DIMMs as second information due to less than all of the information being stored in the one or more caches” (e.g. claim 1, lines 11-15). This limitation is indefinite, for 3 reasons. First, these limitations use inconsistent language, referring to “a first part of the information” but “second portion of the information” (note also the missing article ‘a’); if these are intended to refer to different parts/portions of the same information, Applicant is respectfully requested to utilize consistent language. Second, it is not clear whether these two limitations were intended to be written as mutually exclusive conditions, or as complimentary and potentially overlapping conditions. For example, the second condition occurs “due to less than all of the information being stored in the one or more caches”; if these conditions are meant to be mutually exclusive, then this would imply that the first condition was intended to read “when all the information is stored in the one or more caches”. However, it could also be read in a non-mutually exclusive manner, i.e. when the first part of the information is on the one or more caches, that first portion is retrieved from the cache; when there is a second part of the information that is not stored on the cache (less than all the information being stored on the cache), then the second part is retrieved from the DRAM DIMMs. In other words, it is unclear whether this limitation is intended to mean 1) “retrieve the information from the cache if it is all in the caches; otherwise, retrieve the information from the DRAM DIMMs”, or 2) “retrieve any portion of the information from the cache if it is in the cache, and retrieve what is not cached from the DRAM DIMMS”. Third, it is unclear how these conditional limitations would function for information that is in the one or more caches, but the caches storing the information are not the selected first memory device. The cache lookup routine selects a first memory device of the one or more caches; accordingly, this may involve selecting one cache device from a plurality of devices. Moreover, the cache lookup is not explicitly tied to the information; accordingly, there is no guarantee that the selected first memory device contains all of, or indeed any of, the information. Accordingly, when the condition “the information is stored in the one or more caches” is met, but the information is stored in caches other than the first memory device, it is unclear how the first part of the information can be retrieved from the first memory device.
Claims 2-4, 6-10, 12-14, 16, and 20 are rejected as dependent upon one of claims 1, 11, and 17 above, respectively.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 11, and 16-17 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken et al (US 2003/02128665 A1) in view of Brewer et al (US 2010/0036997 A1).
Re claim 1, Hicken discloses the following:
A method, comprising: receiving a memory request for information at an interface device that is an interface between a processor, a persistent memory, and a plurality of memory devices, wherein the interface device is separate from the processor, persistent memory, and the plurality of memory devices, wherein the plurality of memory devices comprises one or more caches (Fig. 1; ¶ 21). The disk array controller contains an input/output interface (i.e. it is an interface device), and it receives a read request (memory request) from a processor of a host. Disk array controller (interface device) is separate from the host processor (processor), disk array (at least one of the disks being persistent memory), and disk array and memory together (plurality of memory devices). Additionally, the write cache (one or more caches) also interfaces with the other components through the interface device. Under this limitation, the interface device is clearly “between” the processor, as well as the persistent disks (persistent storage device), write cache (one or more caches), and memory. Furthermore, even assuming, arguendo, that the current configuration of Hicken could not be interpreted as having the interface device “between” the processor and the persistent/plurality of memory devices, it would nonetheless have been obvious to one having ordinary skill in the art to rearrange the parts such that the interface device could be considered to be “between” the processor and various memories, because these components are all connected to one another, either directly or indirectly, and thus moving the parts such that the interface device is “between” the other parts would be a mere rearrangement of parts (MPEP § 2144.04(VI)(C));
performing a cache look-up routine in the one or more caches and the plurality of memory devices to select a first memory device from the one or more caches coupled to the interface device (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). This limitation is indefinite, as noted above. Examiner interprets “one or more caches and the plurality of memory devices” as being the one or more caches of the plurality of memory devices. Regardless, Hicken discloses a storage system which includes a memory 116, as well as a write cache 126 (cache; collectively a plurality of memory devices) (Fig. 1). The disk array controller performs a traversal (looks up) of requested data in the write cache (in a cache of the plurality of memory devices). The write cache is a first memory device that is selected for this process (¶ 21-25). Furthermore, the write cache can be considered “separate” from the intput-output interface 128 (which is a component of the disk array controller); however, even assuming, arguendo, that only the entire disk array controller could qualify as the “interface device”, int would nonetheless have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to make the write cache of Hicken “separate” from the memory controller (interface device), because it would merely be making the components separable (MPEP § 2144.04(V)(C));
receiving a first part of the information that is stored in the first memory device as first information when the information is stored in the one or more caches; retrieving second part of the information from the persistent memory or the plurality of DRAM DIMMs as second information due to less than all of the information being stored in the one or more caches (Fig. 2; ¶ 21-25). This limitation is indefinite, as noted above. Examiner interprets it to mean retrieving information from the cache if it is fully in the cache, and either retrieving a cached part from the cache and a non-cached part from non-cache memory if there is a partial hit, or retrieving the entire information from non-cache memory if there is only a partial hit. If there is a full hit to the cache (when the information is stored in the cache), it is retrieved from the cache (first memory device), whereas if there is a partial hit or a miss (less than all the information is stored in the cache), then it is retrieved from the persistent memory (persistent memory or the plurality of DRAM DIMMs);
transmitting the information to the processor (¶ 24-25). The information is transferred (transmitting) to the host, and accordingly, the processor within the host.
Hicken discloses additional memory (memory 116); however, it is not specified whether this is a DRAM, let alone a plurality of DRAM DIMMs.
Brewer discloses the following:
the plurality of memory devices comprises one or more caches on separate integrated circuits (¶ 5; claim 42). The memory of the computing system (plurality of memory devices) includes one or more caches, which may be located on an integrated circuit (one or more caches on separate integrated circuits) (¶ 5). It is noted that it is not clear what the “integrated circuits” must be separate from, as no point of comparison is being given. Examiner interprets the circuit storing the one or more caches to be separate from other components of the storage system. Nevertheless, the integrated circuit that makes up the processors and cache may be separate from another IC that comprises the memory controller (claim 42).
and a plurality of dynamic random access memory (DRAM) dual in-line memory modules (DIMMs) (Fig. 4, memory 402; ¶ 62). The memory of the computing system (plurality of memory devices) includes a plurality of DRAM modules, commonly deployed as DIMMs.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory of Hicken to include a plurality of DRAM DIMMs, as in Brewer, because it would be applying a known technique to improve a similar method in the same way. Hicken discloses a computing system comprising a memory hierarchy of memory and caches. Brewer also discloses a memory hierarchy of memory and caches, which has been improved in a similar way to the claimed invention, for the memory to be implemented as a plurality of DRAM DIMMs. It would have been obvious to modify the memory of Hicken to utilize a plurality of DRAM DIMMs, as in Brewer, because it would yield the predictable improvement of increasing memory bandwidth and/or capacity to utilize multiple DRAM DIMMs.
Re claim 6, Hicken and Brewer disclose the method of claim 1, and Hicken further discloses the following:
receiving an additional memory request for additional information at the interface device from the processor (Fig. 1; ¶ 21). See claim 1 above. Furthermore, Hicken discloses subsequent requests (additional memory requests) and subsequent flushing routines (¶ 34);
performing an additional cache look-up routine in the one or more caches of the memory device to select a second memory device of the plurality of memory devices and the persistent memory (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). See claim 1 above;
receiving the additional information that is stored in the first memory device as third information when the additional information is stored in the one or more caches; retrieving the additional information from the persistent memory as fourth information if less than all of the additional information is stored in the one or more caches; and (Fig. 2; ¶ 21-25). See claim 1 above;
transmitting the additional information to the processor (¶ 24-25). See claim 1 above.
Re claim 7, Hicken and Brewer disclose the method of claim 1, and Hicken further discloses that the processor does not perform a disk input/output routing to receive the first information (¶ 24-25). The processor of the host requests the information, and then the disk array controller returns the data to the host (and processor); there is no mention of the processor performing a disk input/output routing operation.
Re claim 11, Hicken and Brewer disclose the method of claim 1, from the perspective of the memory controller (receiving from the processor); accordingly, they also disclose a method written from the perspective of the processor (sending requests to the memory controller), as in claim 11.
Re claim 16, Hicken and Brewer disclose the method of claim 1, and Hicken further discloses the following:
transmitting an additional memory request for additional information to the interface device (Fig. 1; ¶ 21). See claim 1 above. Furthermore, Hicken discloses subsequent requests (additional memory requests) and subsequent flushing routines (¶ 34);
receiving the additional information at the processor from the interface device after the interface device has: performed an additional cache look-up routine in the one or more caches to select a second memory device of the one or more caches; and (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). See claim 1 above;
retrieved a first part of the additional information that is stored in the second memory device and retrieved a second part of the additional information from the persistent memory or the plurality of DRAM DIMMs as fourth information due to less than all of the information being stored in the one or more caches (Fig. 2; ¶ 21-25). See claim 1 above.
Re claims 17, Hicken and Brewer disclose the method of claim 1 above; accordingly, they also discloses a system implementing that method, as in claim 17 (see Hicken, ¶ 5).
Claims 2-4, 12-14, and 20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Brewer, further in view of Faibish et al (US 7873619 B1).
Re claim 2, Hicken and Brewer disclose the method of claim 1; furthermore, while they disclose that memory is persistent, they do not explicitly specify what kind of persistent memory is used. Accordingly, Examiner has provided Faibish.
Faibish discloses that the persistent memory comprises a solid-state drive (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the persistent memory of Hicken (combined with Brewer) as a non-volatile SSD flash memory, as in Faibish, because Faibish suggests that using this type of memory would provide advantages such as fast access rate, high throughput, high integration density, and stability against external impact (col. 13, lines 6-12).
Re claim 3, Hicken and Brewer disclose the method of claim 1; furthermore, while they disclose that the memory is persistent, they do not explicitly specify what kind of persistent memory is used. Accordingly, Examiner has provided Faibish.
Faibish discloses that the persistent memory comprises a non-volatile memory (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hicken, Brewer, and Faibish, for the reasons noted in claim 2 above.
Re claim 4, Hicken, Brewer, and Faibish disclose the method of claim 3, and Faibish further discloses that the non-volatile memory comprises a flash memory (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hicken, Brewer, and Faibish, for the reasons noted in claim 2 above.
Re claims 12-14, Hicken, Brewer, and Faibish disclose the methods of claims 2-4 above, respectively; accordingly, they also disclose those same limitations as applied to parent claim 11, as in claims 12-14, respectively.
Re claim 20, Hicken, Brewer, and Faibish disclose the method of claim 4 above; accordingly, they also disclose a system implementing that method, as in claim 20 (see Hicken, ¶ 5).
Claims 8-9 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Brewer, further in view of Binkert et al (US 2009/0103855 A1).
Re claim 8, Hicken and Brewer disclose the method of claim 1, but do not specifically disclose a stack of memory devices.
Binkert discloses that the plurality of memory devices is arranged in a stack (¶ 42). A plurality of DRAM memory devices are stacked into a stack.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the memory devices of Hicken (combined with Brewer) as a stack, as in Binkert, because Binkert suggests that stacking memory dies provides shorter, lower-resistance interconnections, which reduces power requirements to transmit signals (¶ 31).
Re claim 9, Hicken, Brewer, and Binkert disclose the method of claim 8, and Brewer further discloses that DRAM devices are DRAM DIMMs (Fig. 4, memory 402; ¶ 62). See claim 1 above.
Binkert further discloses that the stack comprises a plurality of DRAM [devices] that uses a plurality of channels (¶ 42). The stacked memory devices are DRAM, and utilize a plurality of channels.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the memory devices of Hicken (combined with Brewer) as a DRAM stack with a plurality of channels, as in Binkert, because Binkert suggests that stacking DRAM provides shorter, lower-resistance interconnections, which reduces power requirements to transmit signals (¶ 31), while utilizing a plurality of channels increases bandwidth (¶ 42).
Claim 10 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Brewer, further in view of Allen et al (US 2009/0172345 A1).
Re claim 10, Hicken and Brewer disclose the method of claim 1, but do not specifically disclose tags or LBA tables.
Allen discloses storing cache tag values or logical block address (LBA) tables in the plurality of memory devices (¶ 4). The memory device, which can be a plurality of memory devise, may store a translation table which includes LBASs (logical block address table). The tables can be maintained in the individual memory devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory devices of Hicken (combined with Brewer) to store LBA tables in them, as in Allen, because it would be applying a known technique to a known method ready for improvement, to yield predictable results. Hicken (combined with Brewer) discloses caches used to cache from persistent memory, which is ready for the improvement of having a LBA table to manage memory translations. Allen discloses managing LBA translations using a table which can be stored in the memory devices themselves, which is applicable to the memory of Hicken. It would have been obvious to integrate the LBA tables of Allen into the memory devices of Hicken (combined with Brewer), because it would yield the predictable result of providing the memory devices with tables which can be used to locate memory using LBAs.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-4, 6-14, 16-17, and 20 filed 02/04/2026 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING 35 USC § 112, SECOND PARAGRAPH REJECTIONS
Re claims 1-4, 6-14, 16-17 and 20, Applicant argues that the amended claims are sufficient to overcome Examiner’s previous rejections under 35 USC § 112, second paragraph. In response, Applicant’s argument has been fully considered, but is not deemed persuasive. While the proposed amendments resolve some of the original issues with the claims, the new claim language introduces new indefinite subject matter, and accordingly the claims remain rejected under 35 USC § 112, second paragraph.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Re claims 1, 11, and 17, Applicant argues that Hicken does not disclose the claimed invention, for 2 reasons.
First, Applicant argues that Hicken does not disclose an interface that is “between a processor, persistent memory, and a plurality of DRAM DIMMs”. In response, Applicant’s first argument has been fully considered, but is not moot in view of new grounds for rejection. Hicken discloses an interface device (either the entire disk array controller, or the input-output interface thereof), which is “between” a processor, a memory, a cache, and a persistent storage. While Hicken discloses “memory”, it does not explicitly disclose whether it is a DRAM DIMM; accordingly, Examiner has cited Brewer, which discloses a plurality of DRAM DIMMs (Fig. 4, memory 402; ¶ 62).
Second, Applicant argues that Hicken does not disclose that the method “pulls part of a data request from the one or more caches and another part from a DRAM DIMM”. In response, Applicant’s second argument has been fully considered, but is not deemed persuasive, for 2 reasons. First, as noted above, the limitation referred to by Applicant is indefinite, as noted above; it is unclear whether this limitation refers to mutually exclusive conditions, or whether they are complimentary. Second, the current claim language does not actually require any of the information to be retrieved from the DRAM DIMMs, both because these limitations are contingent and need not actually occur (see MPEP § 2111.04(II), and also because even if the contingent limitation does occur, the data need only be retrieved “from the persistent memory or the plurality of DRAM DIMMs”; accordingly, it may simply be retrieved from the persistent memory without involving the DRAM DIMMs at all. In fact, there is no required function for the DRAM DIMMs whatsoever, other than that they exist. Accordingly, Hicken, which reads data from the cache and/or disk array (persistent storage) based on cache hit status, reads onto this claim limitation.
Re claims 2-4, 6-10, 12-14, 16, and 20, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 11, and 17 above, respectively; as this is the sole argument for allowability, Applicant is directed to Examiner’s rejections of claims 1, 11, and 17 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 02/04/2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Vemula et al (US 7596707 B1). Discloses reading requested data from DRAM DIMMs when there is a cache miss (col. 3, lines 16-36).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132