DETAILED ACTION
Re Application No. 18756181, this action responds to the amended claims dated 05/21/2026.
At this point, claim 1, 11, and 16-17 have been amended. Claims 5, 15, and 18-19 have been cancelled. Claims 1-4, 6-14, 16-17, and 20 are pending.
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Examiner notes Applicant’s amended claims dated 02/04/2026. In view of the amended claims, Examiner’s prior rejections under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 11, and 16-17 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken et al (US 2003/02128665 A1) in view of Hirao et al (US 2003/0041214 A1), further in view of Brewer et al (US 2010/0036997 A1).
Re claim 1, Hicken discloses the following:
A method, comprising: receiving a memory request for information at an interface device that is an interface between a processor, a persistent memory, and a plurality of memory devices, wherein the interface device is separate from the processor, persistent memory, and the plurality of memory devices, wherein the plurality of memory devices comprises one or more caches (Fig. 1; ¶ 21). The disk array controller contains an input/output interface (i.e. it is an interface device), and it receives a read request (memory request) from a processor of a host. Disk array controller (interface device) is separate from the host processor (processor), disk array (at least one of the disks being persistent memory), and disk array and memory together (plurality of memory devices). Additionally, the write cache (one or more caches) also interfaces with the other components through the interface device. Under this limitation, the interface device is clearly “between” the processor, as well as the persistent disks (persistent storage device), write cache (one or more caches), and memory. Furthermore, even assuming, arguendo, that the current configuration of Hicken could not be interpreted as having the interface device “between” the processor and the persistent/plurality of memory devices, it would nonetheless have been obvious to one having ordinary skill in the art to rearrange the parts such that the interface device could be considered to be “between” the processor and various memories, because these components are all connected to one another, either directly or indirectly, and thus moving the parts such that the interface device is “between” the other parts would be a mere rearrangement of parts (MPEP § 2144.04(VI)(C));
performing a cache look-up routine in the one or more caches to select a first memory device from the one or more caches coupled to the interface device (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). Hicken discloses a storage system which includes a memory 116, as well as a write cache 126 (cache; collectively a plurality of memory devices) (Fig. 1). The disk array controller performs a traversal (looks up) of requested data in the write cache (in a cache of the plurality of memory devices). The write cache is a first memory device that is selected for this process (¶ 21-25). Furthermore, the write cache can be considered “separate” from the intput-output interface 128 (which is a component of the disk array controller); however, even assuming, arguendo, that only the entire disk array controller could qualify as the “interface device”, it would nonetheless have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to make the write cache of Hicken “separate” from the memory controller (interface device), because it would merely be making the components separable (MPEP § 2144.04(V)(C));
receiving a first part of the information that is stored in the first memory device as first information stored in the one or more caches; retrieving second part of the information from [additional memory] as second information […] due to less than all of the information being stored in the one or more caches (Fig. 2; ¶ 21-25). This limitation is indefinite, as noted above. Examiner interprets it to mean retrieving information from the cache if it is fully in the cache, and either retrieving a cached part from the cache and a non-cached part from non-cache memory if there is a partial hit, or retrieving the entire information from non-cache memory if there is only a partial hit. If there is a full hit to the cache (when the information is stored in the cache), it is retrieved from the cache (first memory device), whereas if there is a partial hit or a miss (less than all the information is stored in the cache), then it is retrieved from the persistent memory (persistent memory or the plurality of DRAM DIMMs);
transmitting the information to the processor (¶ 24-25). The information is transferred (transmitting) to the host, and accordingly, the processor within the host.
Hirao discloses retrieving a first part of the information that is stored in the first memory device as first information stored in the one or more caches; retrieving a second part of the information from the plurality of [additional memory] as second information to supplement the first information due to less than all the information being stored in the one or more caches (claim 3). The host command determines that some of the requested data (first information) is located in the cache, and retrieves it from the cache, and then redefines the remaining data that is not in the cache (second data) as the requested data, and retrieves it from the additional memory to supplement the data retrieved from the cache.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the read caching of Hicken to allow part of data to be retrieved from cache, and part of it to be retrieved from another level of memory, as in Hirao, because it would be applying a known technique to improve a similar method in the same way. Hicken discloses determining whether to service a read request from a cache or another memory. Hirao also discloses determining whether to service a read using cache or another memory, which has been improved in a similar way to the claimed invention, to allow for a partial hit to be serviced by both the cache and the additional memory. It would have been obvious to one having ordinary skill in the art to allow cached data to be retrieved from the cache, and non-cached data to be retrieved from the other memory, because it would yield the predictable improvement of reducing the amount of data that needs to be retrieved from the comparatively slow other memory.
Hicken and Hirao both disclose additional memory which store data that is not in the cache (e.g. Hicken, Fig. 1, memory 116); however, it is not specified whether this is a DRAM, let alone a plurality of DRAM DIMMs.
Brewer discloses the following:
the plurality of memory devices comprises one or more caches on separate integrated circuits (¶ 5; claim 42). The memory of the computing system (plurality of memory devices) includes one or more caches, which may be located on an integrated circuit (one or more caches on separate integrated circuits) (¶ 5). It is noted that it is not clear what the “integrated circuits” must be separate from, as no point of comparison is being given. Examiner interprets the circuit storing the one or more caches to be separate from other components of the storage system. Nevertheless, the integrated circuit that makes up the processors and cache may be separate from another IC that comprises the memory controller (claim 42).
and a plurality of dynamic random access memory (DRAM) dual in-line memory modules (DIMMs) (Fig. 4, memory 402; ¶ 62). The memory of the computing system (plurality of memory devices) includes a plurality of DRAM modules, commonly deployed as DIMMs;
retrieving a second part of the information from the plurality of DRAM DIMMS (¶ 13). If data is not in the cache, it may be retrieved from the main memory, which may be a DRAM DIMM.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory of Hicken (combined with Brewer) to include a plurality of DRAM DIMMs, as in Brewer, because it would be applying a known technique to improve a similar method in the same way. Hicken (combined with Hirao) discloses a computing system comprising a memory hierarchy of memory and caches. Brewer also discloses a memory hierarchy of memory and caches, which has been improved in a similar way to the claimed invention, for the memory to be implemented as a plurality of DRAM DIMMs. It would have been obvious to modify the memory of Hicken (combined with Hirao) to utilize a plurality of DRAM DIMMs, as in Brewer, because it would yield the predictable improvement of increasing memory bandwidth and/or capacity to utilize multiple DRAM DIMMs.
Re claim 6, Hicken, Hirao, and Brewer disclose the method of claim 1, and Hicken further discloses the following:
receiving an additional memory request for additional information at the interface device from the processor (Fig. 1; ¶ 21). See claim 1 above. Furthermore, Hicken discloses subsequent requests (additional memory requests) and subsequent flushing routines (¶ 34);
performing an additional cache look-up routine in the one or more caches of the memory device to select a second memory device of the plurality of memory devices and the persistent memory (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). See claim 1 above;
receiving the additional information that is stored in the first memory device as third information when the additional information is stored in the one or more caches; retrieving the additional information from the persistent memory as fourth information if less than all of the additional information is stored in the one or more caches; and (Fig. 2; ¶ 21-25). See claim 1 above;
transmitting the additional information to the processor (¶ 24-25). See claim 1 above.
Re claim 7, Hicken, Hirao, and Brewer disclose the method of claim 1, and Hicken further discloses that the processor does not perform a disk input/output routing to receive the first information (¶ 24-25). The processor of the host requests the information, and then the disk array controller returns the data to the host (and processor); there is no mention of the processor performing a disk input/output routing operation.
Re claim 11, Hicken, Hirao, and Brewer disclose the method of claim 1, from the perspective of the memory controller (receiving from the processor); accordingly, they also disclose a method written from the perspective of the processor (sending requests to the memory controller), as in claim 11.
Re claim 16, Hicken, Hirao, and Brewer disclose the method of claim 1, and Hicken further discloses the following:
transmitting an additional memory request for additional information to the interface device (Fig. 1; ¶ 21). See claim 1 above. Furthermore, Hicken discloses subsequent requests (additional memory requests) and subsequent flushing routines (¶ 34);
receiving the additional information at the processor from the interface device after the interface device has: performed an additional cache look-up routine in the one or more caches to select a second memory device of the one or more caches; and (Fig. 1, memory 116, write cache 126, disk array 106; ¶ 8, 19, and 21-25). See claim 1 above;
retrieved a first part of the additional information that is stored in the second memory device and retrieved a second part of the additional information from [additional memory] as fourth information due to less than all of the information being stored in the one or more caches (Fig. 2; ¶ 21-25). See claim 1 above.
Hirao further discloses retrieved a first part of the additional information that is stored in the second memory device and retrieved a second part of the information from the plurality of [additional memory] as fourth information to supplement the additional information due to less than all the additional information being stored in the one or more caches (claim 3). See claim 1 above.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hicken, Hirao, and Brewer, for the reasons noted in claim 1 above.
Re claims 17, Hicken, Hirao, and Brewer disclose the method of claim 1 above; accordingly, they also discloses a system implementing that method, as in claim 17 (see Hicken, ¶ 5).
Claims 2-4, 12-14, and 20 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Hirao, further in view of Brewer, further in view of Faibish et al (US 7873619 B1).
Re claim 2, Hicken, Hirao, and Brewer disclose the method of claim 1; furthermore, while they disclose that memory is persistent, they do not explicitly specify what kind of persistent memory is used. Accordingly, Examiner has provided Faibish.
Faibish discloses that the persistent memory comprises a solid-state drive (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the persistent memory of Hicken (combined with Hirao and Brewer) as a non-volatile SSD flash memory, as in Faibish, because Faibish suggests that using this type of memory would provide advantages such as fast access rate, high throughput, high integration density, and stability against external impact (col. 13, lines 6-12).
Re claim 3, Hicken, Hirao, and Brewer disclose the method of claim 1; furthermore, while they disclose that the memory is persistent, they do not explicitly specify what kind of persistent memory is used. Accordingly, Examiner has provided Faibish.
Faibish discloses that the persistent memory comprises a non-volatile memory (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hicken, Hirao, Brewer, and Faibish, for the reasons noted in claim 2 above.
Re claim 4, Hicken, Hirao, Brewer, and Faibish disclose the method of claim 3, and Faibish further discloses that the non-volatile memory comprises a flash memory (SSD) (col. 12, line 24 to col. 13, line 12, and col. 21, lines 8-17). The persistent memory is a non-volatile SSD flash memory.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Hicken, Hirao, Brewer, and Faibish, for the reasons noted in claim 2 above.
Re claims 12-14, Hicken, Hirao, Brewer, and Faibish disclose the methods of claims 2-4 above, respectively; accordingly, they also disclose those same limitations as applied to parent claim 11, as in claims 12-14, respectively.
Re claim 20, Hicken, Hirao, Brewer, and Faibish disclose the method of claim 4 above; accordingly, they also disclose a system implementing that method, as in claim 20 (see Hicken, ¶ 5).
Claims 8-9 are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Hirao, further in view of Brewer, and further in view of Binkert et al (US 2009/0103855 A1).
Re claim 8, Hicken, Hirao, and Brewer disclose the method of claim 1, but do not specifically disclose a stack of memory devices.
Binkert discloses that the plurality of memory devices is arranged in a stack (¶ 42). A plurality of DRAM memory devices are stacked into a stack.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the memory devices of Hicken (combined with Hirao and Brewer) as a stack, as in Binkert, because Binkert suggests that stacking memory dies provides shorter, lower-resistance interconnections, which reduces power requirements to transmit signals (¶ 31).
Re claim 9, Hicken, Hirao, Brewer, and Binkert disclose the method of claim 8, and Brewer further discloses that DRAM devices are DRAM DIMMs (Fig. 4, memory 402; ¶ 62). See claim 1 above.
Binkert further discloses that the stack comprises a plurality of DRAM [devices] that uses a plurality of channels (¶ 42). The stacked memory devices are DRAM, and utilize a plurality of channels.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to implement the memory devices of Hicken (combined with Hirao and Brewer) as a DRAM stack with a plurality of channels, as in Binkert, because Binkert suggests that stacking DRAM provides shorter, lower-resistance interconnections, which reduces power requirements to transmit signals (¶ 31), while utilizing a plurality of channels increases bandwidth (¶ 42).
Claim 10 is rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Hicken in view of Hirao, further in view of Brewer, further in view of Allen et al (US 2009/0172345 A1).
Re claim 10, Hicken and Brewer disclose the method of claim 1, but do not specifically disclose tags or LBA tables.
Allen discloses storing cache tag values or logical block address (LBA) tables in the plurality of memory devices (¶ 4). The memory device, which can be a plurality of memory devise, may store a translation table which includes LBASs (logical block address table). The tables can be maintained in the individual memory devices.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the memory devices of Hicken (combined with Hirao and Brewer) to store LBA tables in them, as in Allen, because it would be applying a known technique to a known method ready for improvement, to yield predictable results. Hicken (combined with Hirao and Brewer) discloses caches used to cache from persistent memory, which is ready for the improvement of having a LBA table to manage memory translations. Allen discloses managing LBA translations using a table which can be stored in the memory devices themselves, which is applicable to the memory of Hicken. It would have been obvious to integrate the LBA tables of Allen into the memory devices of Hicken (combined with Hirao and Brewer), because it would yield the predictable result of providing the memory devices with tables which can be used to locate memory using LBAs.
ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT
Response to Amendment
Applicant’s arguments with respect to claims 1-4, 6-14, 16-17, and 20 filed 05/21/2026 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
ARGUMENTS CONCERNING 35 USC § 112, SECOND PARAGRAPH REJECTIONS
Re claims 1-4, 6-14, 16-17 and 20, Applicant argues that the amended claims are sufficient to overcome Examiner’s previous rejections under 35 USC § 112, second paragraph. In response, Applicant’s argument has been fully considered, and is deemed persuasive. Accordingly, Examiner’s prior rejection under 35 USC § 112(b) have been rendered moot, and are accordingly withdrawn.
ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Re claims 1, 11, and 17, Applicant argues that Hicken and Brewer do not disclose the newly amended limitation “retrieving a first part of the information that is stored in the first memory device as first information stored in the one or more caches; retrieving a second part of the information from the plurality of DRAM DIMMs as second information to supplement the first information due to less than all the information being stored in the one or more caches”. In response, Applicant’s argument has been fully considered, but is moot in view of new grounds for rejection. New reference Hirao discloses handling partial cache hits by retrieving the cached portion from the cache, and redefining the read request to include the portions not found in the cache, so that the remaining data will be retrieved from another memory (claim 3). Furthermore, Brewer discloses retrieving data that is not in a cache from DRAM DIMMs (¶ 13).
Re claims 2-4, 6-10, 12-14, 16, and 20, Applicant argues that the claims are allowable by virtue of their dependence upon one of claims 1, 11, and 17 above, respectively; as this is the sole argument for allowability, Applicant is directed to Examiner’s rejections of claims 1, 11, and 17 above, respectively.
All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 05/21/2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Vemula et al (US 7596707 B1). Discloses reading requested data from DRAM DIMMs when there is a cache miss (col. 3, lines 16-36).
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Per the instant office action, claims 1-4, 6-14, 16-17 and 20 have received an action on the merits and are subject to a final rejection.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6.
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/CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132
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