DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restriction
Claims 9-16 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on February 02, 2026.
Applicant's election with traverse of species II of claims 9-16 in the reply filed on February 02, 2026 is acknowledged. The traversal is on the ground(s) that the Restriction has failed to show a serious burden on the Examiner if the restriction is not required. This is not found persuasive because species II of claims 9-16 is directed to the embodiment shown in FIG. 3 of the injection locking oscillator (ILO) circuit 300 only. For example, as recited in claims 9-11 and shown in FIG. 3, the first amplifier is directed to the amplifier 302, the second amplifier is directed to the amplifier 306, and the phase control circuit is directed to the phase control circuit 305. Clearly the special technical features of species II are not required for the special technical features in species I of claims 1-8 and 17-20 as shown in other embodiments of the IOL circuits in the drawings. Further, the addition of new claim 21, which broadly recites a phase control circuit coupled to the injection locking oscillator circuit, the phase control circuit configured to adjust an output clock of the injection locking oscillator circuit to a selected phase, while the phase control circuit recited in claims 10 and 11 of species II is specific as stated above. Therefore, species I and species II are distinct and represent separate inventive efforts, thus requiring individual analysis by searching different queries or search techniques of a separate and additional search effort. The requirement is still deemed proper and is therefore made FINAL.
Specification
The disclosure is objected to because of the following informalities:
Paragraph 32, line 6, “and output” should be “an output”.
Appropriate correction is required.
Claim Objections
Claims 1-8, 18, and 21 are objected to because of the following informalities:
1. (Original) A circuit comprising:
an injection locking oscillator circuit having an input and an output; and
a sense circuit including:
a sampling circuit having a first input coupled to the input of the injection locking oscillator circuit, a second input coupled to the output of the injection locking oscillator circuit, and an output; and
a comparator having an input coupled to the output of the sampling circuit, and an output.
2. (Proposed Amendment) The circuit of claim 1, wherein the sense circuit further includes a delay circuit having an input coupled to the output of the injection locking oscillator circuit, and an output coupled to the second input of the sampling circuit.
3. (Proposed Amendment) The circuit of claim 1, wherein the sense circuit further includes an amplifier having an input coupled to the input of the injection locking oscillator circuit, and an output coupled to the first input of the sampling circuit.
4. (Proposed Amendment) The circuit of claim 1, wherein:
the sense circuit further includes a frequency divider circuit having an input coupled to the second input of the sampling circuit, and an output; and
the input of the comparator is a first input, and the comparator has a second input coupled to the output of the frequency divider circuit.
6. (Proposed Amendment) The circuit of claim 5, wherein the correction circuit includes a multiplexer configured to:
pass a first signal from the first input of the correction circuit to the output of the correction circuit based on a phase signal at the third input having a first state; and
pass a second signal from the second input of the correction circuit to the output of the correction circuit based on the phase signal at the third input having a second state.
7. (Proposed Amendment) The circuit of claim 1, further comprising a correction circuit having:
a first input coupled to a first locking signal terminal of a reference clock circuit;
a second input coupled to a second locking signal terminal of the reference clock circuit;
a third input coupled to the output of the comparator; and
an output coupled to the input of the injection locking oscillator circuit.
8. (Proposed Amendment) The circuit of claim 1, wherein the injection locking oscillator circuit includes:
a first amplifier having an input coupled to the input of the injection locking oscillator circuit, and an output coupled to the output of the injection locking oscillator circuit;
a second amplifier having an input coupled to the output of the first amplifier, and an output coupled to the output of the first amplifier; and
an inductor-capacitor tank circuit coupled to the output of the first amplifier.
18. (Proposed Amendment) The transceiver circuit of claim 17, wherein the sense circuit includes:
an amplifier having an input configured to receive the locking signal, and an output;
a delay circuit having an input coupled to the output of the ILO circuit, and an output, the delay circuit configured to provide a delayed ILO output clock at the output of the delay circuit;
a sampling circuit having a first input coupled to the output of the amplifier, a second input coupled to the output of the delay circuit, and an output, the sampling circuit configured to sample the delayed ILO output clock based on the locking signal, and provide, at the output of the sampling circuit, a sample signal;
a comparator having a first input coupled to the output of the sampling circuit, a second input, and an output, the comparator configured to compare the sample signal to a reference voltage, and provide a phase signal, at the output of the comparator, indicating that the ILO output clock has one of two phases relative to the locking signal;
and
a frequency divider circuit having an input coupled to the output of the delay circuit, and an output coupled to the second input of the comparator, the frequency divider circuit configured provided a frequency divided signal by dividing the delayed ILO output clock by a divisor value.
21. (Proposed Amendment) The circuit of claim 1, further comprising a phase control circuit coupled to the injection locking oscillator circuit, the phase control circuit configured to adjust an output clock of the injection locking oscillator circuit to a selected phase.
Claim 5 depends from claim 1, therefore it is also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 17-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The phrase “the locking signal” recited in line 8 of claim 17 lacks antecedent basis because it is unclear which of the common phrase “a locking signal” recited in line 5 and line 6 of the claim is reference to.
Claims 18-20 all depend from claim 17, therefore they are also rejected.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zinevich (US 2013/0291044 A1), hereinafter “Zinevick”.
Zinevich illustrates a system 10 in FIG. 1 includes at least a reference unit 20, wherein the reference unit 20 comprises: a navigation (GPS) receiver 28 and an antenna 30; a multi-channel digital receiver 32; a programmable data processor or computer 34; and a communications interface 36.
FIG. 2 illustrates a block diagram of the digital receiver 32 comprising: a splitter 32a to create multiple outputs, which are applied to the inputs of N channels 32b, each channel 32b comprises an RF receiver and a digital sampler. The RF receiver includes a local oscillator (LO) 32c, an RF analog down-converter 32d, and a lowpass filter 32e. The digital sampler (in this embodiment) is an analog-to-digital converter (ADC) 32f, the output of the samples is coupled to the computer 34.
Regarding claim 1, as illustrated in Figures 1 and 2, a circuit (reference unit 20) comprising: an injection locking oscillator circuit (local oscillator 32c) having an input (from the output of the GPS receiver 28) and an output; a sense circuit including: a sampling circuit (digital sampler or analog-to-digital converter (ADC) 32f) having a first input coupled to the input of the injection locking oscillator circuit, a second input coupled to the output of the injection locking oscillator circuit, and an output; and a comparator (computer 34) having an input coupled to the output of the sampling circuit, and an output. Applicant note that a digital computer inherently comprises a comparator, a computer's Central Processing Unit (CPU) requires the ability to compare two values to make logical decisions, execute conditional jumps, and process code.
Regarding claim 2, wherein the sense circuit includes a delay circuit (lowpass filter 32e) having an input coupled to the output of the injection locking oscillator circuit, and an output coupled to the second input of the sampling circuit. Applicant note that although the lowpass filter 32e is not strictly considered a dedicated “delay circuit,” but it inherently introduces time delay and phase shift to the signals passing through it. As a signal passes through the filter, the output waveform is shifted in time relative to the input. This shift is frequency-dependent, meaning different frequencies are delayed by different amounts.
Regarding claim 21, as shown in Figures 1 and 2, the reference unit 20 further comprising a phase control circuit (computer 34) coupled to the injection locking oscillator circuit, inherently, the phase control circuit is configured to adjust an output clock of the injection locking oscillator circuit to a selected phase.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Oosawa et al. (US 2003/0203720 A1), hereinafter “Oosawa” in view of Borras et al. (US 4,484,153), hereinafter “Borras”.
Oosawa illustrates an example of a high-speed pull-in PLL circuit in FIG. 1 comprising: an RF Voltage Controlled Oscillator (VCO) 10; a reference oscillation circuit (TCXO) 11 which uses a crystal oscillator and oscillates at precise high frequencies; a variable frequency divider 12 for dividing the frequency of an oscillation signal of the VCO 10; a fixed frequency divider 13 for dividing the frequency of a reference oscillation signal of the reference oscillation circuit 11; a phase comparator 14 for comparing the phase of a signal subjected to frequency division of the variable frequency divider 12 with the phase of signal subjected to frequency division of the fixed frequency divider 13 and outputting a voltage UP or DOWN according to a phase difference; a charge pump 15; and a loop filter 16. A PLL loop in which the capacitive element of the loop filter 16 is charged up by the charge pump 15, and the resultant is output as a control voltage Vc of the VCO 10 and the VCO 10 is oscillated at predetermined frequencies is constructed. The PLL circuit of the embodiment includes: a switch SW0 provided between the charge pump 15 and the loop filter 16, capable of supplying a predetermined direct-current voltage VDC in place of a voltage Vc from the charge pump 15 at the time of frequency measurement or PLL pull-in; a pull-in initial voltage generating circuit 17 for generating the direct-current voltage VDC to be applied to the charge pump 15; the variable frequency divider 12 for calculating an oscillation signal of the VCO 10 and dividing the frequency; a storing circuit 18 constructed by a register or the like for storing a value obtained by calculation of the variable frequency divider 12; a band determining circuit 19 for comparing a frequency value stored in the storing circuit 18 with set values from the outside into the variable frequency divider 12 and generating band switch signals VB3 to VB0 of the VCO 10; and a control circuit 20 for controlling the switch SW0, variable frequency divider 12, storing circuit 18, and band determining circuit 19.
Regarding claim 17, the PLL circuit comprises: an injection locking oscillator (ILO) circuit (VCO 10) having an input configured to receive a locking signal (from the phase comparator 14), and an output, the ILO circuit configured to provide, at the output, an ILO output clock having a frequency based on a frequency of a locking signal; a sense circuit (prescaler 21 and counters 22) coupled to the ILO circuit, the sense circuit configured to sense a phase of the ILO output clock relative to the locking signal, and provide a phase signal representing the phase; and a correction circuit (register 18 and band determining circuit 19) coupled to the sense circuit and the ILO circuit, the correction circuit configured to adjust a phase of the SILO output clock based on the phase signal.
Although Oosawa does not explicitly show or teach that the PLL circuit is implemented in a transmitter circuit of a transceiver circuit, it is not new in the art that a PLL circuit can be implemented in both a transmitter circuit and a receiver circuit of a transceiver circuit.
Borras illustrates a VHF transceiver circuit in FIG. 3 employing a receiver section 72 and a digital frequency synthesizer in a transmitter section 74.
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art as taught by Borras to implement Oosawa’s PLL circuit in a transmitter circuit of a transceiver circuit in order to enable direct frequency modulation and ultra-precise channelization for outbound data and allow a transmitter to lock onto exact, fine-tuned frequencies (e.g., specific Wi-Fi or cellular channels) referenced to a single stable crystal oscillator. This guarantees that the output signal sits perfectly within its allocated spectral mask without drifting.
Applicant note, in practical RF design, the PLL is rarely restricted to just the transmitter or the receiver, most modern transceivers feature multiple PLLs or a shared PLL that routes to both sections. In the receiver, a PLL provides the exact tuning frequency required for a mixer to down-convert faint, high-frequency inbound signals into manageable intermediate frequencies (IF).
Allowable Subject Matter
Claims 3-8 and 18 would be allowable if rewritten to overcome the objection(s) set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 18-20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang et al. relates to a circuit includes a phase selector to generate an injection clock signal having an injection phase based on a phase of a digitally controlled oscillator clock signal generated within a phase-locking feedback loop. An injection-locked oscillator (ILO), coupled to an output of the phase selector, generates an ILO clock signal that is convertible to provide a feedback clock signal of the circuit. Logic, coupled between an output of the ILO and the phase selector, to, at each predetermined number of cycles of the DCO clock signal, cause the phase selector to output a phase shift in the injection clock signal that causes the ILO clock signal to comprise a rotated phase, relative to the injection phase, and that prevents a glitch in the injection clock signal.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Young T. Tse whose telephone number is (571)272-3051. The examiner can normally be reached Mon-Fri 10:30am-7pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chieh M Fan can be reached at 571-272-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Young T. Tse/Primary Examiner, Art Unit 2632
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