DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments filed on 03/17/2026 with respect to claims 1, 12, and 18 have been considered but are moot in view of the of rejection below.
Dependent claims 2 – 11, 13 – 17, 19, and 20 are not allowable for being dependent on independent claims 1, 12, and 18 which are not allowable.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claim 18 is rejected on the ground of nonstatutory double patenting as being unpatentable over claim 17 of Kale U.S. Patent No. 12,028,638 in view of Turek et al US Publication No. 2021/0150323.
Regarding claim 18 Kale 12,028,638 discloses of applicant’s a device, comprising (claim 17, An apparatus, comprising):
an image sensing pixel array (claim 17, a first integrated circuit die having an image sensing pixel array);
an array of memory cells, wherein each respective memory cell in the array has a threshold voltage programmable in a first mode to facilitate operations of multiplication and accumulation and programmable in a second mode to store data (claim 17, a third integrated circuit die having a memory cell array, wherein threshold voltages of memory cells in the memory cell array are programmable in a first mode to facilitate operations of multiplication and accumulation and programmable in a second mode to store data);
a transceiver (claim 17, a transceiver);
and a circuit configured to:
program, in the first mode, a first memory cells (claim 17, wherein the integrated circuit device is configured to: program, in the first mode, first memory cells in the memory cell array); program, in the second mode, a second memory cells to store data representative of images captured by the image sensing pixel array (claim 17, and program, in the second mode, second memory cells in the memory cell array to store data representative of images captured by the image sensing pixel array);
Kale 12,028,638 further discloses of applicant’s perform operations of multiplication and accumulation using the first memory cells in determination of first classifications for the images respectively (claim 17, wherein the digital camera is configured to store meta data for the images to identify a subset of the images as part of training data, including first images in the subset, first classifications of the first images determined by the artificial neural network and perform operations of multiplication and accumulation using the first memory cells to determine the first classifications);
receive, via the transceiver, second classifications for the images respectively (claim 17, wherein the digital camera is configured to store meta data for the images to identify a subset of the images as part of training data, including first images in the subset, and second classifications of the first images received via the transceiver);
and reduce mismatches between classifications (claim 17, execute computation instructions to determine second weight matrices of the artificial neural network to reduce mismatches between the first classifications and the second classifications);
Kale 12,028,638 discloses a method of programing memory cells in the memory cell array in a first mode to facilitate operations of multiplication and accumulation and to store first weight matrices of an artificial neural network and programmable in a second mode of second memory cells in the memory cell array to store data representative of images captured by the image sensing pixel array but does not expressively disclose a first subset of the memory cells; a second subset of the memory cells; receive from a computer system;
Turek et al teaches a method of having a layered memory tile structure that is accessed by a computing device. Turek et al teaches of Fig. 1 – 15 of applicant’s a first subset of the memory cells and a second subset of the memory cells (paragraph 0051, Fig. 6, tile architecture is used to implement the memory cells 302 of FIG. 3. The tile architecture is also referred to herein as a cross-point architecture (e.g., an architecture in which memory cells sit at the intersection of word lines and bit lines and are individually addressable and in which bit storage is based on a change in bulk resistance), in which each memory cell tile 610, 612, 614, 616, 618, 620, 622, 624, 626, 628, 630, 632, 634, 636, 638, and 640 is addressable by an example x parameter and an example y parameter (e.g., a column and a row). The memory cells 302 includes multiple partitions, each of which includes the tile architecture. The partitions are stacked as layers 602, 604, 606 to form a three-dimensional cross-point architecture such that the layers 602, 604, 606 that have tile architecture are taken as a first and second subset of the memory cells of memory cells 302); receive from a computer system (paragraph 0044 communication circuitry 380 is generally configured to transmit information from the example compute device 300 and/or receive information at the compute device 300 via, for example, a network such that compute device 300 is a computer system that receives information from communication circuitry 380). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Kale in a manner similar to Turek et al. Doing so would result improving Kale invention in a similar way as Turek et al – namely the ability to provide a method of having a layered memory tile structure that is accessed by a computing device, in Turek et al invention, to the method of programing memory cells in the memory cell array in the first and second modes in Kale invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Das Sarma US Publication No. 2020/0349216 in view of Vogel et al US Publication 2021/0256376.
Regarding claim 1 Das Sarma discloses of Fig. 1 – 8 of applicant’s a device (paragraph 0026 training system device is for training a machine learning model process), comprising: an integrated circuit package (paragraph 0026 vehicle sub-systems 201 including sensors 203, deep learning network 205, AI processor 207, vehicle control module 209, network interface 211, vehicle data capture system 213, and capture data store 215 and training data center(s) 221 including training platform 223, training data store 227, and model data store 229. Training platform 223 includes at least one or more node engines 225 are an integrated circuit package for being circuits that are integrated together); memory cells configured an array in the integrated circuit package (paragraph 0037 node engines 300 has a matrix computation unit 325 are memory cells that includes a matrix array of computational cells such as computational cell 327 having a M×N dimension matrix computational unit includes M×N computational cells connected to the node engines 225); and a logic circuit configured in the integrated circuit package (paragraph 0039 control unit 301 is communicatively connected to one or more components of node engine 300 including memory 303, matrix processor 313, output array 315, and post-processing unit 317. Although not shown, control unit 301 is also communicatively connected to each of the remaining matrix processors 351 – 357 such that control unit 301 is a logic circuit in the node engine 300 that is configured in the integrated circuit package);
Das Sarma further discloses of applicant’s wherein the logic circuit is configured to program the memory cells in a first mode and program the memory cells in a second mode, different from the first mode, to store data (paragraph 0037 node engines 300 has a matrix computation unit 325 are memory cells that includes a matrix array of computational cells such as computational cell 327 having a M×N dimension matrix computational unit includes M×N computational cells. Paragraph 0056 control unit 301 issues matrix instructions operations including matrix multiplication, matrix addition, and dot-product, matrix inverse. Paragraph 0023 the result of the training is one or more trained machine learning models where multiple models are trained, each for potentially different neural networks where one machine learning model may be trained to utilize as input the sensor data from a forward facing camera and another model may be trained to utilize as input the sensor data from a side-facing ultrasonic sensor. Paragraph 0040 memory 303 is a memory module for storing the input operands and output results of matrix computations and post-processing computations such that the control unit 301 logic circuit is configured to program and model the matrix computation unit 325 memory cells in a first mode having input the sensor data from a forward facing camera and program and model the matrix computation unit 325 memory cells in a second mode having the input the sensor data from a side-facing ultrasonic sensor, different from the first mode, to store post-processing computations data in memory 303 in for different neural networks); wherein the logic circuit is further configured to perform operations (paragraph 0039 control unit 301 is communicatively connected to one or more components of node engine 300 where (paragraph 0026) of a system for training a machine learning model, node engines 225 are connected to perform parallelized processing for machine learning training such that the control unit 301 logic circuit is further configured to perform operations for machine learning training);
Das Sarma discloses a system for training a machine learning model with a control unit that performs processing for machine learning training but does not expressively disclose the logic circuit is further configured to perform operations of the artificial neural network;
Vogel et al teaches a processor determines a result of the machine learning as a function of output values of the artificial neural network. Vogel et al teaches of Fig. 1 – 2 of applicant’s the logic circuit is further configured to perform operations of the artificial neural network (paragraph 0024 – 0026 of device 100 for machine learning with a processor 108, processor 108 is designed to communicate with memory controller 104 via data bus 106 for implementing a method for machine learning and it is provided that processor 108 predefines hyper-parameters, weights and input values for an artificial neural network, with which the machine learning is to be carried out further it is provided that processor 108 determines a result of the machine learning as a function of output values of the artificial neural network such that the processor 108 logic circuit is further configured to perform operations of the artificial neural network).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify the circuitry of Das Sarma in a manner similar to Vogel et al. Doing so would result improving Das Sarma invention in a similar way as Vogel et al – namely the ability to provide a processor determines a result of the machine learning as a function of output values of the artificial neural network, in Vogel et al invention, to the system for training a machine learning model with a control unit that performs processing for machine learning training in Das Sarma invention.
Regarding claim 12, claim 12 is rejected for being fully encompassed by the reasons found in rejected claim 1 above.
Allowable Subject Matter
Claims 2 – 11, 13 – 17, 19, and 20 are objected to as being dependent upon or ultimately dependent on a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK T MONK whose telephone number is (571)270-7454. The examiner can normally be reached Monday thru Friday 8am to 4pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at 571-272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARK T MONK/Primary Examiner, Art Unit 2637
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