DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 19-20 and 27-29 have been amended. Claims 1-29 have been examined.
Terminal Disclaimer
The terminal disclaimer filed on 3/13/2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of U.S. Patents 10817293, 11113051, and 12050913, and U.S. Patent Applications 17409577 and 19365741 has been reviewed and is accepted. The terminal disclaimer has been recorded.
Response to Arguments/Amendments
The prior double patenting rejections are withdrawn in view of the 3/13/2026 terminal disclaimer.
The prior claim objection is withdrawn in view of the 3/13/2026 amendment.
Applicant's arguments filed 3/13/2026 have been fully considered but they are not persuasive.
On pp. 13-14 of the 3/13/2026 remarks, Applicant argues that cited art of record Temam does not teach or suggest “first metadata generated in a prior execution of a directed graph.” Applicant asserts that Temam’s “bitmap header is not generated as a result of executing the payload,” and “cannot constitute metadata generated during a prior execution of the directed graph.” As noted in the rejection, a “prior execution” can be broadly construed in view of Temam’s directed graph in terms of execution of tiles, each of which generate/modify a bitmap header to be forwarded to the next tile. The teaching of Temam applies to a broad but reasonable interpretation of the claimed limitations.
On pp. 14-15 of the remarks, Applicant argues with respect to claim 1 that the combination of cited art of record Temam in view of Sideris fails to teach or suggest “(ii) a conditional execution of the instruction, using the execution engine and as conditioned by the control logic using the first metadata, generates a conditionally executed output.” In particular, Applicant argues that the claims require that execution is conditioned using metadata but that Sideris’ execution is based on the input data itself which cannot be construed as metadata as defined in Applicant’s specification. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). It is noted that the rejection initially cites Temam ¶ 0031 to disclose the use of metadata for conditional instruction execution. In this respect, Temam is essentially relied upon to teach conditional instruction execution. However, Temam fails to fully teach such conditional execution in terms of a standard execution and a less computationally intensive conditional execution. These limitations are further taught by Sideris as indicated in the rejection. Sideris was not relied upon in isolation to teach conditional execution using metadata, since such teaching is supplied by Temam. Instead, Sideris is relied upon to teach a conditional execution that is less computationally intensive than a standard execution as detailed below. The rejection is based upon the combined teaching of the cited art. Applicant’s argument is not persuasive.
On pp. 15-16 of the remarks, Applicant argues that the combination of Temam and Sideris is based on “incompatible architectures.” Applicant essentially suggests that combining Temam’s data transmission between tiles with Sideris’ localized lookup table would be “inefficient and contrary to the design of Sideris.” In response to applicant's argument that the combination of Temam and Sideris is based on incompatible architectures, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). The combination of Temam and Sideris provides the fundamental teaching of using metadata to provide execution using either a “standard execution” or a “less computationally intensive” conditional execution. Despite different modes of execution, both Temam and Sideris utilize some form of conditional execution. One of ordinary skill in the art would recognize any differences in implementation and would have good reason to modify the combined teaching of Temam with Sideris to provide the benefit of reduced power consumption and avoidance of duplication of processing as suggested by Sideris.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971). Both Temam and Sideris teach elements of a less computationally intensive conditional execution. The benefits of conditional execution are known to those of ordinary skill in the art as exemplified by the teaching of Sideris. Applicant has not shown that the combination includes knowledge gleaned only from the applicant's disclosure.
On p. 17 of the remarks, Applicant argues that Temam and Sideris fail to teach the claimed “data tile,” suggesting that Temam’s tiles are processing units, not units of data. However, while Temam’s discussion of tiles may focus on hardware, they also require data to properly function. The claimed “data tile” can be broadly construed according to the data required for tile execution. As such, Temam teaches data tiles according to a broad but reasonable interpretation of the claims.
Further arguments on pp. 18-19 of the remarks are based upon prior arguments and are not persuasive for the same reasons indicated above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5-6, 8, 11-16, 18 and 25-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication 20180121196 by Temam et al. ("Temam") in view of U.S. Patent Application Publication 20150301826 by Sideris et al. ("Sideris").
In regard to claim 1, Temam discloses:
1. A processing core comprising: a memory; See Fig. 1, elements 102, 104, and 106.
a first data tile stored in the memory, wherein the first data tile includes a first set of data elements from a directed graph; Temam, ¶ 0005, “A tensor accessible from narrow memory and wide memory units, in a single compute tile, is traversed based on memory address values retrieved from registers.” ¶ 0019, “the layers of the neural network are arranged … in a directed graph.” Also ¶ 0073, “Activation values are stored in a narrow memory 210.”
first metadata generated in a prior execution of the directed graph or a prior simplified execution of the directed graph; Temam, ¶ 0031, “In one example, a header (i.e., a bitmap) of the instruction indicates, to a receiving tile, that the receiving tile needs to consume a particular instruction based on a bitmap associated with the instruction.” Also see ¶ 0038-0039, “As discussed above, ring bus 128 also includes a bitmap header indicating the tiles that need to consume payload data comprising instructions or parameters communicated via ring bus 128. ¶ With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.” A first tile modifies the payload data header which is then sent for subsequent execution to other tiles.
a second data tile stored in the memory, wherein the second data tile includes a second set of data elements; Temam, ¶ 0005, “A tensor accessible from narrow memory and wide memory units, in a single compute tile, is traversed based on memory address values retrieved from registers.” ¶ 0020, “multiplication of an input tensor including input activations with a parameter tensor including weights.” ¶ 0073, “another input (a parameter) is received from wide memory 212.”
an execution engine; an instruction, wherein execution of the instruction uses: (i) the execution engine; (ii) a first data element in the first set of data elements; and (iii) a second data element in the second set of data elements; and Temam, ¶ 0055, “Arithmetic operations performed by the MAC operators of the MAC array 214 generally include multiplying an input activation provided by narrow memory 210 with a parameter accessed from wide memory 212 to produce a single output activation value.”
control logic that uses the first metadata to condition execution of the instruction; Temam, ¶ 0031, “In one example, a header (i.e., a bitmap) of the instruction indicates, to a receiving tile, that the receiving tile needs to consume a particular instruction based on a bitmap associated with the instruction.”
Temam does not expressly disclose the remaining limitations. However, they are taught by Sideris:
wherein: (i) a standard execution of the instruction, using the execution engine, generates a standard output; Sideris, ¶ 0061, “When the lookup in the memo_table at stage s0 results into a miss (hit=0), the operation is performed as normal and there is no clock gating in the pipeline.”
(ii) a conditional execution of the instruction, using the execution engine and as conditioned by the control logic using the first metadata, generates a conditionally executed output; and Note that as indicate above, Temam teaches conditional execution by control logic using the first metadata as cited above by way of Temam, ¶ 0031: “In one example, a header (i.e., a bitmap) of the instruction indicates, to a receiving tile, that the receiving tile needs to consume a particular instruction based on a bitmap associated with the instruction.” Also see Temam ¶ 0047, “Results of the one or more tensor computations include writing output activations of a compute layer to a narrow memory unit(s) of the tile performing the computation.” This is further taught by Sideris. See Sideris, ¶ 0063, “The table lookup detects whether there is an entry with the same operation identifier and the same operands as the current micro-operation. If so, then at step 42 the line number is set to identify the table entry corresponding to the current micro-operation, the hit signal is asserted to indicate that there has been a match in the table 24, …”
(iii) the conditional execution of the instruction is less computationally intensive than the standard execution of the instruction. Sideris, ¶ 0040, “In some embodiments, power consumption can be reduced by reusing the result of the second micro-operation for the first micro-operation. The control circuitry may prevent the first processing lane processing the first micro-operation by placing at least part of the first processing lane in a power saving state during a processing cycle when it would otherwise be processing the first micro-operation. Hence, even if the first micro-operation gives the same result as the second micro-operation, it can still be passed to the processing circuitry of the first processing lane, but parts of the first processing lane may be placed in a power saving state so that they do not actually process the micro-operation in order to save power. This avoids duplication of processing which might occur if both the first and second processing lanes process the same micro-operation.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Sideris’ conditional execution with Temam’s data tile in order to reduce power consumption and avoid duplication of processing as suggested by Sideris.
In regard to claim 2, Temam also discloses:
2. The processing core of claim 1, wherein: the first data tile is a first portion of the memory that is addressable by a single physical or virtual address; and the second data tile is a second portion of the memory that is addressable by another single physical or virtual address. Temam, ¶ 0005, “A tensor accessible from narrow memory and wide memory units, in a single compute tile, is traversed based on memory address values retrieved from registers. Memory address values correspond to elements of the tensor.” Also ¶ 0054, “Generally, compute tile 200 receives input activations via data path 205 and DMA control 208 executes an operation to write the input activations into narrow memory 210. Likewise, compute tile 200 receives parameters (weights) via data path 202 and DMA control 208 executes an operation to write the parameters into wide memory 212.”
In regard to claim 5, Temam also discloses:
5. The processing core of claim 1, wherein: the execution engine comprises multipliers and accumulators; and the execution engine receives control inputs from low level kernel instructions of the processing core from the control logic. Temam, ¶ 0024, “In some implementations, instructions are received by controller 102 from host interface 118 at an initial time and stored in instruction memory 106 for execution by controller 102 at a later time.” ¶ 0055, “Arithmetic operations performed by the MAC operators of the MAC array 214 generally include multiplying an input activation provided by narrow memory 210 with a parameter accessed from wide memory 212 to produce a single output activation value.”
In regard to claim 6, Temam does not expressly disclose the limitations. However, they are taught by Sideris:
6. The processing core of claim 1, wherein: the first metadata, as stored in the memory, is from a prior execution of the instruction. See Sideris, ¶ 0040, “In some embodiments, power consumption can be reduced by reusing the result of the second micro-operation for the first micro-operation. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Sideris’ reuse with Temam’s instructions in order to reduce power consumption and avoid duplication of processing as suggested by Sideris.
In regard to claim 8, Temam also discloses:
8. The processing core of claim 1, further comprising: a core controller; wherein the first data tile and the second data tile have sizes that are set by commands received from the core controller. See Temam, Fig. 1 element 102. ¶ 0021, “In general, a tensor traversal unit of a compute tile executes control operations that provide the index of each dimension associated with the tensor and order in which index elements are traversed to perform computations.” Also ¶ 0042, “Controller 102 may examine the payload data to determine the number of data chunks or segments that comprise the payload.”
In regard to claim 11, Temam and Sideris also teach:
11. The processing core of claim 1, wherein: the execution engine executes the instruction in accordance with the standard execution of the instruction at a first time and in accordance with the conditional execution at a second time. See Sideris, ¶ 0040, “In some embodiments, power consumption can be reduced by reusing the result of the second micro-operation for the first micro-operation.
In regard to claim 12, Temam also discloses:
12. The processing core of claim 1, wherein: the directed graph is a neural network; the first set of data elements are activation values of an execution of the neural network; and the second set of data elements at least one of weight values and filter values of the neural network. Temam, ¶ 0016-0019, “machine learning inference workloads of a neural network layer … the layers are arranged in a directed graph.” ¶ 0020, “A computation process performed within a neural network layer may include a multiplication of an input tensor including input activations with a parameter tensor including weights.”
In regard to claim 13, Temam also discloses:
13. The processing core of claim 1, wherein: the directed graph is a neural network; the first set of data elements are at least one of weight values and filter values of the neural network; and the second set of data elements are activation values of an execution of the neural network. Temam, ¶ 0016-0019, “machine learning inference workloads of a neural network layer … the layers are arranged in a directed graph.” ¶ 0020, “A computation process performed within a neural network layer may include a multiplication of an input tensor including input activations with a parameter tensor including weights.”
In regard to claim 14, Temam also discloses:
14. The processing core of claim 1, wherein: the directed graph is a neural network; and the first data tile and the second data tile are both smaller than a layer of the neural network and larger than a single neuron’s weight value. Temam, ¶ 0016-0019, “machine learning inference workloads of a neural network layer … the layers are arranged in a directed graph.” Also ¶ 0021, “In general, a software algorithm is executed by a computing tile to perform tensor computations by processing a nested loop to traverse an N-dimensional tensor. In one example computational process, each loop may be responsible for traversing a particular dimension of the N-dimensional tensor. For a given tensor construct, a compute tile may require access to an element of a particular tensor to execute a plurality of dot product computations associated with the tensor.” Each loop represents a tile that is smaller than a layer, and the N-dimensional tensor relates to multiple weights.
In regard to claim 15, Temam also discloses:
15. The processing core of claim 1, further comprising: runtime hardware that updates the first metadata based on the execution of the instruction. Also see ¶ 0038-0039, “As discussed above, ring bus 128 also includes a bitmap header indicating the tiles that need to consume payload data comprising instructions or parameters communicated via ring bus 128. ¶ With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.” A first tile modifies the payload data header which is then sent for subsequent execution to other tiles.
In regard to claim 16, Temam also discloses:
16. The processing core of claim 1, further comprising: second metadata relationally stored in association with the second set of data elements; wherein the control logic uses the first metadata and the second metadata to condition execution of the instruction. Temam, ¶ 0039, “With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.” Metadata is stored in relation to payload data.
In regard to claim 18, Temam also discloses:
18. The processing core of claim 1, wherein: the prior execution is an upstream operation. Temam, ¶ 0039, “With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.”
In regard to claim 25, Temam discloses:
25. The processing core of claim 1, wherein: the instruction is part of a standard instruction sequence for the directed graph; and the first metadata is generated during an execution of the standard instruction sequence by the processing core. Temam, ¶ 0055, “Arithmetic operations performed by the MAC operators of the MAC array 214 generally include multiplying an input activation provided by narrow memory 210 with a parameter accessed from wide memory 212 to produce a single output activation value.” Also see ¶ 0038-0039, “As discussed above, ring bus 128 also includes a bitmap header indicating the tiles that need to consume payload data comprising instructions or parameters communicated via ring bus 128. ¶ With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.” A first tile modifies the payload data header which is then sent for subsequent execution to other tiles.
In regard to claim 26, Temam discloses:
26. The processing core of claim 1, wherein: the control logic conditions execution of the instruction using the first metadata in that the control logic conducts an analysis of the first metadata to condition the execution of the instruction. See ¶ 0038-0039, “As discussed above, ring bus 128 also includes a bitmap header indicating the tiles that need to consume payload data comprising instructions or parameters communicated via ring bus 128.”
In regard to claim 27, Temam discloses:
27. A processing core comprising: See Fig. 1.
All further limitations of claim 27 have been addressed in the above rejection of claim 1.
In regard to claim 28, Temam discloses:
28. A processing core comprising: See Fig. 1.
All further limitations of claim 28 have been addressed in the above rejection of claim 1.
In regard to claim 29, Temam discloses:
29. A method comprising: See Fig. 6, broadly depicting a method.
All further limitations of claim 29 have been addressed in the above rejection of claim 1
Claim(s) 3-4, 7, 19-21 and 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Temam in view of Sideris as applied above, and further in view of U.S. Patent Application Publication 20150347139 by Keramidas et al. ("Keramidas").
In regard to claim 3, Temam also discloses:
3. The processing core of claim 1, wherein: the first metadata is a flag indicating a type of conditional execution that should be conducted with the first data tile; Temam, ¶ 0033, “At a particular tile of tiles 112, 114, the bus stop associated with instruction bus 124 will examine the header bitmap to determine the instruction type/substype.”
… 8-bit computation …16-bit computation; Temam, ¶ 0034, “As used herein, “narrow” may refer to one or more memory units each having a size or width of less than 16-bits and “wide” may refer to one or more memory units each having a size or width or less than 64-bits.”
Temam does not expressly disclose: the conditional execution is an 8-bit computation; and the standard execution is a 16-bit computation. This is taught by Keramidas. See ¶ 0005, “When evaluating a particular code segment, this dedicated storage area is first checked to identified if the output results are saved in the area. If this is the case, i.e., a hit occurs in the dedicated storage area, the output results are immediately retrieved from the dedicated storage area and used by the software program. If the output results for the given set of input parameters do not exist in the storage area, the output results are calculated, as it would normally happen in a system without the technology provided in this application.” Also ¶ 0053, “lowering the precision of specific calculations.“ Also ¶ 0106, “lowering the precision of specific arithmetic calculations. That is to allow approximate memoizations to be performed.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s logic in order to improve performance as suggested by Keramidas (see ¶ 0053).
In regard to claim 4, Temam also discloses:
4. The processing core of claim 1, wherein: the first metadata is used to determine a type of conditional execution that should be conducted with the first data tile; See at least ¶ 0038-0039, “As discussed above, ring bus 128 also includes a bitmap header indicating the tiles that need to consume payload data comprising instructions or parameters communicated via ring bus 128. ¶ With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile.”
the standard execution uses a value; and Sideris, ¶ 0061, “When the lookup in the memo_table at stage s0 results into a miss (hit=0), the operation is performed as normal and there is no clock gating in the pipeline.”
Temam and Sideris does not expressly disclose: the conditional execution is a reduced precision type of computation which uses the value in a more basic format. However, this is taught by Keramidas. See ¶ 0018, “… reduce the precision of the input parameters during the process of matching the input parameters to the arguments stored in the special purpose functional unit, i.e., the value cache.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s logic in order to improve performance as suggested by Keramidas (see ¶ 0053).
In regard to claim 7, Temam does not expressly disclose:
7. The processing core of claim 1, wherein: the conditional execution of the instruction uses data elements with a decreased number of bits compared to the standard execution of the instruction; and the standard output and the conditionally executed output are not equivalent. However, this is taught by Keramidas. See ¶ 0018, “… reduce the precision of the input parameters during the process of matching the input parameters to the arguments stored in the special purpose functional unit, i.e., the value cache.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s logic in order to improve performance as suggested by Keramidas (see ¶ 0053).
In regard to claim 19, Temam does not expressly disclose:
19. The processing core of claim 1, wherein: … the second set of data elements are accessed based on the first metadata.
Temam, ¶ 0039, “With regard to data (i.e., payload) received at a particular tile via ring bus 128, in response to receiving the information, each tile will zero (i.e., clear out) position data indicated in the bitmap header that is unique to the receiving tile before forwarding the data on to another tile. Hence, when the header bitmap has no remaining bit set data indicating a particular tile that is to receive the payload, forwarding of the payload to another tile will stop.”
Temam does not expressly disclose: the control logic converts a data format of the second set of data elements while the second set of data elements are being accessed from the memory; and … However, this is taught by Keramidas. See ¶ 0100, “The purpose of transforming the input parameters, namely the input register operands, of a given PSCS is to bring them in a desired arrangement, so as to increase the occurrences of value cache hits. Consequently, the extra field 507 may contain an indicator of how a new set of input parameters may be transformed.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keramidas’ data transformation with Temam’s data in order to increase value cache hits and reduce redundant operations as suggested by Keramidas (see ¶ 0004).
In regard to claim 20, Temam does not expressly disclose:
20. The processing core of claim 1, wherein: the control logic converts a data format of the second set of data elements while the second set of data elements are being accessed from the memory; and the data format of the second set of data elements is converted based on the first metadata. However, this is taught by Keramidas. See ¶ 0099, “A preferred method to increase the occurrences of value cache hits may be to add an extra field in the instruction structure, like the field tagged as 507.” Also ¶ 0100, “The purpose of transforming the input parameters, namely the input register operands, of a given PSCS is to bring them in a desired arrangement, so as to increase the occurrences of value cache hits. Consequently, the extra field 507 may contain an indicator of how a new set of input parameters may be transformed.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Keramidas’ data transformation with Temam’s data in order to increase value cache hits and reduce redundant operations as suggested by Keramidas (see ¶ 0004).
In regard to claim 21, Temam does not expressly disclose:
21. The processing core of claim 1, wherein: the control logic conditions execution of the instruction by inspecting the first metadata …; and the instruction is a matrix multiply instruction. Temam, ¶ 0021, “A tensor is a multi-dimensional geometric object and example multi-dimensional geometric objects include matrices and data arrays. In general, a software algorithm is executed by a computing tile to perform tensor computations by processing a nested loop to traverse an N-dimensional tensor. In one example computational process, each loop may be responsible for traversing a particular dimension of the N-dimensional tensor. For a given tensor construct, a compute tile may require access to an element of a particular tensor to execute a plurality of dot product computations associated with the tensor.”
Temam does not expressly disclose: and reducing a precision of an operation for the instruction. However, this is taught by Keramidas. See ¶ 0018, “This special purpose functional unit may also employ additional functionality to reduce the precision of the input parameters.” Also ¶ 0053, “lowering the precision of specific calculations.“ It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s logic in order to improve performance as suggested by Keramidas (see ¶ 0053).
In regard to claim 23, Temam does not expressly disclose:
23. The processing core of claim 1, wherein: the conditional execution of the instruction includes replacing a value with a lower precision data element. However, this is taught by Keramidas. See ¶ 0018, “This special purpose functional unit may also employ additional functionality to reduce the precision of the input parameters.” Also ¶ 0053, “lowering the precision of specific calculations.“ It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s data values in order to improve performance as suggested by Keramidas (see ¶ 0053).
In regard to claim 24, Temam does not expressly disclose:
24. The processing core of claim 1, wherein: the conditional execution of the instruction includes replacing the first set of data elements with lower bit approximations. However, this is taught by Keramidas. See ¶ 0018, “This special purpose functional unit may also employ additional functionality to reduce the precision of the input parameters.” Also ¶ 0053, “lowering the precision of specific calculations.“ Also ¶ 0094, “approximate process.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Temam’s precision reduction with Temam’s data in order to improve performance as suggested by Keramidas (see ¶ 0053).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Temam in view of Sideris as applied above, and further in view of U.S. Patent 8736624 to Mahan et al. ("Mahan").
In regard to claim 9, Temam also discloses:
9. The processing core of claim 1, wherein: … and the first set of data elements are accessible from the memory using a single memory address. Temam, ¶ 0037, “In some implementations, a location or address of a narrow memory unit(s) that a particular input activation will be written to, or read from, …”
Temam does not expressly disclose: the first metadata. However, this is taught by Mahan. See Mahan, Fig. 3 and col. 5 lines 57-66, “For example, the header is shown in FIG. 3 as including sequence number 311 and conditional execution (CX) flag 313. In the depicted embodiment, the sequence number identifies, for example, the relative position of the packet within a pixel sequence, e.g., a single pixel may be spread across four packets, and the sequence number identifies which of those four packets the current packet is. The payload of the pixel data packet contains some or all of the data associated with a particular pixel.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Mahan’s single sequence number in order to identify a single data element as suggested by Mahan.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Temam in view of Sideris as applied above, and further in view of U.S. Patent Application Publication 20140180985 by Alvarez-Icaza et al. ("Alvarez-Icaza").
In regard to claim 10, Temam does not expressly disclose:
10. The processing core of claim 1, wherein: the first metadata is stored in association with the first set of data elements; the first metadata is stored in a separate data structure from the first set of data elements; and the first metadata is independently accessible from the first set of data elements. However, this is taught by Alvarez-Icaza. See Figs. 8-9 and ¶ 0068, “The neuronal state information for a neuron may further include neuron parameters and additional metadata about the system, such as a leak rate Lk and synaptic weights for different types of synaptic connections (e.g., Syn0, Syn1, Syn2, Syn3).” Also ¶ 0086, “The memory device 120 is organized into multiple entries 121. Each entry 121 maintains neuronal state information for a corresponding neuron.”
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the memory organization of Alvarez-Icaza with Temam’s data in order to access data regarding multiple entities as suggested by Alvarez-Icaza (see ¶ 0086).
Claim(s) 17 and 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Temam in view of Sideris as applied above, and further in view of U.S. Patent Application Publication 20110016071 by Guillen et al. ("Guillen").
In regard to claim 17, Temam does not expressly disclose:
17. The processing core of claim 1, wherein: the prior execution is an entirely separate execution of the directed graph. However, this is taught by Guillen. See ¶ 0045, “The contents of the look-up tables for the various sector types may be pre-calculated using genetic or evolutive programming and/or determined through experimentation.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Guillen’s pre-calculated look-up table with Temam’s tiles in order to provide high computational efficiency as suggested by Guillen (see ¶ 0045).
In regard to claim 22, Temam does not expressly disclose:
22. The processing core of claim 1, wherein: the first metadata is generated, during the prior execution of the directed graph, by an additional routine that executes while the directed graph is executed. However, this is taught by Guillen. See ¶ 0045, “The contents of the look-up tables for the various sector types may be pre-calculated using genetic or evolutive programming and/or determined through experimentation.” It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use Guillen’s pre-calculated look-up table with Temam’s tiles in order to provide high computational efficiency as suggested by Guillen (see ¶ 0045).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James D Rutten whose telephone number is (571)272-3703. The examiner can normally be reached M-F 9:00-5:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Li B Zhen can be reached at (571)272-3768. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/James D. Rutten/Primary Examiner, Art Unit 2121
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