Detailed Action
This is a Non-final Office action in response to communications received on 6/27/2024. Claims 1-25 are pending and are examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings, filed 6/27/2024 are acknowledged.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-14 and 24 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Under 35 U.S.C. 101, a claimed invention must fall within one of the four eligible categories of invention (i.e. process, machine, manufacture, or composition of matter) and must not be directed to subject matter encompassing a judicially recognized exception as interpreted by the courts. MPEP § 2106. The four eligible categories of invention include: (1) process which is an act, or a series of acts or steps, (2) machine which is an concrete thing, consisting of parts, or of certain devices and combination of devices, (3) manufacture which is an article produced from raw or prepared materials by giving to these materials new forms, qualities, properties, or combinations, whether by hand labor or by machinery, and (4) composition of matter which is all compositions of two or more substances and all composite articles, whether they be the results of chemical union, or of mechanical mixture, or whether they be gases, fluids, powders or solids. MPEP 2106(I).
Claim 1 recites “A computer program product comprising: a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer-readable storage media”. Claim 24 recites similarly deficient limitations. Notably absent from Applicant’s Specification is any definition of the computer readable medium that explicitly limits it to hardware. The broadest reasonable interpretation of a claim drawn to a recording medium (also called machine readable medium and other such variations) which typically covers forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of recording medium, particularly when the specification is silent (See MPEP 2111.01). When the broadest reasonable interpretation of a claim covers a signal per se, the claim must be rejected under 35 U.S.C. §1 01 as covering non-statutory subject matter. See In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007) (transitory embodiments are not directed to statutory subject matter) and Interim Examination Instructions for Evaluating Subject Matter Eligibility under 35 U.S.C. § 101, Aug. 24, 2009; p. 2.
A claim drawn to such a recording medium that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C. § 101 by adding the limitation "non-transitory" to the claim. Cf Animals - Patentability, 1077 Off. Gaz. Pat. Office 24 (April 21, 1987). Claims 2-14 inherit the deficiencies of claim 1 and are therefore similarly rejected as covering non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 8, 15-17, 19-21 and 23-25 are rejected under 35 U.S.C. 103 as being unpatentable over Greiner (US 20090182988 A1), in view of Giamei (US 20200142705 A1).
Regarding claim 1, Greiner teaches the limitations of claim 1 substantially as follows:
A computer program product comprising: a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer- readable storage media, for causing at least one computing device to perform computer operations including: (Greiner; [0035]: the program code may be embodied in the memory, and accessed by the processor using the processor bus)
executing an instruction to perform cryptographic processing, the executing the instruction including: (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., cryptographic processing))
performing a plurality of operations of the instruction to generate a cryptographic result; (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., plurality of operations of the instruction ))
detecting, based on performing at least multiple operations of the plurality of operations, an access exception condition for a storage location used by an instrumentation counter, (Greiner; [0123], [0125]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated (i.e., detecting, based on performing at least multiple operations of the plurality of operations). An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition (i.e., access exception condition for a storage location); For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., instrumentation counter))
the instrumentation counter to be used to indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result; and (Greiner; [0125]: For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result))
interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition; and (Greiner; [0123]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated. An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition, but a branch instruction or an interruption changes the instruction sequence such that the instruction is not executed (i.e., interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition))
Greiner does not teach the limitations of claim 1 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated.
However, in the same field of endeavor, Giamei discloses the limitations of claim 1 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated))
Giamei is combinable with Greiner because all are from the same field of endeavor of program control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Greiner to incorporate resumption of code execution after disruption as in Giamei in order to improve the efficiency of the system by being able to recover upon disruption (Giamei; [0004]).
Regarding claim 2, Greiner and Giamei teach the limitations of claim 1.
Greiner and Giamei teach the limitations of claim 2 as follows:
The computer program product of claim 1, wherein the cryptographic result is a message authentication code. (Greiner; [0128]: Execution of CIPHER MESSAGE, CIPHER MESSAGE WITH CHAINING, COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE is attempted)
Regarding claim 3, Greiner and Giamei teach the limitations of claim 1.
Greiner and Giamei teach the limitations of claim 3 as follows:
The computer program product of claim 1, wherein the storage location used by the instrumentation counter is owned by a control program. (Greiner; [0054]: Preferably addresses that an application program "sees" are often referred to as virtual addresses. Virtual addresses are sometimes referred to as "logical addresses" and "effective addresses" (i.e., the storage location used by the instrumentation counter is owned by a control program). These virtual addresses are virtual in that they are redirected to physical memory location by one of a variety of Dynamic Address Translation (DAT) 312 technologies)
Regarding claim 4, Greiner and Giamei teach the limitations of claim 1.
Greiner and Giamei teach the limitations of claim 4 as follows:
The computer program product of claim 1, wherein the updating the instrumentation counter is performed absent re-execution of the at least multiple operations. (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., the updating the instrumentation counter is performed absent re-execution of the at least multiple operations)
The same motivation to combine Giamei as in claim 1 is applicable to the instant claim.
Regarding claim 5, Greiner and Giamei teach the limitations of claim 1.
Greiner and Giamei teach the limitations of claim 5 as follows:
The computer program product of claim 1, wherein the executing the instruction further includes setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted))
The same motivation to combine Giamei as in claim 1 is applicable to the instant claim.
Regarding claim 8, Greiner and Giamei teach the limitations of claim 5.
Greiner and Giamei teach the limitations of claim 8 as follows:
The computer program product of claim 5, wherein the executing the instruction includes setting the indicator to another selected value at initial execution of the instruction. (Giamei; [0120]: When the continuation flag (CF), described below, is one, the MVN is an input to the operation. When CF is one and the MVN identifies the same model as the model currently executing the instruction, data from the continuation state buffer (CSB), described below, may be used to resume the operation. When CF is one and the MVN identifies a different model than the model currently executing the instruction, part, or all of the CSB field may be ignored; The program is to initialize the continuation flag (CF) to zero (i.e., setting the indicator to another selected value at initial execution of the instruction))
The same motivation to combine Giamei as in claim 1 is applicable to the instant claim.
Regarding claim 15, Greiner teaches the limitations of claim 15 substantially as follows:
A computer system comprising: at least one computing device; a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer-readable storage media, for causing the at least one computing device to perform computer operations including: (Greiner; [0035]: the program code may be embodied in the memory, and accessed by the processor using the processor bus)
executing an instruction to perform cryptographic processing, the executing the instruction including: (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., cryptographic processing))
performing a plurality of operations of the instruction to generate a cryptographic result; (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., plurality of operations of the instruction ))
detecting, based on performing at least multiple operations of the plurality of operations, an access exception condition for a storage location used by an instrumentation counter, (Greiner; [0123], [0125]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated (i.e., detecting, based on performing at least multiple operations of the plurality of operations). An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition (i.e., access exception condition for a storage location); For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., instrumentation counter))
the instrumentation counter to be used to indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result; and (Greiner; [0125]: For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result))
interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition; and (Greiner; [0123]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated. An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition, but a branch instruction or an interruption changes the instruction sequence such that the instruction is not executed (i.e., interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition))
Greiner does not teach the limitations of claim 15 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated.
However, in the same field of endeavor, Giamei discloses the limitations of claim 15 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated))
Giamei is combinable with Greiner because all are from the same field of endeavor of program control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Greiner to incorporate resumption of code execution after disruption as in Giamei in order to improve the efficiency of the system by being able to recover upon disruption (Giamei; [0004]).
Regarding claim 16, Greiner and Giamei teach the limitations of claim 15.
Greiner and Giamei teach the limitations of claim 16 as follows:
The computer system of claim 15, wherein the updating the instrumentation counter is performed absent re-execution of the at least multiple operations. (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., the updating the instrumentation counter is performed absent re-execution of the at least multiple operations)
The same motivation to combine Giamei as in claim 15 is applicable to the instant claim.
Regarding claim 17, Greiner and Giamei teach the limitations of claim 15.
Greiner and Giamei teach the limitations of claim 17 as follows:
The computer system of claim 15, wherein the executing the instruction further includes setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted))
The same motivation to combine Giamei as in claim 15 is applicable to the instant claim.
Regarding claim 19, Greiner teaches the limitations of claim 19 substantially as follows:
A computer-implemented method comprising:
executing an instruction to perform cryptographic processing, the executing the instruction including: (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., cryptographic processing))
performing a plurality of operations of the instruction to generate a cryptographic result; (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., plurality of operations of the instruction ))
detecting, based on performing at least multiple operations of the plurality of operations, an access exception condition for a storage location used by an instrumentation counter, (Greiner; [0123], [0125]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated (i.e., detecting, based on performing at least multiple operations of the plurality of operations). An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition (i.e., access exception condition for a storage location); For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., instrumentation counter))
the instrumentation counter to be used to indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result; and (Greiner; [0125]: For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., indicate that a particular cryptographic function has been used by the plurality of operations to generate the cryptographic result))
interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition; and (Greiner; [0123]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated. An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition, but a branch instruction or an interruption changes the instruction sequence such that the instruction is not executed (i.e., interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition))
Greiner does not teach the limitations of claim 19 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated.
However, in the same field of endeavor, Giamei discloses the limitations of claim 19 as follows:
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter, based on the storage location used by the instrumentation counter being validated))
Giamei is combinable with Greiner because all are from the same field of endeavor of program control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Greiner to incorporate resumption of code execution after disruption as in Giamei in order to improve the efficiency of the system by being able to recover upon disruption (Giamei; [0004]).
Regarding claim 20, Greiner and Giamei teach the limitations of claim 19.
Greiner and Giamei teach the limitations of claim 20 as follows:
The computer-implemented method of claim 19, wherein the updating the instrumentation counter is performed absent re-execution of the at least multiple operations. (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., the updating the instrumentation counter is performed absent re-execution of the at least multiple operations)
The same motivation to combine Giamei as in claim 19 is applicable to the instant claim.
Regarding claim 21, Greiner and Giamei teach the limitations of claim 19.
Greiner and Giamei teach the limitations of claim 21 as follows:
The computer-implemented method of claim 19, wherein the executing the instruction further includes setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., setting an indicator to a selected value, based on detecting the access exception condition, and wherein the re-executing the instruction includes checking the indicator to determine where execution was interrupted))
The same motivation to combine Giamei as in claim 19 is applicable to the instant claim.
Regarding claim 23, Greiner and Giamei teach the limitations of claim 21.
Greiner and Giamei teach the limitations of claim 23 as follows:
The computer-implemented method of claim 21, wherein based on the indicator being set to the selected value and re-executing the instruction, the plurality of operations includes checking accessibility of the instrumentation counter and performing the updating of the instrumentation counter based on the instrumentation counter being accessible. (Giamei; [0120]: When the continuation flag (CF), described below, is one, the MVN is an input to the operation. When CF is one and the MVN identifies the same model as the model currently executing the instruction, data from the continuation state buffer (CSB), described below, may be used to resume the operation. When CF is one and the MVN identifies a different model than the model currently executing the instruction, part, or all of the CSB field may be ignored; The program is to initialize the continuation flag (CF) to zero (i.e., checking accessibility of the instrumentation counter and performing the updating of the instrumentation counter based on the instrumentation counter being accessible))
The same motivation to combine Giamei as in claim 19 is applicable to the instant claim.
Regarding claim 24, Greiner teaches the limitations of claim 24 substantially as follows:
A computer program product comprising: a set of one or more computer-readable storage media; and program instructions, collectively stored in the set of one or more computer- readable storage media, for causing at least one computing device to perform computer operations including: (Greiner; [0035]: the program code may be embodied in the memory, and accessed by the processor using the processor bus)
executing an instruction to perform hash-based message authentication code processing, the instruction including an indicator and the executing the instruction including: (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., hash-based message authentication code processing))
performing a plurality of operations of the instruction to generate a hash-based message authentication code; (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., generate a hash-based message authentication code))
detecting, based on performing the plurality of operations, an access exception condition for a storage location used by an instrumentation counter, the instrumentation counter to be accessed by the instruction; (Greiner; [0123], [0125]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated (i.e., detecting, based on performing at least multiple operations of the plurality of operations). An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition (i.e., access exception condition for a storage location); For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., instrumentation counter))
interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition; and (Greiner; [0123]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated. An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition, but a branch instruction or an interruption changes the instruction sequence such that the instruction is not executed (i.e., interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition))
Greiner does not teach the limitations of claim 24 as follows:
setting the indicator to a selected value based on detecting the access exception condition; and
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted as indicated by the indicator set to the selected value and including updating the instrumentation counter.
However, in the same field of endeavor, Giamei discloses the limitations of claim 24 as follows:
setting the indicator to a selected value based on detecting the access exception condition; and (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., setting an indicator to a selected value, based on detecting the access exception condition))
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted as indicated by the indicator set to the selected value and including updating the instrumentation counter. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter))
Giamei is combinable with Greiner because all are from the same field of endeavor of program control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Greiner to incorporate resumption of code execution after disruption as in Giamei in order to improve the efficiency of the system by being able to recover upon disruption (Giamei; [0004]).
Regarding claim 25, Greiner teaches the limitations of claim 25 substantially as follows:
A computer-implemented method comprising:
executing an instruction to perform hash-based message authentication code processing, the instruction including an indicator and the executing the instruction including: (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., hash-based message authentication code processing))
performing a plurality of operations of the instruction to generate a hash-based message authentication code; (Greiner; [0133]: Execution of COMPUTE INTERMEDIATE MESSAGE DIGEST, COMPUTE LAST MESSAGE DIGEST, or COMPUTE MESSAGE AUTHENTICATION CODE (i.e., generate a hash-based message authentication code))
detecting, based on performing the plurality of operations, an access exception condition for a storage location used by an instrumentation counter, the instrumentation counter to be accessed by the instruction; (Greiner; [0123], [0125]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated (i.e., detecting, based on performing at least multiple operations of the plurality of operations). An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition (i.e., access exception condition for a storage location); For a store-type operand, access exceptions are recognized for the entire operand even if the operation could be completed without the use of the inaccessible part of the operand. In situations where the value of a store-type operand is defined to be unpredictable, it is unpredictable whether an access exception is indicated. Whenever an access to an operand location can cause an access exception to be recognized, the word "access" is included in the list of program exceptions in the description of the instruction. This entry also indicates which operand can cause the exception to be recognized and whether the exception is recognized on a fetch or store access to that operand location. Access exceptions are recognized only for the portion of the operand as defined for each particular instruction (i.e., instrumentation counter))
interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition; and (Greiner; [0123]: Any access exception is recognized as part of the execution of the instruction with which the exception is associated. An access exception is not recognized when the CPU attempts to prefetch from an unavailable location or detects some other access-exception condition, but a branch instruction or an interruption changes the instruction sequence such that the instruction is not executed (i.e., interrupting execution of the instruction indicating incomplete processing, based on detecting the access exception condition))
Greiner does not teach the limitations of claim 25 as follows:
setting the indicator to a selected value based on detecting the access exception condition; and
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted as indicated by the indicator set to the selected value and including updating the instrumentation counter.
However, in the same field of endeavor, Giamei discloses the limitations of claim 25 as follows:
setting the indicator to a selected value based on detecting the access exception condition; and (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., setting an indicator to a selected value, based on detecting the access exception condition))
re-executing the instruction to obtain access to the instrumentation counter, the re-executing the instruction starting from where execution was interrupted as indicated by the indicator set to the selected value and including updating the instrumentation counter. (Giamei; [0222]: When the operation ends with partial completion, internal state data, which may include a history of prior comparisons between records, is stored to the continuation state buffer (CSB) field of the parameter block. Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., re-executing the instruction starting from where execution was interrupted and including updating the instrumentation counter))
Giamei is combinable with Greiner because all are from the same field of endeavor of program control. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the system of Greiner to incorporate resumption of code execution after disruption as in Giamei in order to improve the efficiency of the system by being able to recover upon disruption (Giamei; [0004]).
Claims 6, 7, 18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Greiner (US 20090182988 A1), in view of Giamei (US 20200142705 A1), as applied to independent claims, further in view of Kim (US 20100031052 A1).
Regarding claim 6, Greiner and Giamei teach the limitations of claim 5.
Greiner and Giamei teach the limitations of claim 6 as follows:
The computer program product of claim 5, wherein based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed, (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed)
The same motivation to combine Giamei as in claim 1 is applicable to the instant claim.
Greiner and Giamei do not teach the limitations of claim 6 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation.
However, in the same field of endeavor, Kim discloses the limitations of claim 6 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation. (Kim; [0017]: there is provided a low power HMAC encryption apparatus using a low power SHA-1 hash algorithm, the apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector)
Kim is combinable with Greiner and Giamei because all are from the same field of endeavor of transmission of digital information. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified system of Greiner and Giamei to incorporate a variety of potential hashing operations as in Kim in order to expand the functionality of the system to explicitly handle multiple variations of hash algorithms.
Regarding claim 7, Greiner and Giamei teach the limitations of claim 6.
Greiner and Giamei teach the limitations of claim 7 as follows:
The computer program product of claim 6, wherein based on the indicator being set to the selected value and re-executing the instruction, the plurality of operations includes checking accessibility of the instrumentation counter and performing the updating of the instrumentation counter based on the instrumentation counter being accessible. (Giamei; [0120]: When the continuation flag (CF), described below, is one, the MVN is an input to the operation. When CF is one and the MVN identifies the same model as the model currently executing the instruction, data from the continuation state buffer (CSB), described below, may be used to resume the operation. When CF is one and the MVN identifies a different model than the model currently executing the instruction, part, or all of the CSB field may be ignored; The program is to initialize the continuation flag (CF) to zero (i.e., checking accessibility of the instrumentation counter and performing the updating of the instrumentation counter based on the instrumentation counter being accessible))
Regarding claim 18, Greiner and Giamei teach the limitations of claim 17.
Greiner and Giamei teach the limitations of claim 18 as follows:
The computer system of claim 17, wherein based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed, (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed)
The same motivation to combine Giamei as in claim 15 is applicable to the instant claim.
Greiner and Giamei do not teach the limitations of claim 18 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation.
However, in the same field of endeavor, Kim discloses the limitations of claim 18 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation. (Kim; [0017]: there is provided a low power HMAC encryption apparatus using a low power SHA-1 hash algorithm, the apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector)
Kim is combinable with Greiner and Giamei because all are from the same field of endeavor of transmission of digital information. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified system of Greiner and Giamei to incorporate a variety of potential hashing operations as in Kim in order to expand the functionality of the system to explicitly handle multiple variations of hash algorithms.
Regarding claim 22, Greiner and Giamei teach the limitations of claim 21.
Greiner and Giamei teach the limitations of claim 22 as follows:
The computer-implemented method of claim 21, wherein based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed, (Giamei; [0222]: Subsequently, when the instruction is re-executed, for the purpose of resuming the operation, the contents of the CSB may be loaded into the implementation and the history may be referenced when the operation resumes (i.e., based on the indicator being set to the selected value and re-executing the instruction, processing of the at least multiple operations is bypassed)
The same motivation to combine Giamei as in claim 19 is applicable to the instant claim.
Greiner and Giamei do not teach the limitations of claim 22 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation.
However, in the same field of endeavor, Kim discloses the limitations of claim 22 as follows:
the at least multiple operations including an input message padding and hashing operation, an outer-key padding and hashing operation and an output message padding and hashing operation. (Kim; [0017]: there is provided a low power HMAC encryption apparatus using a low power SHA-1 hash algorithm, the apparatus including: a key padder padding key data for HMAC algorithm; an XOR operator XOR operating the padded key data and a padding constant; a data connector connecting a text to be encrypted, to data obtained by the XOR operating; a data padder padding the connected data; an SHA-1 hash algorithm part performing an SHA-1 hash algorithm on the padded data; a data selector selecting and applying one of a result of the SHA-1 hash algorithm and the text to be encrypted, to the data connector)
Kim is combinable with Greiner and Giamei because all are from the same field of endeavor of transmission of digital information. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified system of Greiner and Giamei to incorporate a variety of potential hashing operations as in Kim in order to expand the functionality of the system to explicitly handle multiple variations of hash algorithms.
Allowable Subject Matter
Claims 9-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 9, it contains allowable subject matter when the claim is taken as a whole. See the italicized text indicating aspects that in combination with the remainder of the claim differentiate it from prior art.
The computer program product of claim 1, wherein the performing the plurality of operations includes: performing a sequence of hash operations on a message obtained using the instruction to generate an intermediate message digest, the performing the sequence of hash operations using an output chaining value generated based on performing an inner-key padding and hashing operation using a cryptographic key of the instruction; and performing an outer-key padding and hashing operation using the cryptographic key to generate another output chaining value to be used in generating a final output message digest based on a final input message digest produced using the intermediate message digest, the final output message digest being a resulting authentication code, the resulting authentication code being the cryptographic result.
Furthermore, claims 10-14 contain allowable subject matter based on the virtue of dependency from claim 9.
Prior Art Considered But Not Relied Upon
Weiler (US 20210218547 A1) which teaches a MAC in which a hash or sum of the other fields in the encrypted slice of the pointer may be generated (e.g., the version and Max RSP fields). The same calculation is performed when decorating and decrypted the pointer. If the MAC does not match when decrypting the pointer, then this pointer must have been altered and should be deemed invalid.
Gopal (US 10313129 B2) which teaches a decode unit to decode a keyed-hash message authentication code instruction.
Conclusion
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/BLAKE I NARRAMORE/Examiner, Art Unit 2438