DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
The terminal disclaimer filed on February 02, 2026 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US Patent No. 12/108,652 B2, has been reviewed and is accepted. The terminal disclaimer has been recorded.
Double Patenting
Examiner acknowledges the Terminal Disclaimer filed on February 02, 2026. The Double Patenting rejections in the previous Office Action filed on October 01, 2025 are hereby withdrawn.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 12, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US PG-Pub No.: 2016/0189593, hereinafter, “Lee”), prior art of record.
Regarding claim 1, Lee discloses a display device (see Lee, FIG. 9A) comprising:
a pixel electrode (111a+111b+105b, FIG. 9A) including a first subpixel electrode (111a) and a second subpixel electrode (111b+105b) that are spaced apart from each other within at least one subpixel of a plurality of subpixels over a substrate (101, FIG. 9A);
a driving transistor (DT_W2, FIG. 9A) driving the at least one subpixel (OLED_W2 and OLED_W1, FIG. 9A); and
a connection electrode structure (RHL+B1+B2, FIG. 9A) disposed between the first subpixel electrode (111a) and the second subpixel electrode (111b+105b),
wherein the connection electrode structure (RHL+B1+B2) connects at least one of the first subpixel electrode (111a) and the second subpixel electrode (111b+105b) of the pixel electrode with the driving transistor (DT_W2, FIG. 9A),
wherein the first subpixel electrode (111a) and the second subpixel electrode (111b+105b) are electrically connected to one driving transistor (DT_W2, FIG. 9A), and
wherein the first subpixel electrode (111a) and the second subpixel electrode (partial 111b+105b) are disposed in a same subpixel.
Regarding claim 2, Lee discloses the display device of claim 1, further comprising a bank (117, FIG. 9A) covering the connection electrode structure (partially covering RHL+B1+B2, FIG. 9A).
Regarding claim 3, Lee discloses the display device of claim 1, wherein the connection electrode structure (RHL+B1+B2) is disposed on the same layer as the pixel electrode (111a+11b lower part, FIG. 9A).
Regarding claim 4, Lee discloses the display device of claim 1, wherein the connection electrode structure (RHL+B1+B2) includes a common connection electrode (RHL) electrically connected with at least one of the first subpixel electrode (111a) and the second subpixel electrode (111b+105b, FIG. 9A).
Regarding claim 5, Lee discloses the display device of claim 4, wherein the common connection electrode (RHL) is arranged over a same layer (101) as an active layer (102b, FIG. 9A) constituting the driving transistor (DT_W2).
Regarding claim 12, Lee discloses the display device of claim 1, wherein at least one of the first subpixel electrode (111a) and the second subpixel electrode (111b+105b) is partially arranged over the driving transistor (DT_W2; Lee, FIG. 9A).
Regarding claim 17, Lee discloses the display device of claim 1, further comprising a transmissive area (area without OLED and DT, FIG. 9A) transmitting external light of the substrate (101).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US PG-Pub No.: 2016/0189593, hereinafter, “Lee”), prior art of record, as applied to claim 4 above, in view of Chae (US PG-Pub No.: 2019/0131355 A1, hereinafter, “Chae”), prior art of record.
Regarding claim 6, Lee discloses the display device of claim 4, wherein the connection electrode structure (RHL+B1+B2) includes a first connection electrode (B1), a second connection electrode (B2).
Lee is silent regarding a third connection electrode connected with the common connection electrode.
However, Lee discloses that the common connection electrode (RHL) is made of the same material as anode (¶ [¶ [0112]]) and it is well-known that an anode can be a multilayer. For example, Chae discloses a display device (see Chae, FIG. 3), wherein an anode (132, FIG. 3) comprises a multilayer (¶ [0041]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Lee’s anode and RHL with a multilayer structure, as taught by Chae, in order to improve the emission efficiency. Accordingly, one layer of RHL is the common connection electrode and another layer of RHL is the third connection electrode.
Regarding claim 7, Lee in view of Chae discloses the display device of claim 6, wherein the common connection electrode (one layer of RHL, see above regarding claim 6) has a first end contacted with the first connection electrode (B1) and a second end contacted with the second connection electrode (B2), is contacted with the third connection electrode (the other layer of RHL) between the first end and the second end (Lee, FIG. 9A).
Regarding claim 8, Lee in view of Chae discloses the display device of claim 6, wherein the common connection electrode (one layer of RHL) is arranged in a layer different from at least one of the first connection electrode (B1), the second connection electrode (B2; Lee, FIG. 9A) and the third connection electrodes.
Regarding claim 9, Lee in view of Chae discloses the display device of claim 6, wherein the first connection electrode (B1) extended from a first end of the first subpixel electrode (111a) to a first direction (up-down) which is perpendicular to a direction (left-right) from the first subpixel electrode (111a) to the second subpixel electrode (111b+105b; Lee, FIG. 9A).
Regarding claim 10, Lee in view of Chae discloses the display device of claim 6, wherein the second connection electrode (B2) extended from a first end of the second subpixel electrode (111b+105b) to a first direction (up-down) which is perpendicular to a direction (left-right) from the first subpixel electrode (111a) to the second subpixel electrode (111b+105b; Lee, FIG. 9A).
Regarding claim 11, Lee in view of Chae discloses the display device of claim 6, wherein the third connection electrode (the other layer of RHL) electrically connected to the driving transistor (DT_W2) and extended to a first direction (up-down; since RHL is a 3D object, it extends in all directions) which is perpendicular to a direction (left-right) from the first subpixel electrode (111a) to the second subpixel electrode (111b+105b; Lee, FIG. 9A).
Regarding claim 13, Lee in view of Chae discloses the display device of claim 9, wherein the common connection electrode (one layer of RHL) is arranged in a second direction (left-right) different from or orthogonal to the first direction (up-down), and connects the first connection electrode (B1) with the third connection electrode (the other layer of RHL) through a bridge or connects the second connection electrode (B2) with the third connection electrode (the other layer of RHL) through a bridge (Lee, FIG. 9A).
Allowable Subject Matter
Claims 14-16 are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 14, in particular, a buffer layer over the substrate; a first insulating film over the active layer or the common connection electrode over the buffer layer; and a second insulating film over the first insulating film, wherein at least one of the second connection electrode and the third connection electrode is connected with the common connection electrode through a contact hole of the first insulating film and the second insulating film, wherein a first end of the third connection electrode is contacted with a conductive layer extended from source electrode or drain electrode of the driving transistor, constituting one electrode of a capacitor in the at least one subpixel, wherein the third connection electrode connected with the driving transistor is arranged between the first subpixel electrode and the second subpixel electrode.
The prior art of record neither anticipates nor renders obvious all the claimed subject of claim 15, in particular, the at least one subpixel further includes: a data line arranged to overlap with at least a portion of the at least one subpixel in a direction from the first subpixel electrode to the second subpixel electrode; and a repair line arranged at one side of the at least one subpixel in a direction parallel with the data line, at least a portion of the repair line is arranged to overlap with at least a portion of the connection electrode structure or cross the connection electrode structure, wherein the repair line is extended in a direction of an adjacent subpixel adjacent to the at least one subpixel in a direction of the data line. Claim 16 depends upon claim 15.
Response to Arguments
Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection with new mapping does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIA L CROSS/Primary Examiner, Art Unit 2892