DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Compact Prosecution
With respect to Claim Interpretation, the Examiner has provided some notes regarding “[BRI on the record]” throughout the Office Action, so that the record is clear about the scope of the claimed invention, and the record is also clear about the basis for the Examiner’s analyses. A clear record of the claim interpretation could expedite the examination by creating the condition to allow the examination to focus on Applicant’s inventive concept and its comparison with related prior art.
If there are disagreements, Applicant may present an alternative interpretation based on MPEP 2111. The Examiner will adopt Applicant’s interpretation on the record, if Applicant’s interpretation is reasonable and/or arguments are persuasive.
Applicant may amend claims relying on the Examiner’s claim interpretation provided on the record.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “independent display frame interpolation circuit,” and “independent display chip.” The meaning of the term “independent” is unclear, because (a) the specification’s particular usage of the term creates confusions, and (b) it is unclear as to the nature of the independence or from whom the “circuit” or “chip” is independent from.
(a) The specification uses “independent” more than 200 times. For example, the specification states, “independent display frame interpolation method” and “independent display frame interpolation function.” Spec. ¶¶ 14, 18. What is an “independent” method/function/circuit? What is a “dependent” method/function/circuit/chip? The confusing usage of the term “independent” does not provide guidance to the interpretation of the term.
Claim 1 recites “comprises a System-on-a-Chip and an independent display chip.” Is the “System-on-a-Chip” dependent or independent? What is an independent “System-on-a-Chip”? What is a dependent “System-on-a-Chip”?
(b) For example, a person could be financially independent or emotionally independent. It is unclear from the specification what the nature of the independence is with respect to the claimed “circuit” or “chip.” It is also unclear as to from whom the “circuit” or “chip” is independent from.
All independent claims recites “independent” and have a similar deficiency. All dependent claims inherit the deficiency. All these claims are rejected.
Claim 18 recites the limitation "the System-on-a-Chip" and “the electronic device,” and their antecedent basis is unclear.
Claim 18 recites and claims “An electronic device” and “the System-on-a-Chip” in the preamble. However, the claim also recites “a System-on-a-Chip” (lines 5-6) and “an electronic device” (line 6). The claim later recites “the System-on-a-Chip” (line 6, 7) and “the electronic device” (line 8). It is unclear which “System-on-a-Chip” or which “electronic device” they refer to.
Claims 19-20 depend on Claim 18 and inherit the deficiency. They are also rejected.
Claim Objection
Claims 1, 6-7, 9, 11-13 are objected to because of the following informalities: they recite “in a case.” The Examiner requests clarification on the interpretation of the term: whether they make the corresponding limitations optional, particularly the method claims, in view of MPEP 2111.04.II with respect to contingent limitations and Ex parte Schulhauser. The Examiner recommends amending them to be “in response to.”
Claims 1, 5-6, 13, and 16 are objected to because of the following informalities: they recite “. . . signal … is received, . . . ,” but it is unclear within the context the claim what received the signal. Some may argue any signal is always received by something, e.g., air or wire. Appropriate clarification or explanation is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-8, 11-14, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng et al. (CN 110996170 A) in view of Youn et al. (US 20230030201 A1).
Regarding Claim 1, Zheng teaches An independent display frame interpolation circuit (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
The display frame interpolation circuit is mapped to the circuit that includes the “frame-inserting chip,” because the disclosed frame insertion is based on “performing the frame interpolation process” according to Zheng.),
wherein the independent display frame interpolation circuit comprises a chip system Zheng’s system, including CPU+GPU) and an independent display chip (Zheng’s “frame-inserting chip”) (
[BRI on the record]
With respect to “independent display chip,” the Examiner had rejected the claim due to the term “independent” under 112(b). The Examiner requests clarification from Applicant regarding the interpretation and scope of the term as already explained. Here, the Examiner is reading the recited “independent” as separate. Therefore, the recited “independent display chip” is read as a “display chip” that is separate from the recited “System-on-a-Chip.”
[Mapping Analysis]
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, . . . ; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, . . ..” Zheng Abstract.),
wherein the chip system Zheng’s system, including CPU+GPU) is configured to:
generate first data (Zheng’s “third video file”) based on first content (Zheng’s “first video file”) to be displayed, and send the first data (Zheng’s “third video file”) to the independent display chip (Zheng’s “frame-inserting chip”) (Zheng’s “third video file”) is smaller than a frame rate of the first content (Zheng’s “first video file”) (
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.
Frame rate of the first data (“third video file”) is equal to “second video file,” which is “less [/smaller] than a frame rate of the first video [(first content)]”); and
the independent display chip (Zheng’s “frame-inserting chip”) is configured to perform frame interpolation processing on the first data (Zheng’s “third video file”) to obtain second data (Zheng’s “fourth video file”), and a frame rate of the second data (Zheng’s “fourth video file”) is greater than or equal to the frame rate of the first content (Zheng’s “first video file”) (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
“wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.).
Zheng does not explicitly disclose the chip system is a System-on-a-Chip; or synchronizing in a case that a target display frame rate synchronization (TE) signal sent by the independent display chip is received.
Youn teaches
the chip system could be a System-on-a-Chip (“In the illustrated embodiment, the components of the frame generation subsystem 102 are implemented together in a host system-on-a-chip (SoC) 128 while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130.” Youn ¶ 21.); and
synchronizing in a case that a target display frame rate synchronization (TE) signal sent by the independent display chip is received (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display panel and a frame renderer on a SOC, and their functionalities to synchronize frames are similar as well.
Fig. 1 shows that (TE) signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128).
Youn teaches synchronization based on TE to a target frame rate as determined by (DDIC 130/frame-inserting chip).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the corresponding visual effect displayed is consistent and pleasing. “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer.” Youn ¶ 4.
Regarding Claim 2, Zheng in view of Youn teaches The circuit according to claim 1,
wherein the System-on-a-Chip (Youn ¶ 21) is specifically configured to perform frame loss processing on the first content (Zheng’s “first video file”) based on a preset frame rate (“12fps” in Zheng’s example), to obtain first data (Zheng’s “third video file”) at the preset frame rate (“12fps”) (
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. 6.
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, . . ..” Zheng Abstract.
The frame loss processing is mapped to disclosed “reducing frame processing.”).
Regarding Claim 5, Zheng in view of Youn teaches The circuit according to claim 1, wherein the target TE signal comprises a plurality of TE signals ( Youn:
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Note the target TE signals have multiple TE signals 514, 522, 528, and 534.); and
the System-on-a-Chip (Youn fig. 1 (SoC) 128) is specifically configured to send one frame of data (Youn fig. 1 131) in the first data to the independent display chip (Youn fig. 1 DDIC 130) every time when one TE signal is received (e.g., Youn fig. 1 shows that frame N-1 is received after TE 522), so as to send a plurality of frames of data (Youn fig. 1 N-2, N-1, N, N+1) in the first data to the independent display chip (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Youn Fig. 1 shows that TE signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128)/SYS (CPU+GPU).
Here, a frame of Zheng’s rendered third video file, first data, is transmitted to (DDIC 130/frame-inserting chip) when assertion of TE signal is received, without which the transmission would be delayed. Youn Fig. 5 shows multiples frames N-1, N, N+1, N+2 are generated and sent to (DDIC 130/frame-inserting chip) (Youn Fig. 1).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 6, Zheng in view of Youn teaches The circuit according to claim 1, wherein the independent display frame interpolation circuit (including DDIC 130/frame-inserting chip) further comprises a display unit (Youn fig. 1 120 + 106);
the independent display chip (DDIC 130/frame-inserting chip) is further configured to send the second data (Youn fig. 1 showing frame data that go into Youn fig. 1 120; “the frame data 131 of the frame 132”) to the display unit (Youn fig. 1 120 +106) in a case that a first TE signal sent by the display unit is received, and a frequency value of the first TE signal is greater than or equal to a value of the frame rate of the second data (
“The timing controller 122 uses timing signaling and other control signaling 140 to control the pixel driver 120 to drive the display panel 106 to display a frame 132 from the GRAM 118 by scanning the frame data 131 of the frame 132 from the GRAM 118 into the pixel array (not shown) of the display panel 106 with row-line addressing, with the transfer of the pixel data from the pixel driver 120 to the display panel 106 represented by a SCAN signal 142.” Youn ¶ 24.
Note Youn fig. 1 120 “Pixel Driver” is part of DDIC 130 as shown in Youn fig. 1. According to MPEP 2144.04.V “MAKING PORTABLE, INTEGRAL, SEPARABLE, ADJUSTABLE, OR CONTINUOUS”, it would have been obvious to make fig. 1 120 “Pixel Driver” as an integral part of or separable part from DDIC 130.
Youn fig. 1 shows that the control signaling 140 could be sent from Youn fig. 1 120 and received by fig. 1 122. The control signaling 140 effect the target frame rate, which is mapped to the frame rate of the second data.
“. . . the timing controller 122 employs a discrete VRR scheme 144 that provides for the implementation of frame rates that permit alignment and synchronization of the corresponding frame periods to the PWM cycles of the EM signal 138 such that each frame period is aligned to a PWM cycle and spans only a PWM cycles in their entireties, and thus allows changes in the frame rate to accommodate a delayed rendering of a frame to avoid distortion of the effective duty cycle for that frame or frames preceding or following it.” Youn ¶ 26.
Youn teaching determining a target frame rate based on display characteristics, stating “As one example, the maximum frame rate F.sub.H could be set to the maximum display frame rate supported by the display panel 106 or the software application 110 (e.g., 120 frames-per-second (fps)) while the minimum frame rate F.sub.L could be set to the lowest frame rate deemed to provide a viewing experience of minimum sufficient quality (e.g., 30 fps). The target frame rate F.sub.C represents a target frame rate between the minimum and maximum frame rates (that is, F.sub.L<=F.sub.C<=F.sub.H) and is selected based on one or more considerations, including user preferences or settings, current rendering bandwidth capacity, and the like.” Youn ¶ 31.
Youn does not explicitly disclose that the control signaling 140 is the claimed first TE signal.
However, Youn teaches TE signal as control signal in a different context, stating “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Youn’s control signaling 140. One of ordinary skill in the art would be motivated to synchronize the pixel driver with target frame rate. This would make the display panel display properly as intended.); and
the display unit (Youn Fig. 1 120) is configured to display second content based on the second data (“The timing controller 122 uses timing signaling and other control signaling 140 to control the pixel driver 120 to drive the display panel 106 to display a frame 132 from the GRAM 118 by scanning the frame data 131 of the frame 132 from the GRAM 118 into the pixel array (not shown) of the display panel 106 with row-line addressing, with the transfer of the pixel data from the pixel driver 120 to the display panel 106 represented by a SCAN signal 142.” Youn ¶ 24.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 7, Claim 7 is similar to Claim 1. Refer to Claim 1’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches An independent display frame interpolation method, applied to an electronic device (“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.), and comprising:
generating first data (Zheng’s “third video file”) based on first content (Zheng’s “first video file”) to be displayed on the electronic device through a System-on-a-Chip (Youn fig. 1 (SoC) 128) in the electronic device (Youn Fig. 1), wherein a frame rate of the first data (Zheng’s “third video file”) is smaller than a frame rate of the first content (Zheng’s “first video file”) (
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.
Frame rate of the first data (“third video file”) is equal to “second video file,” which is “less [/smaller] than a frame rate of the first video [(first content)]”);
in a case that the System-on-a-Chip receives a target display frame rate synchronization (TE) signal sent by an independent display chip in the electronic device, sending the first data to the independent display chip through the System-on-a-Chip (
“In the illustrated embodiment, the components of the frame generation subsystem 102 are implemented together in a host system-on-a-chip (SoC) 128 while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130.” Youn ¶ 21.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4. “At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23; see Fig. 1.
After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well. Fig. 1 shows that (TE) signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128).); and
performing frame interpolation processing on the first data through the independent display chip to obtain second data, wherein a frame rate of the second data is greater than or equal to the frame rate of the first content (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
“wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 8, Claim 8 is similar to Claim 2. Refer to Claim 2’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches The method according to claim 7, wherein
the generating first data based on first content to be displayed on the electronic device through a System-on-a-Chip (Youn fig. 1 (SoC) 128) in the electronic device (here, the claim references limitation from Claim 7) comprises: performing frame loss processing on the first content based on a preset frame rate through the System-on-a-Chip (Youn fig. 1 (SoC) 128), to obtain first data at the preset frame rate (
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. 6.
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, . . ..” Zheng Abstract.
The frame loss processing is mapped to disclosed “reducing frame processing.”).
Regarding Claim 11, Claim 11 is similar to Claim 5. Refer to Claim 5’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches The method according to claim 7, wherein the target TE signal comprises a plurality of TE signals (Youn Fig. 5 shows that the target TE signals have multiple TE signals 514, 522, 528, and 534.); and
in a case that the System-on-a-Chip (Youn fig. 1 (SoC) 128) receives a target TE signal sent by an independent display chip (DDIC 130/frame-inserting chip) in the electronic device (Youn Fig. 1 shows that (TE) signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128)),
the sending the first data to the independent display chip through the System-on-a-Chip (here, the claim references limitation from Claim 7; reference Claim 7 for the rejection analyses) comprises:
sending one frame of data in the first data to the independent display chip through the System-on-a-Chip every time when the System-on-a-Chip receives one TE signal, so as to send a plurality of frames of data in the first data to the independent display chip through the System-on-a-Chip (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Youn Fig. 1 shows that TE signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128)/SYS (CPU+GPU).
Here, a frame of Zheng’s rendered third video file, first data, is transmitted to (DDIC 130/frame-inserting chip) when assertion of TE signal is received, without which the transmission would be delayed.
Youn Fig. 5 shows multiples frames N-1, N, N+1, N+2 are generated and sent to (DDIC 130/frame-inserting chip) (Youn Fig. 1).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 12, Claim 12 is similar to Claim 6. Refer to Claim 6’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches The method according to claim 7,
wherein after the performing frame interpolation processing on the first data (Zheng’s “third video file”) through the independent display chip to obtain second data (Zheng’s “fourth video file”) (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5. “CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.), the method further comprises:
in a case that the independent display chip (DDIC 130/frame-inserting chip) receives a first TE signal sent by a display unit (Youn fig. 1 120 +106) in the electronic device, sending the second data to the display unit through the independent display chip, wherein a frequency value of the first TE signal is greater than or equal to a value of the frame rate of the second data (
“The timing controller 122 uses timing signaling and other control signaling 140 to control the pixel driver 120 to drive the display panel 106 to display a frame 132 from the GRAM 118 by scanning the frame data 131 of the frame 132 from the GRAM 118 into the pixel array (not shown) of the display panel 106 with row-line addressing, with the transfer of the pixel data from the pixel driver 120 to the display panel 106 represented by a SCAN signal 142.” Youn ¶ 24.
Note Youn fig. 1 120 “Pixel Driver” is part of DDIC 130 as shown in Youn fig. 1. According to MPEP 2144.04.V “MAKING PORTABLE, INTEGRAL, SEPARABLE, ADJUSTABLE, OR CONTINUOUS”, it would have been obvious to make fig. 1 120 “Pixel Driver” as an integral part of or separable part from DDIC 130.
Youn fig. 1 shows that the control signaling 140 could be sent from Youn fig. 1 120 and received by fig. 1 122. The control signaling 140 effect the target frame rate, which is mapped to the frame rate of the second data.
“. . . the timing controller 122 employs a discrete VRR scheme 144 that provides for the implementation of frame rates that permit alignment and synchronization of the corresponding frame periods to the PWM cycles of the EM signal 138 such that each frame period is aligned to a PWM cycle and spans only a PWM cycles in their entireties, and thus allows changes in the frame rate to accommodate a delayed rendering of a frame to avoid distortion of the effective duty cycle for that frame or frames preceding or following it.” Youn ¶ 26.
Youn teaching determining a target frame rate based on display characteristics, stating “As one example, the maximum frame rate F.sub.H could be set to the maximum display frame rate supported by the display panel 106 or the software application 110 (e.g., 120 frames-per-second (fps)) while the minimum frame rate F.sub.L could be set to the lowest frame rate deemed to provide a viewing experience of minimum sufficient quality (e.g., 30 fps). The target frame rate F.sub.C represents a target frame rate between the minimum and maximum frame rates (that is, F.sub.L<=F.sub.C<=F.sub.H) and is selected based on one or more considerations, including user preferences or settings, current rendering bandwidth capacity, and the like.” Youn ¶ 31.
Youn does not explicitly disclose that the control signaling 140 is the claimed first TE signal.
However, Youn teaches TE signal as control signal in a different context, stating “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Youn’s control signaling 140. One of ordinary skill in the art would be motivated to synchronize the pixel driver with target frame rate. This would make the display panel display properly as intended.); and
displaying second content based on the second data through the display unit (“The timing controller 122 uses timing signaling and other control signaling 140 to control the pixel driver 120 to drive the display panel 106 to display a frame 132 from the GRAM 118 by scanning the frame data 131 of the frame 132 from the GRAM 118 into the pixel array (not shown) of the display panel 106 with row-line addressing, with the transfer of the pixel data from the pixel driver 120 to the display panel 106 represented by a SCAN signal 142.” Youn ¶ 24.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 13, Zheng teaches A chip system chip system As shown in FIG. 1, FIG. 1 is a structure schematic diagram of a electronic device provided by the embodiment of the invention. the electronic device comprises a processor, a memory, a signal processor, a communication interface, a display screen, a speaker, a microphone, a random access memory (Random Access Memory, RAM), and frame-inserting chip, a video processing module, a camera shooting module and a sensor or the like. wherein the memory, a signal processor, a display screen, a speaker, a microphone, a RAM, a camera shooting module, a sensor, a frame-inserting chip, video processing module is connected with the processor, the communication interface is connected with the signal processor.” Zheng p. 4.), the processor is configured to generate first data (Zheng’s “third video file”) based on first content (Zheng’s “first video file”) to be displayed on an electronic device, wherein a frame rate of the first data (Zheng’s “third video file”) is smaller than a frame rate of the first content (Zheng’s “first video file”) (
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.
Frame rate of the first data (“third video file”) is equal to “second video file,” which is “less [/smaller] than a frame rate of the first video [(first content)]”)
Zheng does not explicitly disclose the chip system is a System-on-a-Chip, or
the communications interface is configured to: in a case that a target display frame rate synchronization (TE) signal sent by an independent display chip in the electronic device is received, send the first data to the independent display chip.
Youn teaches
the chip system is a System-on-a-Chip (“In the illustrated embodiment, the components of the frame generation subsystem 102 are implemented together in a host system-on-a-chip (SoC) 128 while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130.” Youn ¶ 21.), and
the communications interface (communication interface between Youn fig. 1 128 and 130) is configured to: in a case that a target display frame rate synchronization (TE) signal sent by an independent display chip (Youn fig. 1 DDIC 130) in the electronic device is received, send the first data (Youn fig. 1 Frame Data 131) to the independent display chip (Youn fig. 1 DDIC 130) (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Fig. 1 shows that (TE) signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128).
Youn teaches synchronization based on TE to a target frame rate as determined by (DDIC 130/frame-inserting chip).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing. “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
Regarding Claim 14, Claim 14 is similar to Claim 2. Refer to Claim 2’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches The System-on-a-Chip according to claim 13, wherein the processor is specifically configured to perform frame loss processing on the first content (Zheng’s “first video file) based on a preset frame rate, to obtain first data (Zheng’s “third video file”) at the preset frame rate (
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.
The processor is mapped to the disclosed “CPU.” The Examiner conducts a KSR analysis regarding: Simple substitution of one known element (GPU) for another (CPU) to obtain predictable results regarding “rendering.” The GPU’s use is to enhance speed and/efficiency of certain type of computation that CPU can also do. GPU’s rendering could be completed by CPU.
Alternatively, the processor could also be mapped to the disclosed “CPU” + “GPU.”).
Regarding Claim 16, Claim 16 is similar to Claim 5. Refer to Claim 5’s rejection analyses for relevant/related details. Further, Zheng in view of Youn teaches The System-on-a-Chip according to claim 13,
wherein the target TE signal comprises a plurality of TE signals (Youn Fig. 5 shows that the target TE signals have multiple TE signals 514, 522, 528, and 534.); and
the communications interface (communication interface between Youn fig. 1 128 and 130) is specifically configured to send one frame of data in the first data to the independent display chip every time when one TE signal is received, so as to send a plurality of frames of data in the first data to the independent display chip (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Youn Fig. 1 shows that TE signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128)/SYS (CPU+GPU).
Here, a frame of Zheng’s rendered third video file, first data, is transmitted to (DDIC 130/frame-inserting chip) when assertion of TE signal is received, without which the transmission would be delayed. Youn Fig. 5 shows multiples frames N-1, N, N+1, N+2 are generated and sent to (DDIC 130/frame-inserting chip) (Youn Fig. 1).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Regarding Claim 17, Zheng in view of Youn teaches An electronic device, comprising the independent display frame interpolation circuit according to claim 1 (See Claim 1 rejection for detailed analyses).
Claims 3-4, 9-10, and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Youn as applied to Claim 1, 7 or 13, in further view of Takazane et al. (US 20210233494 A1).
Regarding Claim 3, Zheng in view of Youn teaches The circuit according to claim 1, wherein the System-on-a-Chip (Youn ¶ 21) is further configured to determine a preset frame rate (
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. 6.
Here, a preset frame rate, e.g., “12fps,” is determined.
After the combination of Zheng and Youn, the determination is made at Youn’s System-on-a-Chip.); and
the independent display chip is further configured to generate the target TE signal and send the target TE signal to the System-on-a-Chip, and a frequency value of the target TE signal is equal to a value of the preset frame rate (
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Therefore, the independent display chip (DDIC 130/frame-inserting chip, including 104) generates the target TE signal (136) and send it to the System-on-a-Chip (128). The frequency value of the target TE signal is equal to the preset frame rate (“given frame rate”).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing. “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
Zheng in view of Youn does not explicitly disclose send a first instruction to the independent display chip, and the first instruction comprises a preset frame rate.
Takazane teaches send a first instruction to the independent display chip, and the first instruction comprises a preset frame rate (
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
“The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
After Zheng in view of Youn is combined with Takazane, the first instruction is communicated from Zheng in view of Youn’s System-on-a-Chip to Zheng in view of Youn’s independent display chip.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly. “The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
Regarding Claim 4, Zheng in view of Youn and Takazane teaches The circuit according to claim 3, wherein the first instruction further comprises a target frame rate (
Youn teaching determining a target frame rate based on a user preference and/or display characteristics, stating “As one example, the maximum frame rate F.sub.H could be set to the maximum display frame rate supported by the display panel 106 or the software application 110 (e.g., 120 frames-per-second (fps)) while the minimum frame rate F.sub.L could be set to the lowest frame rate deemed to provide a viewing experience of minimum sufficient quality (e.g., 30 fps). The target frame rate F.sub.C represents a target frame rate between the minimum and maximum frame rates (that is, F.sub.L<=F.sub.C<=F.sub.H) and is selected based on one or more considerations, including user preferences or settings, current rendering bandwidth capacity, and the like.” Youn ¶ 31.
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
The Examiner takes an Official Notice that an instruction may comprise multiple settings/parameters. The benefits of combining this well-known knowledge would have been that an instruction could contain more information, allow sophisticated instructions, and/or allow efficient communication.
After Zheng, Youn, Takazane, and Official Notice are combined, the first instruction comprises Youn’s target display framerate and Zeng’s preset frame rate.); and
the independent display chip (including “frame-inserting chip”) is specifically configured to perform frame interpolation processing on the first data (third video file) by using the target frame rate (frame rate of the fourth video file) to obtain the second data (fourth video file) (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
“GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract.
After the combination of Zheng, Youn, and Takazane, the frame rate of the fourth video file corresponds to the target frame rate to be displayed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s target framerate with Zheng. One of ordinary skill in the art would be motivated to allow the flexibility to select display/target frame rate, so that energy could be saved or display quality could be enhanced.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly.
Regarding Claim 9, Claim 9 is similar to Claim 3. Refer to Claim 3’s rejection analyses for relevant/related details. Further, Zheng in view of Youn and Takazane teaches The method according to claim 7,
wherein before the in a case that the System-on-a-Chip receives a target TE signal sent by an independent display chip in the electronic device, sending the first data to the independent display chip through the System-on-a-Chip (
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Therefore, the independent display chip (DDIC 130/frame-inserting chip, including 104) generates the target TE signal (136) and send it to the System-on-a-Chip (128). The first data correspond to the frame sent to the independent display chip (DDIC 130/frame-inserting chip, including 104) from the System-on-a-Chip (128).
Youn Fig. 5 shows the time sequence related to data transmission and TE signals.),
the method further comprises:
determine a preset frame rate (
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. X.
Here, a preset frame rate, e.g., “12fps,” is determined.
After the combination of Zheng and Youn, the determination is made at Youn’s System-on-a-Chip.); and
generating the target TE signal through the independent display chip, and sending the target TE signal to the System-on-a-Chip through the independent display chip, wherein a frequency value of the target TE signal is equal to a value of the preset frame rate (
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Therefore, the independent display chip (DDIC 130/frame-inserting chip, including 104) generates the target TE signal (136) and send it to the System-on-a-Chip (128). The frequency value of the target TE signal is equal to the preset frame rate (“given frame rate”).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Zheng in view of Youn does not explicitly disclose
sending a first instruction to the independent display chip through the System-on-a-Chip, wherein the first instruction comprises a preset frame.
Takazane teaches sending a first instruction to the independent display chip through the System-on-a-Chip, wherein the first instruction comprises a preset frame (
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
“The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
After Zheng in view of Youn is combined with Takazane, the first instruction is communicated from Zheng in view of Youn’s System-on-a-Chip to Zheng in view of Youn’s independent display chip.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly.
Regarding Claim 10, Claim 10 is similar to Claim 4. Refer to Claim 4’s rejection analyses for relevant/related details. Further, Zheng in view of Youn and Takazane teaches The method according to claim 9,
wherein the first instruction further comprises a target frame rate (
Youn teaching determining a target frame rate based on a user preference and/or display characteristics, stating “As one example, the maximum frame rate F.sub.H could be set to the maximum display frame rate supported by the display panel 106 or the software application 110 (e.g., 120 frames-per-second (fps)) while the minimum frame rate F.sub.L could be set to the lowest frame rate deemed to provide a viewing experience of minimum sufficient quality (e.g., 30 fps). The target frame rate F.sub.C represents a target frame rate between the minimum and maximum frame rates (that is, F.sub.L<=F.sub.C<=F.sub.H) and is selected based on one or more considerations, including user preferences or settings, current rendering bandwidth capacity, and the like.” Youn ¶ 31.
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
The Examiner takes an Official Notice that an instruction may comprise multiple settings/parameters. The benefits of combining this well-known knowledge would have been that an instruction could contain more information, allow sophisticated instructions, and/or allow efficient communication.
After Zheng, Youn, Takazane, and Official Notice are combined, the first instruction comprises Youn’s target display framerate and Zeng’s preset frame rate.); and
the performing frame interpolation processing on the first data through the independent display chip to obtain second data comprises: performing frame interpolation processing on the first data through the independent display chip by using the target frame rate, to obtain the second data (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
“GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract.
After the combination of Zheng, Youn, and Takazane, the frame rate of the fourth video file corresponds to the target frame rate to be displayed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s target framerate with Zheng. One of ordinary skill in the art would be motivated to allow the flexibility to select display/target frame rate, so that energy could be saved or display quality could be enhanced.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly.
Regarding Claim 15, Claim 15 is similar to Claim 3. Refer to Claim 3’s rejection analyses for relevant/related details. Further, Zheng in view of Youn and Takazane teaches The System-on-a-Chip according to claim 13,
wherein the communications interface (communication interface between Youn fig. 1 128 and 130) is further configured todetermine a preset frame rate (
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. 6.
Here, a preset frame rate, e.g., “12fps,” is determined.
After the combination of Zheng and Youn, the determination is made at Youn’s System-on-a-Chip and transmitted by a communication interface between Youn fig. 1 128 and 130 ); and
the communications interface (communication interface between Youn fig. 1 128 and 130) is further configured to receive the target TE signal sent by the independent display chip, and a frequency value of the target TE signal is equal to a value of the preset frame rate (
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Therefore, the independent display chip (DDIC 130/frame-inserting chip, including 104) generates the target TE signal (136) and send it to the System-on-a-Chip (128). The frequency value of the target TE signal is equal to the preset frame rate (“given frame rate”).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Zheng in view of Youn does not explicitly disclose send a first instruction to the independent display chip, and the first instruction comprises a preset frame rate.
Takazane teaches send a first instruction to the independent display chip, and the first instruction comprises a preset frame rate (
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
“The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
After Zheng in view of Youn is combined with Takazane, the first instruction is communicated from Zheng in view of Youn’s System-on-a-Chip to Zheng in view of Youn’s independent display chip.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Youn as applied to Claim 13, in further view of Maeda et al. (“US 20210327366 A1”).
Regarding Claim 18, Zheng in view of Youn teaches An electronic device, comprising the System-on-a-Chip according to claim 13 (see Claim 13 rejection for detailed analysis) and an independent display chip (the combination based on Youn’s DDIC 130 and Zheng’s frame-inserting chip);
wherein the independent display chip comprises
“. . . while the components of the display control subsystem 104 are implemented on a separate display driver integrated circuit (DDIC) 130.” Youn ¶ 21.
Youn Fig. 1 shows that DDIC 130 communicates with Fig. 1 128, 106.),
the communications interface is configured to:
send a target display frame rate synchronization (TE) signal (Youn figs. 1, 5) to a System-on-a-Chip in an electronic device, and receive first data (Zheng’s “third video file”) sent by the System-on-a-Chip, wherein the first data (Zheng’s “third video file”) is data generated by the System-on-a-Chip based on first content (Zheng’s “first video file”) to be displayed on the electronic device, a frame rate of the first data (Zheng’s “third video file”) is smaller than a frame rate of the first content (Zheng’s “first video file”) (
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Fig. 1 shows that (TE) signal (136) sent by independent display chip (DDIC 130/frame-inserting chip) is received by SOC (128).
Youn teaches synchronization based on TE to a target frame rate as determined by (DDIC 130/frame-inserting chip).
“CPU obtains the first video file; if the frame rate of the first video file is greater than or equal to a first threshold, then the video processing module for reducing frame processing the first video file to obtain the second video file, frame rate of the second video file is less than a frame rate of the first video file; GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.
Frame rate of the first data (“third video file”) is equal to “second video file,” which is “less [/smaller] than a frame rate of the first video [(first content)]”); and
the processor is configured to perform frame interpolation processing on the first data (Zheng’s “third video file”) to obtain second data (Zheng’s “fourth video file”), and a frame rate of the second data (Zheng’s “fourth video file”) is greater than or equal to the frame rate of the first content (Zheng’s “first video file”) (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5. “wherein, the frame rate of the fourth video file may be greater than a frame rate of the first video file, can be less than or equal to the frame rate of the first video file, will not be limited. frame rate of the second video file is equal to the frame rate of the third video file.” Zheng p. 6.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing.
Zheng in view of Youn does not explicitly disclose wherein the independent display chip comprises a processor.
Maeda teaches wherein the independent display chip comprises a processor and the communications interface is coupled to the processor (
“wherein the display driver IC comprises: a pre-processor configured to, . . ..” Maeda Claim 15.
The communication interface is coupled to the processor because the communication interface receives data for the processor to process and transmits data processed by the processor.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Maeda’s processor in display driver with Zheng in view of Youn. One of ordinary skill in the art would be motivated to enhance the processing capability of the display driver. The could reduce the computation burden on the computing device that sends the displaying data. Maeda discloses, “Referring to FIG. 12, a display driver IC 100a may further include a pre-processing device 160. In some example embodiments, although such pre-processing device 160 may be located outside the source driver 120, the embodiments are not limited thereto.” Maeda ¶ 92.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zheng in view of Youn and Maeda as applied to Claim 18, in further view of Takazane.
Regarding Claim 19, Zheng in view of Youn and Maeda teaches The electronic device according to claim 18,
wherein the communications interface is further configured to receive
“as illustrated, frame rate of the first video file is 30fps, the screening processing of video processing module can do a certain frame rate for the first video file to obtain the second video file. the frame rate of the video file is reduced from 30fps to the received fourth video file the 12fps; GPU 12fps for rendering an image to obtain a third video file, and the third video file and provided to the frame-inserting chip; the frame-inserting chip by way of inserting frame the frame rate up to 60fps. obtain a fourth video file, so as to obtain the picture more smoothly than the 30fps frame rate of the first video file. Because the GPU end processing of the frame rate of the second video file is 12fps, reduces 18fps relative to the frame rate of the first video file, so as to reduce the GPU needs to consume about 380mW power consumption. and for inserting a frame chip, its power consumption is substantially increased by about 60mW.” Zheng p. X.
Here, a preset frame rate, e.g., “12fps,” is determined.
After the combination of Zheng and Youn, the determination is made at Youn’s System-on-a-Chip and sent through the communications interface.);
the processor is further configured to generate the target TE signal (Youn figs. 1, 5); and the communications interface is further configured to send the target TE signal to the System-on-a-Chip, and a frequency value of the target TE signal is equal to a value of the preset frame rate (
“At the display control subsystem 104, the timing controller 122 uses one or more clock (CLK) signals 134 provided by the one or more clock sources 124 and one or more counters 126 to generate various control signals, including a tearing effect (TE) signal 136, . . .. The TE signal 136 is used to synchronize the transfer of the next frame 130 from the frame generation subsystem 102 to the GRAM 118 so as to mitigate screen tearing artifacts resulting from overwriting the current frame before the last row of the current frame has been displayed at the display pane 106.” Youn ¶ 23.
“For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
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After Zheng and Youn are combined, Youn’s DDIC 130 and Zheng’s “frame-inserting chip” are merged. Both are similarly situated between a display and a frame render on SOC, and their functionalities to synchronize frames are similar as well.
Therefore, the independent display chip (DDIC 130/frame-inserting chip, including 104) generates the target TE signal (136) and send it to the System-on-a-Chip (128). The frequency value of the target TE signal is equal to the preset frame rate (“given frame rate”).).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s TE signals for synchronization with Zheng. One of ordinary skill in the art would be motivated to synchronize frame-generation and frame-displaying. The frames would be displayed accurately, and/or the visual effect is consistent and pleasing. “For a given frame rate, this specified signal is provided within a specified delay following assertion of a synchronizing signal, such as a tearing effect (TE) signal. Such a synchronizing signal may be used to synchronize transfer of the next frame from a frame generation subsystem to a buffer. As such, failure to receive this specified signal within the corresponding delay following assertion of the synchronizing signal indicates that rendering of the frame is delayed.” Youn ¶ 4.
Zheng in view of Youn and Maeda does not explicitly disclose send a first instruction to the independent display chip, and the first instruction comprises determine a preset frame rate.
Takazane teaches send a first instruction to the independent display chip, and the first instruction comprises a preset frame rate (
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
“The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
After Zheng in view of Youn and Maeda is combined with Takazane, the first instruction is communicated from Zheng in view of Youn and Maeda’s System-on-a-Chip to Zheng in view of Youn and Maeda’s independent display chip.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn and Maeda. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly. “The frame rate setting unit 22 sets the frame rate of the video image data, to be output to the display panel 4 from the timing generator 3, to the predetermined value and outputs a frame rate control signal to the timing generator 3. The frame rate control signal is a control signal for controlling the timing generator 3 to set the frame rate of the video image data to the predetermined value.” Takazane ¶ 36.
Regarding Claim 20, Zheng in view of Youn, Maeda, Takazane teaches The electronic device according to claim 19,
wherein the first instruction further comprises a target frame rate (
Youn teaching determining a target frame rate based on a user preference and/or display characteristics, stating “As one example, the maximum frame rate F.sub.H could be set to the maximum display frame rate supported by the display panel 106 or the software application 110 (e.g., 120 frames-per-second (fps)) while the minimum frame rate F.sub.L could be set to the lowest frame rate deemed to provide a viewing experience of minimum sufficient quality (e.g., 30 fps). The target frame rate F.sub.C represents a target frame rate between the minimum and maximum frame rates (that is, F.sub.L<=F.sub.C<=F.sub.H) and is selected based on one or more considerations, including user preferences or settings, current rendering bandwidth capacity, and the like.” Youn ¶ 31.
Takazane teaches send a first instruction, comprising information of a frame rate, to another circuit component, stating “The predetermined frame rate is set by the frame rate setting unit 22. In response to receiving an instruction from the video frame rate setting unit 22, the video image data transfer unit 21 transfers the video image data to the timing generator 3 at the predetermined frame rate.” Takazane ¶ 35.
The Examiner takes an Official Notice that an instruction may comprise multiple settings/parameters. The benefits of combining this well-known knowledge would have been that an instruction could contain more information, allow sophisticated instructions, and/or allow efficient communication.
After Zheng, Youn, Maeda, Takazane, and Official Notice are combined, the first instruction comprises Youn’s target display framerate and Zeng’s preset frame rate.); and
the processor is specifically configured to perform frame interpolation processing on the first data by using the target frame rate to obtain the second data (
“frame-inserting chip frame-inserting processing the third video file.” Zheng Abstract. “then performing the frame interpolation process, the frame rate of the video file after inserting frame is greater than a frame rate of the video file before inserting frame, so it improves the fluency of the video file playing.” Zheng p. 5.
“GPU rendering processing, the second video file to obtain the third video file, frame-inserting chip frame-inserting processing the third video file, obtaining the fourth video file, frame rate of the fourth video file is greater than a frame rate of the second video file, the CPU controls the display screen to play the fourth video file using the embodiment of the invention can improve the degree of smooth video file playing, reduces the power consumption of the electronic device.” Zheng Abstract.
After the combination of Zheng, Youn, Maeda, and Takazane, the frame rate of the fourth video file corresponds to the target frame rate to be displayed.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Youn’s target framerate with Zheng. One of ordinary skill in the art would be motivated to allow the flexibility to select display/target frame rate, so that energy could be saved or display quality could be enhanced.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Takazane’s framerate related instruction with Zheng in view of Youn and Maeda. One of ordinary skill in the art would be motivated to allow different components of a device to use consistent settings. Therefore, the corresponding computing system would perform correctly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
LOBETE (US 20210400170 A1) teaches features similar to claimed invention as explained below:
[0079] Generally, the interpolation approach of the disclosure allows for the timings of rendered frames to be controlled so that frames may be displayed in a way which provides smoother motion of content within the frames. In other words, the existing problem of jerky motion may be reduced. In addition, the interpolation approach of the disclosure is able to compensate for when content fails to be rendered in time for a delay refresh. This is because the disclosure is able to fill missed frames with interpolated frames, rather than existing approaches of repeating the last frame. In addition, the disclosure is able to reduce the rendering frame rate and compensate for this by up-converting the rendered frames. For example, a frame rendered rate of 30 frames per second may be up-converted to 60 frames per second. As another example, a frame rendering rate of 60 frames per second may be up-converted to 120 frames per second. This can improve the user experience.
However, the limitation generate first data based on first content to be displayed is not clearly taught.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHENGXI LIU whose telephone number is (571)270-7509. The examiner can normally be reached M-F 9 AM - 5 PM.
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/ZHENGXI LIU/ Primary Examiner, Art Unit 2611
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