Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(II) and Interview Practice for additional details.
Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of claim to be treated in this office action:
Independent: 1, 9, 17 and 19.
b. Claims 1-20 are pending on the application.
Preliminary Amendment
2. Acknowledgment is made of applicant’s Preliminary Amendment, filed 08/28/2024. The changes and remarks disclosed therein were considered.
An amendment of the specification has been amended. Claims 1-20 are pending in the application.
Drawing
3 The drawings were received on 06/27/2024. These drawings are review and accepted by examiner.
Specification
4. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words. It is important that the abstract not exceed 150 words in length since the space provided for the abstract on the computer tape used by the printer is limited. The form and legal phraseology often used in patent claims, such as "means" and "said," should be avoided. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details.
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, "The disclosure concerns," "The disclosure defined by this invention," "The disclosure describes," etc.
The abstract of the disclosure is objected to because it uses the phrase “Embodiments of the disclosure are drawn to”, “In some examples,” “that are present”, “In some other examples” and “In some other examples” in page 35, line 2, 6, 7, 8 and 10, respectively, which are implied. Correction is required. See MPEP § 608.01(b).
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1-3 and 17-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sonehara (Pub. No.: US 2014/0321194 A1).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding to independent claim 1. Sonehara in Figures 1, 6-7 and 9 are directly discloses an apparatus (an apparatus of a non-volatile memory device, Figure 1) comprising:
a first digit line (a bit line BL, a memory cell array 1 includes a plurality of memory cell MC, each memory cell MC contain the bit line BL, Fig. 1);
a first word line (a word line WL, a memory cell array 1 includes a plurality of memory cell MC, each memory cell MC contain the word line WL, Fig. 1); and
a first memory cell (a memory cell array 1 includes a plurality of memory cell MC, each memory cell MC contain the bit line BL and the word line WL, Fig. 1) coupled to the first digit line (the memory cell MC coupled to the bit line BL, Fig. 1) and to the first word line (the memory cell MC coupled to the word line WL, Fig. 1), wherein the first memory cell (the memory cell MC, Fig. 1 and the select memory cell MC0<1,1>, Figs. 6-7) is configured to store a first value (the select memory cell MC0<1,1> with bit value 1,1, Figs. 6-7, paragraph 0086), and wherein the first value is generated based at least in part on a first residual charge (the select memory cell MC0<1,1> of the residual charge such as cause o potential of the select bit line BL or select word line WL, Figs. 6-7, paragraph 0094-0096) in the first memory cell (see at least in Figures 1, 6-7 and 9, paragraph 0045-0064, paragraph 0084-0098 and the related disclosures).
Regarding dependent claim 2. Sonehara in Figures 1, 6-7 and 9 are directly discloses an apparatus (an apparatus of a non-volatile memory device, Figure 1), wherein the first residual charge (the select memory cell MC0<1,1> of the residual charge such as cause o potential of the select bit line BL or select word line WL, Figs. 6-7, paragraph 0094-0096) is from before start-up of the apparatus.
Regarding dependent claim 3. Sonehara in Figures 1, 6-7 and 9 are directly discloses an apparatus (an apparatus of a non-volatile memory device, Figure 1), wherein the first value (the select memory cell MC0<1,1>, Figs. 6-7) is, at least partially representative of an initial count value of access operations performed on a row of memory cells (the select memory cell MC0<1,1> access into the row/bit line of memory cell).
Regarding claims 17-18, they encompass the same scope of invention as that of claims 1-3, except they draft the invention in method format instead of apparatus format. Sonehara teach all the necessary elements to perform the method of these claims. The aspects of the invention contained in claims 17-18, are therefore rejected in method format for the same reasons claims 1-3, were rejected in apparatus format, as discussed above in the prior paragraphs of the office action.
Allowable Subject Matter
6. Claims 4-8, insofar as in compliance with the rejection above, are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The cited are, whether taken singularly or in combination, especially when all limitations are considered within the claimed specific combination, fail to teach or render obvious of the remaining claimed limitations.
With respected to dependent claims 4-8, the prior art fails to tech or suggest the claimed limitations, namely, a sense amplifier, wherein the first value is generated based at least in part on operations by the sense amplifier on the first residual charge, wherein the sense amplifier comprises a threshold voltage compensation sense amplifier, the apparatus further comprising: a pseudo-random generator circuit configured to generate a value having a plurality of bits; and, a threshold voltage compensation pulse width generator circuit configured to generate a pulse width signal based at least in part on the value from the pseudo-random generator circuit, and configured to provide the pulse width signal to the sense amplifier, wherein a duration of a threshold voltage compensation phase of the sense amplifier is based at least in part on the pulse width signal, wherein the pseudo-random generator circuit comprises a linear feedback shift register, further comprising: a second digit line coupled to the sense amplifier; a second word line; a second memory cell coupled to the second digit line and to the second word line, wherein the second memory cell is configured to store a second value, wherein the second value is complementary to the first value, wherein the sense amplifier is configured to compare the first residual charge to a second residual charge on the second memory cell.
9. Claims 9-16 and 19-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
There is no teaching or suggestion in the prior art to provide:
Per claim 9: there is no teaching, suggestion, or motivation for combination in the prior art to “a threshold voltage compensation sense amplifier coupled to the first digit line; and a first memory cell coupled to the first digit line and to the first word line, wherein the first memory cell is configured to store a first value that is based at least in part on a random or pseudo-random threshold voltage compensation pulse width” in an apparatus as claimed in the independent claim 9. Claims 10-16 are also allowed because of their dependency on claim 9; or
Per claim 19: there is no teaching, suggestion, or motivation for combination in the prior art to the steps of “initializing the counter a memory cell of the memory device with a value that is based at least in part on a random or pseudo-random threshold voltage compensation pulse width for a threshold voltage compensation sense amplifier” in a method for initializing a counter memory cell of a memory device as claimed in the independent claim 19. Claim 20 is also allowed because of its dependency on claim 19.
Conclusion
Examiner's note: Examiner has cited particular columns and line numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Di Vincenzo et al (US. 10,049,713 B2) discloses full bias sensing in a memory array.
Tanzawa (US. 11,978,529 B2) discloses random access type memory circuit and memory system.
When responding to the office action, Applicant are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner to located the appropriate paragraphs.
A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the data of this letter. Failure to respond within the period for response will cause the application to become abandoned (see MPEP 710.02 (b)).
Any inquiry concerning this communication or earlier communications from the Examiner should be directed to PHO M LUU whose telephone number is
571.272.1876. The Examiner can normally be reached on M-F 8:00AM – 5:00PM.
If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s Supervisor, Richard Elms, can be reached on 571.272.1869. The official fax number for the organization where this application or proceeding is assigned is 571.273.8300 for all official communications.
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/Pho M Luu/
Primary Examiner, Art Unit 2824.
571-272-1876.
Miner.Luu@uspto.gov