Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to claims filed 06/27/2024. Claims 1-20 are pending.
Priority
Applicant’s claim for priority from foreign application KR10-2023-0153674 filed 11/08/2023 is acknowledged.
Claim Objections
Claims 1-11 are objected to because of the following informalities:
Regarding Claim 1, Line 7 states “a second core that configure to.” For examination, the Examiner is interpreting this as stating “a second core that is configured to.”
Any Claim not specifically mentioned is objected to due to its dependence on an objected Claim.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Therien et al. (US 20170177407 A1) in view of Vajapeyam (US 9804896 B2), hereinafter referred to as Therien and Vajapeyam, respectively.
Regarding Claim 1, Therien discloses A multi-core processor which includes a plurality of cores ([0016] a multicore processor used in conjunction with at least one embodiment […] a processor 101 includes a core region 120 and an uncore 122. In some embodiments, the core region 120 includes multiple processing cores 102, but disclosed functionality may be applicable to single core processors in a multi-processor system. Please note that the multicore processor 101, including multiple processing cores 102, corresponds to Applicant’s multi-core processor which includes a plurality of cores.), comprising:
a first core configured to receive a task migration instruction ([0025] migrate a thread and its corresponding performance objective or context information from a first core (e.g., the first processing core 102-1). Please note that the first processing core 102-1 that is to be migrated from corresponds to Applicant’s first core configured to receive a task migration instruction.),
and transmit metadata obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory ([0031] a core migration flow can include the following operations: Save core states of the cores to be migrated to C6 storage.; [0034] In block 314, the source core 302 saves its core state (e.g., instruction location, register values and/or other state data) to a core state (or context and identity) storage, such as C6 storage. Please note that saving the core state of the core to be migrated, in this case, that of the first core, including various state data, to the core state storage for context and identity in the C6 storage, corresponds to Applicant’s transmitting metadata obtained during execution of a migration subject task determined as a subject of the task migration instruction among a plurality of tasks, to an external memory. );
and a second core that configure to receive a task execution instruction, read the metadata from the external memory based on the task execution instruction, and execute the migration subject task using the metadata ([0029] When resuming, the core can restore the core context and identity and resume processing.; [0031] Restore each core from the other core's state that was saved in C6 storage. Please note that restoring each core, in this case, a second core 102-2 distinct from the first core 102-1, from the first core’s state that was saved in C6 storage, restoring the core context and identity, and resuming processing, corresponds to Applicant’s second core that is configured to receive a task execution instruction, read the metadata from the external memory based on the task execution instruction, and execute the migration subject task using the metadata.).
Therien does not explicitly disclose including branch prediction data
However, Vajapeyam discloses including branch prediction data (Col. 4, Lines 12-15- The micro-architectural state components 110A and 110B may include […] branch predictor tables. Please note that the state components including branch predictor tables corresponds to Applicant’s including branch prediction metadata. )
Therien and Vajapeyam are both considered to be analogous to the claimed invention because they are in the same field of computer thread migration across cores. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Therien to incorporate the teachings of Vajapeyam to modify the multi-core processor system with a first core receiving a task migration instruction, transmitting metadata to an external memory, and with a second core that receives a task execution instruction, reads the metadata from the external data based on it, and executes the migration subject task using the metadata to include branch prediction data in the metadata , allowing for improved dynamic acquisition of the state data from the other core and resulting in improved system adaptability, as described in Vajapeyam.
Regarding Claim 2, Therien-Vajapeyam as described in Claim 1, Therien further discloses a scheduler configured to assign the plurality of tasks to the first core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Please note that the placement controller 134 corresponds to Applicant’s scheduler configured to assign the plurality of tasks to the first core.),
determine task migration from the first core to the second core based on utilizations of the first core and of the second core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, corresponds to Applicant’s determining task migration from the first core to the second core based on utilizations of the first core and of the second core.),
and transmit the task migration instruction and the task execution instruction based on the determination of the task migration from the first core to the second core ([0023] The OS places work on the logical processors visible to it, and the processor (e.g., the PCU 124) may at a later time migrate a thread to a different resource. For example, the PCU 124 can initiate a sequence that saves the core's context, restores the context to a different core, and redirects a local APIC ID of the previous core to the new core. This migration can occur at the core or thread level. Alternatively, the hardware can provide migration hints to the OS through an operating system interface 126, and the OS can move the work from one core or thread to another. Please note that the PCU 124 migrating a thread, which can occur at a core level that is carried out by a sequence initiated by the PCU, corresponds to Applicant’s transmitting the task migration instruction and the task execution instruction based on the determination of the task migration from the first core to the second core.).
Regarding Claim 3, Therien-Vajapeyam as described in Claim 2, Therien further discloses wherein the utilization is determined based on a load or power consumption of the plurality of cores, and the utilization of the second core is less than the utilization of the first core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, where power use can be a measure of efficiency, corresponds to Applicant’s utilization being determined based on a power consumption of the plurality of cores, and the utilization of the second core is less than the utilization of the first core, i.e., if the first core would be operating above a threshold, it would have a higher utilization than the second core.).
Regarding Claim 4, Therien-Vajapeyam as described in Claim 2, Therien further discloses wherein the multi-core processor further includes a third core configured to execute a plurality of tasks ([0016] In some embodiments, the processor 101 includes a first processing core 102-1, a second processing core 102-2, and so forth through an n-th processing core 102-n. Please note that a 3rd core of the n processing cores, i.e., a processing core 102-3, corresponds to Applicant’s multi-core processor further including a third core configured to execute a plurality of tasks.),
and the scheduler is configured to determine task migration from the third core to the first core based on the utilization of the first core and a utilization of the third core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, and the placement controller 134 determining the work that can be moved to a different core corresponds to Applicant’s scheduler being configured to determine task migration from the third core to the first core based on the utilization of the first core and a utilization of the third core.),
and the first core is configured to read metadata to be used to execute a migration subject task migrated from the third core, from the external memory ([0029] When resuming, the core can restore the core context and identity and resume processing.; [0031] Restore each core from the other core's state that was saved in C6 storage. Please note that restoring each core, in this case, the first core 102-1 distinct from the third core 102-3, from the other, third core’s state that was saved in C6 storage, restoring the core context and identity, and resuming processing, corresponds to Applicant’s first core being configured to read metadata to be used to execute a migration subject task migrated from the third core from the external memory.).
Regarding Claim 5, Therien-Vajapeyam as described in Claim 1, Vajapeyam further discloses wherein the metadata contains a tag for identifying the metadata (Col. 4, Lines 20-23- state data associated with the architectural state and the micro-architectural state of the first processing core 102 and the second processing core 104 includes tags. Please note that tags included in state data associated with the processing core states corresponds to Applicant’s metadata containing a tag for identifying the metadata. ).
Regarding Claim 6, Therien-Vajapeyam as described in Claim 5, Therien further discloses wherein the task execution instruction contains a task ID for identifying the migration subject task ([0010] When the work is transitioned between cores, these identifiers can be transferred along with the work (such as a thread). Please note that the identifiers associated with work that are transferred with it correspond to Applicant’s task execution instruction containing a task ID for identifying the migration subject task.)
Vajapeyam further discloses and tag information for identifying the metadata(Col. 4, Lines 20-23- state data associated with the architectural state and the micro-architectural state of the first processing core 102 and the second processing core 104 includes tags. Please note that tags included in state data associated with the processing core states corresponds to Applicant’s tag information for identifying the metadata. ).
Regarding Claim 7, Therien-Vajapeyam as described in Claim 1, Vajapeyam further discloses wherein the first core and the second core are a same type of cores (Col. 10, Lines 28-34- processor 604 may be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor 604 may include one or more levels of caching, such as a level one cache 610 and a level two cache 612, two or more processor cores 614, and registers 616. Please note that the processor consisting of two or more processor cores, where the processor may be of a type that has 2 identical cores, such as two microprocessors, corresponds to Applicant’s first and second cores being a same type of core.).
Regarding Claim 8, Therien-Vajapeyam as described in Claim 1, Vajapeyam further discloses wherein the first core includes a first converter configured to convert the metadata according to conversion rules (Col. 8, Lines 13-37-A state coherence request can be sent to the coherence module 114B of the second processing core 104 to trigger the state coherence protocol (operation 406). The state coherence request can be sent from the coherence module 114B to the coherence module 114A of the first processing core 102 for acquiring the respective value 204A of the corresponding register 212A from the first processing core 102 (operation 408). Please note that the coherence model 114A carrying out the state coherence protocol 406 corresponds to the first converter configured to convert the metadata according to conversion rules, and as it is of the first processing core 102 and operates with its respective values, this corresponds to being included in the first core.),
and the second core includes a second converter configured to interpret the converted metadata and reconvert the converted metadata into a form usable in the second core, according to the conversion rules (Col. 8, Lines 13-37- The value of the entry 204A can then be passed on to the coherence module 114B of the second processing core 104 (operation 416). The value then replaces the current value 204B of the register (R0) 212B of the register file 200B (operation 418) and the Vbit 220B of the corresponding entry can be set to be valid (operation 420). This updated value 204B can be utilized by the processor 106B while executing the thread 112 on the second processing core 104 (operation 422). Please note that the coherence module 114B of the second processing core 104 that replaces the values of the registers associated with the second core based on the received data from the first core after it can be passed corresponds to Applicant’s second core including a second converter configured to interpret the converted metadata and reconvert the converted metadata into a form usable in the second core, according to the conversion rules).
Regarding Claim 9, Therien-Vajapeyam as described in Claim 8, Vajapeyam further discloses wherein the first core and the second core are different types of cores Col. 10, Lines 28-34- processor 604 may be of any type including but not limited to a microprocessor (μP), a microcontroller (μC), a digital signal processor (DSP), or any combination thereof. Processor 604 may include one or more levels of caching, such as a level one cache 610 and a level two cache 612, two or more processor cores 614, and registers 616. Please note that the processor consisting of two or more processor cores, where the processor may be of a type that has 2 different cores, such as a microprocessor and a microcontroller, as the reference recites “any combination” of processor types, corresponds to Applicant’s first and second cores being a different type of core.).
Regarding Claim 10, Therien-Vajapeyam as described in Claim 1, Vajapeyam further discloses wherein the metadata further contains translation lookaside buffer data (TLB data) (Col. 1, Lines 40-42- translation lookaside buffer (TLB) entries may be stored in data cache of the source core and may be subsequently migrated to data cache of the target core. Please note that TLB entries being stored in data cache of the source core to be subsequently migrated to the data cache of the target core corresponds to Applicant’s metadata further containing translation lookaside buffer (TLB) data.),
Therien further discloses prefetch data ([0017] the processing cores 102 include a front end 104, […] the front end 104 is operable to fetch instructions from an instruction cache (not depicted) and schedule the fetched instructions for execution. Please note that fetching instructions and scheduling the fetched instructions for execution as part of the front end 104 of the processing cores 102 corresponds to Applicant’s metadata including prefetch data, i.e., the fetched instructions scheduled to be executed by the particular core.),
and power control data ([0021] The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in […] power use. Please note that the power use of particular processing cores 102 being measured by the placement controller 134 corresponds to Applicant’s power control data of the metadata.).
Regarding Claim 11, Therien-Vajapeyam as described in Claim 1, Therien further discloses wherein the task migration is a process migration or a thread migration ([0014] migrating workloads (or hardware threads).; [0025] select processing cores 102 for execution of specific threads and to migrate a thread and its corresponding performance objective or context information from a first core (e.g., the first processing core 102-1) to a second core (e.g., the second processing core 102-2). Please note that migrating threads and its performance objective corresponds to Applicant’s task migration being a thread migration. ).
Regarding Claim 12, Therien discloses An operating method of a computing system ([0009] [0009] Techniques, apparatus and methods are disclosed that enable migration of work between processor cores. Please note that the method enabling migration of work between processor cores corresponds to Applicant’s operating method of a computing system.), the method comprising:
determining a first core as a source core among a plurality of cores based on a utilization of the first core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core).; [0025] migrate a thread and its corresponding performance objective or context information from a first core (e.g., the first processing core 102-1). Please note that determining the work that can be moved from a first core to a different core to increase efficiency, measured in work accomplished, corresponds to Applicant’s determining a first core as a source core among a plurality of cores based on a utilization of the first core.);
determining a first task among a plurality of tasks assigned to the first core, as a migration subject task ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Please note that the placement controller 134 determining which work from the first core can be moved to a different core to increase efficiency corresponds to Applicant’s determining a first task among a plurality of tasks assigned to the first core as a migration subject task.),
Therien does not explicitly disclose converting metadata obtained during execution of the first task into conversion data based on conversion rules;
and transmitting the conversion data to a memory.
However, Vajapeyam discloses converting metadata obtained during execution of the first task into conversion data based on conversion rules (Col.7, Lines 43-54- a state coherence protocol to dynamically acquire state data for thread migration from the first processing core 102 to the second processing core 104 of the multi-core processor 100; Col. 8, Lines 13-37-A state coherence request can be sent to the coherence module 114B of the second processing core 104 to trigger the state coherence protocol (operation 406). The state coherence request can be sent from the coherence module 114B to the coherence module 114A of the first processing core 102 for acquiring the respective value 204A of the corresponding register 212A from the first processing core 102 (operation 408). Please note that the coherence model 114A carrying out the state coherence protocol 406 corresponds to the converting the metadata into conversion data based on conversion rules, and as it is of the first processing core 102 and operates with its respective values, this corresponds to being obtained during execution of the first task.);
and transmitting the conversion data to a memory (Col.7, Lines 43-54- a state coherence protocol to dynamically acquire state data for thread migration from the first processing core 102 to the second processing core 104 of the multi-core processor 100. […] In some example embodiments, the first processing core 102 includes an architectural state component such as a register file 200A and the second processing core 104 includes a register file 200B. For ease of description, a register file can be utilized to depict an architectural state component of each of the processing cores 102 and 104. Please note that acquiring state data for thread migration from the first processing core 102 to the second processing core 104, including a register file 200A that depicts the architectural state component of processing core 102, corresponds to Applicant’s transmitting the conversion data to a memory.).
Therien and Vajapeyam are both considered to be analogous to the claimed invention because they are in the same field of computer thread migration across cores. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Therien to incorporate the teachings of Vajapeyam to modify the computing system operating method that determines a first core as a source core among a plurality of cores based on a utilization of the first core and a first task among a plurality of tasks assigned to the first core as a migration subject task to convert metadata obtained during execution of the first task into conversion data based on conversion rules and transmit the conversion data to a memory, allowing for improved dynamic acquisition of the state data from the other core and resulting in improved system adaptability, as described in Vajapeyam.
Regarding Claim 13, Therien-Vajapeyam as described in Claim 12, Therien further discloses determining a second core among the plurality of cores as a target core based on a utilization of the second core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, and the placement controller 134 determining the work that can be moved to a different core corresponds to Applicant’s determining a second core among the plurality of cores as a target core based on a utilization of the second core.);
Vajapeyam further discloses receiving the conversion data from the memory; interpreting the conversion data, and reconverting the conversion data in a form usable in the target core according to conversion rules (Col. 8, Lines 13-37- The value of the entry 204A can then be passed on to the coherence module 114B of the second processing core 104 (operation 416). The value then replaces the current value 204B of the register (R0) 212B of the register file 200B (operation 418) and the Vbit 220B of the corresponding entry can be set to be valid (operation 420). This updated value 204B can be utilized by the processor 106B while executing the thread 112 on the second processing core 104 (operation 422). Please note that the coherence module 114B of the second processing core 104 that replaces the values of the registers associated with the second core based on the received data from the first core after it can be passed corresponds to Applicant’s receiving the conversion data from the memory, interpreting the conversion data, and reconverting the conversion data in a form usable in the target core according to conversion rules);
and executing the first task (Col. 8, Lines 13-37- The value of the entry 204A can then be passed on to the coherence module 114B of the second processing core 104 (operation 416). The value then replaces the current value 204B of the register (R0) 212B of the register file 200B (operation 418) and the Vbit 220B of the corresponding entry can be set to be valid (operation 420). This updated value 204B can be utilized by the processor 106B while executing the thread 112 on the second processing core 104 (operation 422). Please note that the second processing core executing the thread 112 corresponds to Applicant’s executing the first task).
Regarding Claim 14, Therien-Vajapeyam as described in Claim 13, Therien further discloses assigning the plurality of tasks to the plurality of cores ([0022] a core is used and/or used to perform a large workload, the efficiency of the core decreases. […] The workload can be spread among cores. Please note that the workload spread among cores corresponds to Applicant’s assigning the plurality of tasks to the plurality of cores.);
and detecting utilizations of each of the plurality of cores ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished for each core, corresponds to Applicant’s detecting utilizations of each of the plurality of cores.).
Regarding Claim 15, Therien-Vajapeyam as described in Claim 14, Therien further discloses wherein determining the first core as the source core includes determining that the utilization of the first core exceeds a utilization threshold ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, in order to avoid a core from operating above a threshold corresponds to Applicant’s determining the first core as the source core includes determining that the utilization of the first core exceeds a utilization threshold, as if the first core was to operate above a threshold, it would be the source core.),
and determining the second core as the target core includes determining that the utilization of the second core is less than the utilization of the first core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved to a different core to increase efficiency, measured in work accomplished, corresponds to Applicant’s determining the second core as the target core includes determining that the utilization of the second core is less than the utilization of the first core, i.e., if the first core would be operating above a threshold, it would have a higher utilization than the second core, thus making the second core the target for work to be transferred to.).
Regarding Claim 16, Therien-Vajapeyam as described in Claim 13, Vajapeyam further discloses wherein the metadata contains branch prediction data (Col. 4, Lines 12-15- The micro-architectural state components 110A and 110B may include […] branch predictor tables. Please note that the state components including branch predictor tables corresponds to Applicant’s metadata containing branch prediction data. ),
TLB data (Col. 1, Lines 40-42- translation lookaside buffer (TLB) entries may be stored in data cache of the source core and may be subsequently migrated to data cache of the target core. Please note that TLB entries being stored in data cache of the source core to be subsequently migrated to the data cache of the target core corresponds to Applicant’s metadata containing TLB data.),
Therien further discloses prefetch data ([0017] the processing cores 102 include a front end 104, […] the front end 104 is operable to fetch instructions from an instruction cache (not depicted) and schedule the fetched instructions for execution. Please note that fetching instructions and scheduling the fetched instructions for execution as part of the front end 104 of the processing cores 102 corresponds to Applicant’s metadata including prefetch data, i.e., the fetched instructions scheduled to be executed by the particular core.),
and power control data ([0021] The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in […] power use. Please note that the power use of particular processing cores 102 being measured by the placement controller 134 corresponds to Applicant’s power control data of the metadata.).
Regarding Claim 17, Therien discloses A multi-core processor ([0016] a multicore processor used in conjunction with at least one embodiment […] a processor 101 includes a core region 120 and an uncore 122. In some embodiments, the core region 120 includes multiple processing cores 102, but disclosed functionality may be applicable to single core processors in a multi-processor system. Please note that the multicore processor 101, including multiple processing cores 102, corresponds to Applicant’s multi-core processor.) comprising:
a scheduler ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Please note that the placement controller 134 corresponds to Applicant’s scheduler.);
and a first core that includes first metadata save logics configured to save first metadata obtained during execution of a first task that is a subject of a task migration instruction of the scheduler based on receiving the task migration instruction and transmit the first metadata to an external memory ([0031] a core migration flow can include the following operations: Save core states of the cores to be migrated to C6 storage.; [0034] In block 314, the source core 302 saves its core state (e.g., instruction location, register values and/or other state data) to a core state (or context and identity) storage, such as C6 storage. Please note that saving the core state of the core to be migrated, in this case, that of the first core, including various state data, to the core state storage for context and identity in the C6 storage as part of a core migration flow, corresponds to Applicant’s first core that includes first metadata save logics configured to save first metadata obtained during execution of a first task that is a subject of a task migration instruction of the scheduler based on receiving the task migration instruction and transmit the first metadata to an external memory. ),
Therien does not explicitly disclose and first metadata restore logics configured to receive second metadata to be used to execute a second task that is the subject of a task execution instruction of the scheduler, from the external memory based on receiving the task execution instruction, and restore the second metadata.
However, Vajapeyam discloses and first metadata restore logics configured to receive second metadata to be used to execute a second task that is the subject of a task execution instruction of the scheduler, from the external memory based on receiving the task execution instruction, and restore the second metadata (Col. 3, Lines 34-41- migrating threads across processing cores in a multi-core processor. The multi-core processor may include two or more processing cores. One or more threads are migrated from a source core to a target core selected from the two or more processing cores. In the described embodiments, a state coherence protocol is utilized to acquire selective state data from the source core while a migrated thread is executed on the target core.; Col.7, Lines 43-54- a state coherence protocol to dynamically acquire state data for thread migration from the first processing core 102 to the second processing core 104 of the multi-core processor 100. […] In some example embodiments, the first processing core 102 includes an architectural state component such as a register file 200A and the second processing core 104 includes a register file 200B. For ease of description, a register file can be utilized to depict an architectural state component of each of the processing cores 102 and 104. Please note that acquiring state data for thread migration from the first processing core 102 to the second processing core 104, including a register file 200A that depicts the architectural state component of processing core 102, corresponds to Applicant’s transmitting the conversion data to a memory.). Please note that migrated threads from a source core to a target core selected from the two or more processing cores, acquiring selective state data from the source core while a migrated thread is executed on the target core, where each core has a respective register file depicting its architectural state component, corresponds to Applicant’s first metadata restore logics configured to receive second metadata to be used to execute a second task that is the subject of a task execution instruction of the scheduler, from the external memory based on receiving the task execution instruction, and restore the second metadata. A person of ordinary skill in the art prior to the filing date of the invention would be able to utilize this system to restore second metadata received from the external memory to execute a second task, given the state coherence mechanisms implemented.).
Therien and Vajapeyam are both considered to be analogous to the claimed invention because they are in the same field of computer thread migration across cores. Therefore, it would have been obvious to someone of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Therien to incorporate the teachings of Vajapeyam to modify the multi-core processor system comprising a scheduler and a first core that includes first metadata save logics configured to save first metadata obtained during execution of a first task that is a subject of a task migration instruction of the scheduler based on receiving the task migration instruction and transmits the first metadata to an external memory to have first metadata restore logics configured to receive second metadata to be used to execute a second task that is the subject of a task execution instruction of the scheduler, from the external memory based on receiving the task execution instruction, and restore the second metadata, allowing for improved dynamic acquisition of the state data from the other core and resulting in improved system adaptability, as described in Vajapeyam.
Regarding Claim 18, Therien-Vajapeyam as described in Claim 17, Therien further discloses a second core that includes second metadata restore logics configured to receive the first metadata to be used to execute the first task, from the external memory, based on a task execution instruction of the scheduler, and restore the first metadata ([0023] the PCU 124 can initiate a sequence that saves the core's context, restores the context to a different core, and redirects a local APIC ID of the previous core to the new core. This migration can occur at the core or thread level.; [0029] When a core is placed into a power-saving state, the core software context and identity (or core state) can be saved to the C6 storage. A core software context and identity can include instruction locations, register values, APIC ID, etc. By saving the core context and identity, a core can transition into a low-power or even an off state in which the core has little or no activity, thermal activity and/or power draw. When resuming, the core can restore the core context and identity and resume processing. Please note that another core, i.e., the second core, restoring the values and resuming processing based on the saved first core context and identity, including the instruction locations, register values, etc, as part of a migration sequence corresponds to Applicant’s second core that includes second metadata restore logics configured to receive the first metadata to be used to execute the first task, from the external memory, based on a task execution instruction of the scheduler, and restore the first metadata.).
Regarding Claim 19, Therien-Vajapeyam as described in Claim 17, Therien further discloses wherein the scheduler is configured to transmit the task migration instruction and the task execution instruction based on a utilization of the first core ([0021] a power control unit (PCU) 124 includes a placement controller 134. A power control unit is a microcontroller or programmable state machine that consumes power related telemetry (sometimes continuously) from components on the CPU in order to manage power, frequency and temperature of the components. The placement controller 134 can monitor workloads of the processing cores 102 and determine which work can be moved to a different core to increase efficiency. Efficiency can be measured in thermal output, power use and/or work accomplished. For example, efficiency can be increased by moving threads between cores that differ due to in-die variation (lower thermal output, decreased power usage, lifetime use management or more work performed). Efficiency can be increased by maintaining a low-voltage operation of a core by not providing a workload above a threshold (i.e., moving threads between cores to prevent a core from operating above a threshold, which is also known as “stressing” a core). Please note that determining the work that can be moved from a core, i.e., the first core, to a different core to increase efficiency, measured in work accomplished, to prevent the first core from operating above a threshold, and the placement controller 134 determining the work that can be moved to a different core corresponds to Applicant’s scheduler being configured to transmit the task migration instruction and the task execution instruction based on a utilization of the first core.).
Regarding Claim 20, Therien-Vajapeyam as described in Claim 17, Therien further discloses the first core further includes architectural logics configured to transmit information indicating a point at which the execution of the first task was stopped, to the external memory, based on the task migration instruction of the scheduler ([0029] When a core is placed into a power-saving state, the core software context and identity (or core state) can be saved to the C6 storage. A core software context and identity can include instruction locations, register values, APIC ID, etc. By saving the core context and identity, a core can transition into a low-power or even an off state in which the core has little or no activity, thermal activity and/or power draw. When resuming, the core can restore the core context and identity and resume processing. Please note that saving the core context and identity, including the instruction locations, register values, etc, that allows a core to restore these values and resume processing, corresponds to Applicant’s first core further including architectural logics configured to transmit information indicating a point at which the execution of the first task was stopped, to the external memory, based on the task migration instruction of the scheduler, as it allows for resuming the processing at the point at which the execution was initially stopped by restoring the core context and identity.).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Weissmann et al. (US 20210200656 A1) discloses migrating threads between processors with different core types, branch prediction, instruction fetching, a TLB, regulating the power state of cores, scheduling threads based on a state that balances performance and power consumption, in addition to thread specific characteristics, migrating a running thread, and saving and restoring metadata about threads (see [0089, 0105, 0148, 0166, 0199]).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FARAZ T AKBARI whose telephone number is (571)272-4166. The examiner can normally be reached Monday-Thursday 9:30am-7:30pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, April Blair can be reached at (571)270-1014. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FARAZ T AKBARI/Examiner, Art Unit 2196
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196
Prosecution Insights