DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu et al. (US Patent Appl. Pub. No. 2016/0149011 A1).
[Re claim 1] Hu discloses the semiconductor device isolation structure comprising: a substrate (502); a DTI region (514) extending to a predetermined depth within the substrate from a surface of the substrate; a buried layer (506 or 548) of a second conductivity type (N-type) disposed within the substrate; and an ion implantation region (550) of a second conductivity type (N-type) disposed under the buried layer within the substrate (see figure 5 and paragraph [0034]-[0037]).
[Re claim 2] Hu discloses the semiconductor device wherein the ion implantation region (550) has a low-concentration doped region of a second conductivity-type impurity compared to the buried layer (548) (see paragraph [0034]).
[Re claim 3] Hu discloses the semiconductor device wherein the ion implantation region is formed within the substrate, and the buried layer is formed over the ion implantation region (see figure 5 and paragraph [0034]-[0037]). The limitation of “the ion implantation region is formed within the substrate before the buried layer is formed” are limitations directed to details of the device being made by process and therefore do not impart significant patentable weight. See MPEP 2113(I). "[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process”.
[Re claim 4] Hu discloses the semiconductor device wherein the DTI region comprises: a liner (516) disposed in contact with a portion of the substrate adjacent thereto; a sidewall disposed on the liner; and a gap-fill region (522 and 524) disposed on the sidewall (see figure 5 and paragraph [0035]).
[Re claim 5] Hu discloses the semiconductor device wherein the gap-fill region (522 and 524) comprises polysilicon doped with a first conductivity-type impurity (see paragraph [0035]).
[Re claim 6] Hu discloses the semiconductor device wherein the gap-fill region (522 and 524) has a lower surface in contact with a portion (528) of the substrate under the gap-fill region (see figure 5 and paragraph [0036]).
[Re claim 7] Hu discloses the semiconductor device further comprising: a deep well region (552) disposed above the buried layer within the substrate (see figure 5 paragraph [0037]).
Allowable Subject Matter
Claim 8 objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all the limitations of the base claim and any intervening claims.
Claim 9-20 allowed.
The following is an examiner's statement of reasons for allowance: Claim 9 allowable because of the closest prior art, either singly or in combination, fails to anticipate or render obvious, the device, wherein an ion implantation region of a second conductivity type disposed within the substrate; a buried layer of a second conductivity type having at least a portion disposed in the first epitaxial layer, the buried layer being disposed on the ion implantation region; a second epitaxial layer disposed on the first epitaxial layer; and a DTI region extending from a surface of the second epitaxial layer to a predetermined depth within the substrate. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
The following is an examiner's statement of reasons for allowance: Claim 14 allowable because of the closest prior art, either singly or in combination, fails to anticipate or render obvious, the method, the step of forming an ion implantation region in a substrate; forming a first epitaxial layer on the substrate in which the ion implantation region is formed; forming a buried layer in the first epitaxial layer; forming one or more additional epitaxial layers on the first epitaxial layer; forming a multilayer film on a top epitaxial layer of the one or more additional epitaxial layers; exposing a portion of the top epitaxial layer by etching one side of the multilayer film; forming a deep trench by etching the one or more additional epitaxial layers, the first epitaxial layer, and the substrate; and forming a DTI region within the deep trench. These features in combination with the other elements of the claim are neither disclosed nor suggested by the prior art of record.
Claims 10-13 and 15-20 depend on claim 9 or 14 so they are allowed for the same reason.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KYOUNG LEE whose telephone number is (571)272-1982. The examiner can normally be reached M to F, 10am to 6pm.
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/KYOUNG LEE/ Primary Examiner, Art Unit 2817
